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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_rst/] [_primary.vhd] - Blame information for rev 2

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library verilog;
use verilog.vl_types.all;
entity ac97_rst is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        rst_force       : in     vl_logic;
        ps_ce           : out    vl_logic;
        \ac97_rst_\     : out    vl_logic
    );
end ac97_rst;

Line No.	Rev	Author	Line
1	2	dimamali	`library verilog;`
2			`use verilog.vl_types.all;`
3			`entity ac97_rst is`
4			`port(`
5			`clk : in vl_logic;`
6			`rst : in vl_logic;`
7			`rst_force : in vl_logic;`
8			`ps_ce : out vl_logic;`
9			`\ac97_rst_\ : out vl_logic`
10			`);`
11			`end ac97_rst;`

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-gr-xc3s-1500/] [modelsim/] [opencores/] [ac97_rst/] [_primary.vhd] - Blame information for rev 2