OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-memec-v2mb1000/] [config.help] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
 
2
 
3
Prompt for target technology
4
CONFIG_SYN_INFERRED
5
  Selects the target technology for memory and pads.
6
  The following are available:
7
 
8
  - Inferred: Generic FPGA or ASIC targets if your synthesis tool
9
    is capable of inferring RAMs and pads automatically.
10
 
11
  - Actel ProAsic/P/3 and Axellerator FPGAs
12
  - Altera: Any Altera FPGA family
13
  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
14
  - IHP25: IHP 0.25 um CMOS
15
  - Lattice : EC/ECP/XP FPGAs
16
  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
17
  - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
18
  - Xilinx-Spartan3E: Xilinx Spartan3E libraries
19
  - Xilinx-Virtex/E: Xilinx Virtex/E libraries
20
  - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
21
 
22
 
23
Ram library
24
CONFIG_MEM_VIRAGE
25
  Select RAM generators for ASIC targets.
26
 
27
Infer ram
28
CONFIG_SYN_INFER_RAM
29
  Say Y here if you want the synthesis tool to infer your
30
  RAM automatically. Say N to directly instantiate technology-
31
  specific RAM cells for the selected target technology package.
32
 
33
Infer pads
34
CONFIG_SYN_INFER_PADS
35
  Say Y here if you want the synthesis tool to infer pads.
36
  Say N to directly instantiate technology-specific pads from
37
  the selected target technology package.
38
 
39
No async reset
40
CONFIG_SYN_NO_ASYNC
41
  Say Y here if you disable asynchronous reset in some of the IP cores.
42
  Might be necessary if the target library does not have cells with
43
  asynchronous set/reset.
44
 
45
 
46
Use Virtex CLKDLL for clock synchronisation
47
CONFIG_CLK_INFERRED
48
  Certain target technologies include clock generators to scale or
49
  phase-adjust the system and SDRAM clocks. This is currently supported
50
  for Xilinx and Altera FPGAs. Depending on technology, you can select
51
  to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), the
52
  Xilinx DCM (Virtex-2, Spartan3, Virtex-4), or the Altera ALTDLL
53
  (Stratix, Cyclone). Choose the 'inferred' option if you are not
54
  using Xilinx or Altera FPGAs.
55
 
56
  Using a technology specific clock generator is necessary to
57
  re-syncronize the SDRAM clock. For this to work, connect the
58
  external SDCLK signal with PLLREF.
59
 
60
Clock multiplier
61
CONFIG_CLK_MUL
62
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
63
  be multiplied with a factor of 2 - 32, and divided by a factor of
64
  1 - 32. This makes it possible to generate almost any desired
65
  processor frequency. When using the Xilinx CLKDLL generator,
66
  the resulting frequency scale factor (mul/div) must be one of
67
  1/2, 1 or 2.
68
 
69
  WARNING: The resulting clock must be within the limits specified
70
  by the target FPGA family.
71
 
72
Clock divider
73
CONFIG_CLK_DIV
74
  When using the Xilinx DCM or Altera ALTPLL, the system clock can
75
  be multiplied with a factor of 2 - 32, and divided by a factor of
76
  1 - 32. This makes it possible to generate almost any desired
77
  processor frequency. When using the Xilinx CLKDLL generator,
78
  the resulting frequency scale factor (mul/div) must be one of
79
  1/2, 1 or 2.
80
 
81
  WARNING: The resulting clock must be within the limits specified
82
  by the target FPGA family.
83
 
84
System clock multiplier
85
CONFIG_CLKDLL_1_2
86
  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
87
  or 2.0. Useful when the target board has an oscillator with a too high
88
  (or low) frequency for your design. The divided clock will be used as the
89
  main clock for the whole processor (except PCI and ethernet clocks).
90
 
91
System clock multiplier
92
CONFIG_DCM_2_3
93
  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
94
  range of factors. Useful when the target board has an oscillator with a
95
  too high (or low) frequency for your design. The divided clock will
96
  be used as the main clock for the whole processor (except PCI and
97
  ethernet clocks). NOTE: the resulting frequency must be at least
98
  24 MHz or the DCM and ALTDLL might not work.
99
 
100
Enable CLKDLL for PCI clock
101
CONFIG_PCI_CLKDLL
102
  Say Y here to re-synchronize the PCI clock using a
103
  Virtex BUFGDLL macro. Will improve PCI clock-to-output
104
  delays on the expense of input-setup requirements.
105
 
106
Use PCI clock system clock
107
CONFIG_PCI_SYSCLK
108
  Say Y here to the PCI clock to generate the system clock.
109
  The PCI clock can be scaled using the DCM or CLKDLL to
110
  generate a suitable processor clock.
111
 
112
External SDRAM clock feedback
113
CONFIG_CLK_NOFB
114
  Say Y here to disable the external clock feedback to synchronize the
115
  SDRAM clock. This option is necessary if your board or design does not
116
  have an external clock feedback that is connected to the pllref input
117
  of the clock generator.
118
Number of processors
119
CONFIG_PROC_NUM
120
  The number of processor cores. The LEON3MP design can accomodate
121
  up to 4 LEON3 processor cores. Use 1 unless you know what you are
122
  doing ...
123
 
124
Number of SPARC register windows
125
CONFIG_IU_NWINDOWS
126
  The SPARC architecture (and LEON) allows 2 - 32 register windows.
127
  However, any number except 8 will require that you modify and
128
  recompile your run-time system or kernel. Unless you know what
129
  you are doing, use 8.
130
 
131
SPARC V8 multiply and divide instruction
132
CONFIG_IU_V8MULDIV
133
  If you say Y here, the SPARC V8 multiply and divide instructions
134
  will be implemented. The instructions are: UMUL, UMULCC, SMUL,
135
  SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
136
  integer multiplications and divisions, significant performance
137
  increase can be achieved. Emulated floating-point operations will
138
  also benefit from this option.
139
 
140
  By default, the gcc compiler does not emit multiply or divide
141
  instructions and your code must be compiled with -mv8 to see any
142
  performance increase. On the other hand, code compiled with -mv8
143
  will generate an illegal instruction trap when executed on processors
144
  with this option disabled.
145
 
146
  The divider consumes approximately 2 kgates, the multiplier 6 kgates.
147
 
148
Multiplier latency
149
CONFIG_IU_MUL_LATENCY_4
150
  The multiplier used for UMUL/SMUL instructions is implemented
151
  with a 16x16 multiplier which is iterated 4 times. This leads
152
  to a 4-cycle latency for multiply operations. To improve timing,
153
  a pipeline stage can be inserted into the 16x16 multiplier which
154
  will lead to a 5-cycle latency for the multiply oprations.
155
 
156
Multiplier latency
157
CONFIG_IU_MUL_MAC
158
  If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
159
  instructions will be enabled. The instructions implement a
160
  single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
161
  The details of these instructions can be found in the LEON manual,
162
 
163
Single vector trapping
164
CONFIG_IU_SVT
165
  Single-vector trapping is a SPARC V8e option to reduce code-size
166
  in small applications. If enabled, the processor will jump to
167
  the address of trap 0 (tt = 0x00) for all traps. No trap table
168
  is then needed. The trap type is present in %psr.tt and must
169
  be decoded by the O/S. Saves 4 Kbyte of code, but increases
170
  trap and interrupt overhead. Currently, the only O/S supporting
171
  this option is eCos. To enable SVT, the O/S must also set bit 13
172
  in %asr17.
173
 
174
Load latency
175
CONFIG_IU_LDELAY
176
  Defines the pipeline load delay (= pipeline cycles before the data
177
  from a load instruction is available for the next instruction).
178
  One cycle gives best performance, but might create a critical path
179
  on targets with slow (data) cache memories. A 2-cycle delay can
180
  improve timing but will reduce performance with about 5%.
181
 
182
Reset address
183
CONFIG_IU_RSTADDR
184
  By default, a SPARC processor starts execution at address 0.
185
  With this option, any 4-kbyte aligned reset start address can be
186
  choosen. Keep at 0 unless you really know what you are doing.
187
 
188
Power-down
189
CONFIG_PWD
190
  Say Y here to enable the power-down feature of the processor.
191
  Might reduce the maximum frequency slightly on FPGA targets.
192
  For details on the power-down operation, see the LEON3 manual.
193
 
194
Hardware watchpoints
195
CONFIG_IU_WATCHPOINTS
196
  The processor can have up to 4 hardware watchpoints, allowing to
197
  create both data and instruction breakpoints at any memory location,
198
  also in PROM. Each watchpoint will use approximately 500 gates.
199
  Use 0 to disable the watchpoint function.
200
 
201
Floating-point enable
202
CONFIG_FPU_ENABLE
203
  Say Y here to enable the floating-point interface for the MEIKO
204
  or GRFPU. Note that no FPU's are provided with the GPL version
205
  of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
206
  cores and must be obtained separately.
207
 
208
FPU selection
209
CONFIG_FPU_GRFPU
210
  Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
211
  Meiko FPU core. All cores  are fully IEEE-754 compatible and support
212
  all SPARC FPU instructions.
213
 
214
GRFPU Multiplier
215
CONFIG_FPU_GRFPU_INFMUL
216
  On FPGA targets choose inferred multiplier. For ASIC implementations
217
  choose between Synopsys Design Ware (DW) multiplier or Module
218
  Generator (ModGen) multiplier. DW multiplier gives better results
219
  (smaller area  and better timing) but requires DW license. ModGen
220
  multiplier is part of GRLIB and does not require license.
221
 
222
GRFPC Configuration
223
CONFIG_FPU_GRFPC0
224
  Configures the GRFPU-LITE controller.
225
 
226
  In simple configuration controller executes FP instructions
227
  in parallel with  integer instructions. FP operands are fetched
228
  in the register file stage and the result is written in the write
229
  stage. This option uses least area resources.
230
 
231
  Data forwarding configuration gives ~ 10 % higher FP performance than
232
  the simple configuration by adding data forwarding between the pipeline
233
  stages.
234
 
235
  Non-blocking controller allows FP load and store instructions to
236
  execute in parallel with FP instructions. The performance increase is
237
  ~ 20 % for FP applications. This option uses most logic resources and
238
  is suitable for ASIC implementations.
239
 
240
Enable Instruction cache
241
CONFIG_ICACHE_ENABLE
242
  The instruction cache should always be enabled to allow
243
  maximum performance. Some low-end system might want to
244
  save area and disable the cache, but this will reduce
245
  the performance with a factor of 2 - 3.
246
 
247
Enable Data cache
248
CONFIG_DCACHE_ENABLE
249
  The data cache should always be enabled to allow
250
  maximum performance. Some low-end system might want to
251
  save area and disable the cache, but this will reduce
252
  the performance with a factor of 2 at least.
253
 
254
Instruction cache associativity
255
CONFIG_ICACHE_ASSO1
256
  The instruction cache can be implemented as a multi-set cache with
257
  1 - 4 sets. Higher associativity usually increases the cache hit
258
  rate and thereby the performance. The downside is higher power
259
  consumption and increased gate-count for tag comparators.
260
 
261
  Note that a 1-set cache is effectively a direct-mapped cache.
262
 
263
Instruction cache set size
264
CONFIG_ICACHE_SZ1
265
  The size of each set in the instuction cache (kbytes). Valid values
266
  are 1 - 64 in binary steps. Note that the full range is only supported
267
  by the generic and virtex2 targets. Most target packages are limited
268
  to 2 - 16 kbyte. Large set size gives higher performance but might
269
  affect the maximum frequency (on ASIC targets). The total instruction
270
  cache size is the number of set multiplied with the set size.
271
 
272
Instruction cache line size
273
CONFIG_ICACHE_LZ16
274
  The instruction cache line size. Can be set to either 16 or 32
275
  bytes per line. Instruction caches typically benefit from larger
276
  line sizes, but on small caches it migh be better with 16 bytes/line
277
  to limit eviction miss rate.
278
 
279
Instruction cache replacement algorithm
280
CONFIG_ICACHE_ALGORND
281
  Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
282
  algorithm selects the set to evict randomly. The least-recently-used
283
  (LRR) algorithm evicts the set least recently replaced. The least-
284
  recently-used (LRU) algorithm evicts the set least recently accessed.
285
  The random algorithm uses a simple 1- or 2-bit counter to select
286
  the eviction set and has low area overhead. The LRR scheme uses one
287
  extra bit in the tag ram and has therefore also low area overhead.
288
  However, the LRR scheme can only be used with 2-set caches. The LRU
289
  scheme has typically the best performance but also highest area overhead.
290
  A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
291
  per line, and a 4-set LRU uses 5 flip-flops per line to store the access
292
  history.
293
 
294
Instruction cache locking
295
CONFIG_ICACHE_LOCK
296
  Say Y here to enable cache locking in the instruction cache.
297
  Locking can be done on cache-line level, but will increase the
298
  width of the tag ram with one bit. If you don't know what
299
  locking is good for, it is safe to say N.
300
 
301
Data cache associativity
302
CONFIG_DCACHE_ASSO1
303
  The data cache can be implemented as a multi-set cache with
304
  1 - 4 sets. Higher associativity usually increases the cache hit
305
  rate and thereby the performance. The downside is higher power
306
  consumption and increased gate-count for tag comparators.
307
 
308
  Note that a 1-set cache is effectively a direct-mapped cache.
309
 
310
Data cache set size
311
CONFIG_DCACHE_SZ1
312
  The size of each set in the data cache (kbytes). Valid values are
313
  1 - 64 in binary steps. Note that the full range is only supported
314
  by the generic and virtex2 targets. Most target packages are limited
315
  to 2 - 16 kbyte. A large cache gives higher performance but the
316
  data cache is timing critical an a too large setting might affect
317
  the maximum frequency (on ASIC targets). The total data cache size
318
  is the number of set multiplied with the set size.
319
 
320
Data cache line size
321
CONFIG_DCACHE_LZ16
322
  The data cache line size. Can be set to either 16 or 32 bytes per
323
  line. A smaller line size gives better associativity and higher
324
  cache hit rate, but requires a larger tag memory.
325
 
326
Data cache replacement algorithm
327
CONFIG_DCACHE_ALGORND
328
  See the explanation for instruction cache replacement algorithm.
329
 
330
Data cache locking
331
CONFIG_DCACHE_LOCK
332
  Say Y here to enable cache locking in the data cache.
333
  Locking can be done on cache-line level, but will increase the
334
  width of the tag ram with one bit. If you don't know what
335
  locking is good for, it is safe to say N.
336
 
337
Data cache snooping
338
CONFIG_DCACHE_SNOOP
339
  Say Y here to enable data cache snooping on the AHB bus. Is only
340
  useful if you have additional AHB masters such as the DSU or a
341
  target PCI interface. Note that the target technology must support
342
  dual-port RAMs for this option to be enabled. Dual-port RAMS are
343
  currently supported on Virtex/2, Virage and Actel targets.
344
 
345
Data cache snooping implementation
346
CONFIG_DCACHE_SNOOP_FAST
347
  The default snooping implementation is 'slow', which works if you
348
  don't have AHB slaves in cacheable areas capable of zero-waitstates
349
  non-sequential write accesses. Otherwise use 'fast' and suffer a
350
  few kgates extra area. This option is currently only needed in
351
  multi-master systems with the SSRAM or DDR memory controllers.
352
 
353
Fixed cacheability map
354
CONFIG_CACHE_FIXED
355
  If this variable is 0, the cacheable memory regions are defined
356
  by the AHB plug&play information (default). To overriden the
357
  plug&play settings, this variable can be set to indicate which
358
  areas should be cached. The value is treated as a 16-bit hex value
359
  with each bit defining if a 256 Mbyte segment should be cached or not.
360
  The right-most (LSB) bit defines the cacheability of AHB address
361
 
362
  3840 - 4096 MByte. If the bit is set, the corresponding area is
363
  cacheable. A value of 00F3 defines address 0 - 0x20000000 and
364
  0x40000000 - 0x80000000 as cacheable.
365
 
366
Local data ram
367
CONFIG_DCACHE_LRAM
368
  Say Y here to add a local ram to the data cache controller.
369
  Accesses to the ram (load/store) will be performed at 0 waitstates
370
  and store data will never be written back to the AHB bus.
371
 
372
Size of local data ram
373
CONFIG_DCACHE_LRAM_SZ1
374
  Defines the size of the local data ram in Kbytes. Note that most
375
  technology libraries do not support larger rams than 16 Kbyte.
376
 
377
Start address of local data ram
378
CONFIG_DCACHE_LRSTART
379
  Defines the 8 MSB bits of start address of the local data ram.
380
  By default set to 8f (start address = 0x8f000000), but any value
381
  (except 0) is possible. Note that the local data ram 'shadows'
382
  a 16 Mbyte block of the address space.
383
 
384
MMU enable
385
CONFIG_MMU_ENABLE
386
  Say Y here to enable the Memory Management Unit.
387
 
388
MMU split icache/dcache table lookaside buffer
389
CONFIG_MMU_COMBINED
390
  Select "combined" for a combined icache/dcache table lookaside buffer,
391
  "split" for a split icache/dcache table lookaside buffer
392
 
393
MMU tlb replacement scheme
394
CONFIG_MMU_REPARRAY
395
  Select "LRU" to use the "least recently used" algorithm for TLB
396
  replacement, or "Increment" for a simple incremental replacement
397
  scheme.
398
 
399
Combined i/dcache tlb
400
CONFIG_MMU_I2
401
  Select the number of entries for the instruction TLB, or the
402
  combined icache/dcache TLB if such is used.
403
 
404
Split tlb, dcache
405
CONFIG_MMU_D2
406
  Select the number of entries for the dcache TLB.
407
 
408
mmu snooping
409
CONFIG_DCACHE_MMUSNOOP
410
  Save physical tags along with virtual tags. This is
411
  needed on smp systems with MMU enabled. Adds extra
412
  RAM to store the physical address beside the
413
  simple snoopings dualport ram. If disabled
414
  snooping will only work with MMU disabled.
415
 
416
DSU enable
417
CONFIG_DSU_ENABLE
418
  The debug support unit (DSU) allows non-intrusive debugging and tracing
419
  of both executed instructions and AHB transfers. If you want to enable
420
  the DSU, say Y here and select the configuration below.
421
 
422
Trace buffer enable
423
CONFIG_DSU_TRACEBUF
424
  Say Y to enable the trace buffer. The buffer is not necessary for
425
  debugging, only for tracing instructions and data transfers.
426
 
427
Enable instruction tracing
428
CONFIG_DSU_ITRACE
429
  If you say Y here, an instruction trace buffer will be implemented
430
  in each processor. The trace buffer will trace executed instructions
431
  and their results, and place them in a circular buffer. The buffer
432
  can be read out by any AHB master, and in particular by the debug
433
  communication link.
434
 
435
Size of trace buffer
436
CONFIG_DSU_ITRACESZ1
437
  Select the buffer size (in kbytes) for the instruction trace buffer.
438
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
439
  need 2 kbyte.
440
 
441
Enable AHB tracing
442
CONFIG_DSU_ATRACE
443
  If you say Y here, an AHB trace buffer will be implemented in the
444
  debug support unit processor. The AHB buffer will trace all transfers
445
  on the AHB bus and save them in a circular buffer. The trace buffer
446
  can be read out by any AHB master, and in particular by the debug
447
  communication link.
448
 
449
Size of trace buffer
450
CONFIG_DSU_ATRACESZ1
451
  Select the buffer size (in kbytes) for the AHB trace buffer.
452
  Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
453
  need 2 kbyte.
454
 
455
 
456
IU assembly printing
457
CONFIG_IU_DISAS
458
  Enable printing of executed instructions to the console.
459
 
460
IU assembly printing in netlist
461
CONFIG_IU_DISAS_NET
462
  Enable printing of executed instructions to the console also
463
  when simulating a netlist. NOTE: with this option enabled, it
464
  will not be possible to pass place&route.
465
 
466
32-bit program counters
467
CONFIG_DEBUG_PC32
468
  Since the LSB 2 bits of the program counters always are zero, they are
469
  normally not implemented. If you say Y here, the program counters will
470
  be implemented with full 32 bits, making debugging of the VHDL model
471
  much easier. Turn of this option for synthesis or you will be wasting
472
  area.
473
 
474
CONFIG_AHB_DEFMST
475
  Sets the default AHB master (see AMBA 2.0 specification for definition).
476
  Should not be set to a value larger than the number of AHB masters - 1.
477
  For highest processor performance, leave it at 0.
478
 
479
Default AHB master
480
CONFIG_AHB_RROBIN
481
  Say Y here to enable round-robin arbitration of the AHB bus. A N will
482
  select fixed priority, with the master with the highest bus index having
483
  the highest priority.
484
 
485
Support AHB split-transactions
486
CONFIG_AHB_SPLIT
487
  Say Y here to enable AHB split-transaction support in the AHB arbiter.
488
  Unless you actually have an AHB slave that can generate AHB split
489
  responses, say N and save some gates.
490
 
491
Default AHB master
492
CONFIG_AHB_IOADDR
493
  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
494
  in the plug&play extentions of the AMBA bus. Should be kept to FFF
495
  unless you really know what you are doing.
496
 
497
APB bridge address
498
CONFIG_APB_HADDR
499
  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
500
  kept at 800 for software compatibility.
501
 
502
 
503
DSU enable
504
CONFIG_DSU_UART
505
  Say Y to enable the AHB uart (serial-to-AHB). This is the most
506
  commonly used debug communication link.
507
 
508
JTAG Enable
509
CONFIG_DSU_JTAG
510
  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
511
  with GRMON through the boards JTAG chain at speed of 300 kbits/s.
512
  Supported JTAG cables are Xilinx Parallel Cable III and IV.
513
 
514
Ethernet DSU enable
515
CONFIG_DSU_ETH
516
  Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
517
  provides a DSU gateway between ethernet and the AHB bus. Debugging is
518
  done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
519
  enable the GRETH Ethernet MAC for this option to become active.
520
 
521
Size of EDCL trace buffer
522
CONFIG_DSU_ETHSZ1
523
  Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
524
  usually enough, while a larger buffer will increase the transfer rate.
525
  When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
526
  maximum throughput.
527
 
528
MSB IP address
529
CONFIG_DSU_IPMSB
530
  Set the MSB 16 bits of the IP address of the EDCL.
531
 
532
LSB IP address
533
CONFIG_DSU_IPLSB
534
  Set the LSB 16 bits of the IP address of the EDCL.
535
 
536
MSB ethernet address
537
CONFIG_DSU_ETHMSB
538
  Set the MSB 24 bits of the ethernet address of the EDCL.
539
 
540
LSB ethernet address
541
CONFIG_DSU_ETHLSB
542
  Set the LSB 24 bits of the ethernet address of the EDCL.
543
Leon2 memory controller
544
CONFIG_MCTRL_LEON2
545
  Say Y here to enable the LEON2 memory controller. The controller
546
  can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
547
  and SRAM is programmable to 8-, 16- or 32-bits.
548
 
549
8-bit memory support
550
CONFIG_MCTRL_8BIT
551
  If you say Y here, the PROM/SRAM memory controller will support
552
  8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
553
  Say N to save a few hundred gates.
554
 
555
16-bit memory support
556
CONFIG_MCTRL_16BIT
557
  If you say Y here, the PROM/SRAM memory controller will support
558
  16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
559
  Say N to save a few hundred gates.
560
 
561
Write strobe feedback
562
CONFIG_MCTRL_WFB
563
  If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
564
  be used to enable the data bus drivers during write cycles. This
565
  will guarantee that the data is still valid on the rising edge of
566
  the write strobe. If you say N, the write strobes and the data bus
567
  drivers will be clocked on the rising edge, potentially creating
568
  a hold time problem in external memory or I/O. However, in all
569
  practical cases, there is enough capacitance in the data bus lines
570
  to keep the value stable for a few (many?) nano-seconds after the
571
  buffers have been disabled, making it safe to say N and remove a
572
  combinational path in the netlist that might be difficult to
573
  analyze.
574
 
575
Write strobe feedback
576
CONFIG_MCTRL_5CS
577
  If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
578
  be enabled. If you don't intend to use it, say N and save some gates.
579
 
580
SDRAM controller enable
581
CONFIG_MCTRL_SDRAM
582
  Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
583
  intend to use SDRAM, say N and save about 1 kgates.
584
 
585
SDRAM controller inverted clock
586
CONFIG_MCTRL_SDRAM_INVCLK
587
  If you say Y here, the SDRAM controller output signals will be delayed
588
  with 1/2 clock in respect to the SDRAM clock. This will allow the used
589
  of an SDRAM clock which in not strictly in phase with the internal
590
  clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
591
 
592
  On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
593
  say Y. On ASIC targets, say N and tell your foundry to balance the
594
  SDRAM clock output.
595
 
596
SDRAM separate address buses
597
CONFIG_MCTRL_SDRAM_SEPBUS
598
  Say Y here if your SDRAM is connected through separate address
599
  and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
600
  board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
601
 
602
64-bit data bus
603
CONFIG_MCTRL_SDRAM_BUS64
604
  Say Y here to enable 64-bit SDRAM data bus.
605
 
606
Page burst enable
607
CONFIG_MCTRL_PAGE
608
  Say Y here to enable SDRAM page burst operation. This will implement
609
  read operations using page bursts rather than 8-word bursts and save
610
  about 500 gates (100 LUTs). Note that not all SDRAM supports page
611
  burst, so use this option with care.
612
 
613
Programmable page burst enable
614
CONFIG_MCTRL_PROGPAGE
615
  Say Y here to enable programmable SDRAM page burst operation. This
616
  will allow to dynamically enable/disable page burst by setting
617
  bit 17 in MCFG2.
618
 
619
SDRAM controller enable
620
CONFIG_DDRSP
621
  Say Y here to enabled a 16-bit DDR266 SDRAM controller.
622
 
623
Power-on init
624
CONFIG_DDRSP_INIT
625
  Say Y here to enable the automatic DDR initialization sequence.
626
  If disabled, the sequencemust be performed in software before
627
  the DDR can be used. If unsure, say Y.
628
 
629
Memory frequency
630
CONFIG_DDRSP_FREQ
631
  Enter the frequency of the DDR clock (in MHz). The value is
632
  typically between 80 - 133, depending on system configuration.
633
  Some template design (such as the leon3-avnet-eval-lx25)
634
  calculate this value automatically and this value is not used.
635
 
636
Column bits
637
CONFIG_DDRSP_COL
638
  Select the number of colomn address bits of the DDR memory.
639
  Typical values are 8 - 11. Only needed when automatic DDR
640
  initialisation is choosen. The column size can always be
641
  programmed by software as well.
642
 
643
Chip select size
644
CONFIG_DDRSP_MBYTE
645
  Select the memory size (Mbytes) that each chip select should decode.
646
  Only needed when automatic DDR initialisation is choosen. The chip
647
  select size can always be programmed by software as well.
648
 
649
Read clock phase shift
650
CONFIG_DDRSP_RSKEW
651
  On Xilinx targets, the read clock is de-skewed and phase-shifted
652
  using a DCM connected to the feed-back clock input. On some boards,
653
  the de-skewing does not work perfectly, and some extra phase shifting
654
  must be added manually. The entered value is set to the PHASE_SHIFT
655
  generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
656
  needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
657
On-chip rom
658
CONFIG_AHBROM_ENABLE
659
  Say Y here to add a block on on-chip rom to the AHB bus. The ram
660
  provides 0-waitstates read access,  burst support, and 8-, 16-
661
  and 32-bit data size. The rom will be syntheised into block rams
662
  on Xilinx and Altera FPGA devices, and into gates on ASIC
663
  technologies. GRLIB includes a utility to automatically create
664
  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
665
  documentation for details.
666
 
667
On-chip rom address
668
CONFIG_AHBROM_START
669
  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
670
  a 1 Mbyte slot at the selected address. Default is 000, corresponding
671
  to AHB address 0x00000000. When address 0x0 is selected, the rom area
672
  of any other memory controller is set to 0x10000000 to avoid conflicts.
673
 
674
Enable pipeline register for on-chip rom
675
CONFIG_AHBROM_PIPE
676
  Say Y here to add a data pipeline register to the on-chip rom.
677
  This should be done when the rom is implemenented in (ASIC) gates,
678
  or in logic cells on FPGAs. Do not use this option when the rom is
679
  implemented in block rams. If enabled, the rom will operate with
680
  one waitstate.
681
 
682
On-chip ram
683
CONFIG_AHBRAM_ENABLE
684
  Say Y here to add a block on on-chip ram to the AHB bus. The ram
685
  provides 0-waitstates read access and 0/1 waitstates write access.
686
  All AHB burst types are supported, as well as 8-, 16- and 32-bit
687
  data size.
688
 
689
On-chip ram size
690
CONFIG_AHBRAM_SZ1
691
  Set the size of the on-chip AHB ram. The ram is infered/instantiated
692
  as four byte-wide ram slices to allow byte and half-word write
693
  accesses. It is therefore essential that the target package can
694
  infer byte-wide rams. This is currently supported on the generic,
695
  virtex, virtex2, proasic and axellerator targets.
696
 
697
On-chip ram address
698
CONFIG_AHBRAM_START
699
  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
700
  a 1 Mbyte slot at the selected address. Default is A00, corresponding
701
  to AHB address 0xA0000000.
702
 
703
Gaisler Ethernet MAC enable
704
CONFIG_GRETH_ENABLE
705
  Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has
706
  one AHB master interface to read and write packets to memory, and one
707
  APB slave interface for accessing the control registers.
708
 
709
Gaisler Ethernet 1G MAC enable
710
CONFIG_GRETH_GIGA
711
  Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .
712
  The 1G MAC is only available in the commercial version of GRLIB,
713
  so do NOT enable it if you are using the GPL version.
714
 
715
CONFIG_GRETH_FIFO4
716
  Set the depth of the receive and transmit FIFOs in the MAC core.
717
  The MAC core will perform AHB burst read/writes with half the
718
  size of the FIFO depth.
719
 
720
 
721
UART1 enable
722
CONFIG_UART1_ENABLE
723
  Say Y here to enable UART1, or the console UART. This is needed to
724
  get any print-out from LEON3 systems regardless of operating system.
725
 
726
UART1 FIFO
727
CONFIG_UA1_FIFO1
728
  The UART has configurable transmitt and receive FIFO's, which can
729
  be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
730
  maximum throughput.
731
 
732
 
733
LEON3 interrupt controller
734
CONFIG_IRQ3_ENABLE
735
  Say Y here to enable the LEON3 interrupt controller. This is needed
736
  if you want to be able to receive interrupts. Operating systems like
737
  Linux, RTEMS and eCos needs this option to be enabled. If you intend
738
  to use the Bare-C run-time and not use interrupts, you could disable
739
  the interrupt controller and save about 500 gates.
740
 
741
LEON3 interrupt controller broadcast
742
CONFIG_IRQ3_BROADCAST_ENABLE
743
  If enabled the broadcast register is used to determine which
744
  interrupt should be sent to all cpus instead of just the first
745
  one that consumes it.
746
Timer module enable
747
CONFIG_GPT_ENABLE
748
  Say Y here to enable the Modular Timer Unit. The timer unit consists
749
  of one common scaler and up to 7 independent timers. The timer unit
750
  is needed for Linux, RTEMS, eCos and the Bare-C run-times.
751
 
752
Timer module enable
753
CONFIG_GPT_NTIM
754
  Set the number of timers in the timer unit (1 - 7).
755
 
756
Scaler width
757
CONFIG_GPT_SW
758
  Set the width if the common pre-scaler (2 - 16 bits). The scaler
759
  is used to divide the system clock down to 1 MHz, so 8 bits should
760
  be sufficient for most implementations (allows clocks up to 256 MHz).
761
 
762
Timer width
763
CONFIG_GPT_TW
764
  Set the width if the timers (2 - 32 bits). 32 bits is recommended
765
  for the Bare-C run-time, lower values (e.g. 16 bits) can work with
766
  RTEMS and Linux.
767
 
768
Timer Interrupt
769
CONFIG_GPT_IRQ
770
  Set the interrupt number for the first timer. Remaining timers will
771
  have incrementing interrupts, unless the separate-interrupts option
772
  below is disabled.
773
 
774
Watchdog enable
775
CONFIG_GPT_WDOGEN
776
  Say Y here to enable the watchdog functionality in the timer unit.
777
 
778
Watchdog time-out value
779
CONFIG_GPT_WDOG
780
  This value will be loaded in the watchdog timer at reset.
781
 
782
GPIO port
783
CONFIG_GRGPIO_ENABLE
784
  Say Y here to enable a general purpose I/O port. The port can be
785
  configured from 1 - 32 bits, whith each port signal individually
786
  programmable as input or output. The port signals can also serve
787
  as interrupt inputs.
788
 
789
GPIO port witdth
790
CONFIG_GRGPIO_WIDTH
791
  Number of bits in the I/O port. Must be in the range of 1 - 32.
792
 
793
GPIO interrupt mask
794
CONFIG_GRGPIO_IMASK
795
  The I/O port interrupt mask defines which bits in the I/O port
796
  should be able to create an interrupt.
797
 
798
Text-mode VGA
799
CONFIG_VGA_ENABLE
800
  Say Y here to enable a simple text-mode VGA controller. The controller
801
  generate 48x36 characters on a 640x480 pixel screen. The pixel clock
802
  is 25 MHz.
803
 
804
SVGA frame buffer
805
CONFIG_SVGA_ENABLE
806
  Say Y here to enable a graphical frame buffer. The frame buffer
807
  can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
808
  colour depth.
809
 
810
PS2 KBD interface
811
CONFIG_KBD_ENABLE
812
  Say Y here to enable a PS/2 keyboard or mouse interface.
813
 
814
UART debugging
815
CONFIG_DEBUG_UART
816
  During simulation, the output from the UARTs is printed on the
817
  simulator console. Since the ratio between the system clock and
818
  UART baud-rate is quite high, simulating UART output will be very
819
  slow. If you say Y here, the UARTs will print a character as soon
820
  as it is stored in the transmitter data register. The transmitter
821
  ready flag will be permanently set, speeding up simulation. However,
822
  the output on the UART tx line will be garbled.  Has not impact on
823
  synthesis, but will cause the LEON test bench to fail.
824
 
825
FPU register tracing
826
CONFIG_DEBUG_FPURF
827
  If you say Y here, all writes to the floating-point unit register file
828
  will be printed on the simulator console.
829
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.