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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-memec-v2mb1000/] [leon3mp.ucf] - Blame information for rev 2

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1 2 dimamali 
# User constrains file for the "Virtex-II V2MB1000 Development kit",
2 
# the "P160 Communications module" and the "P160 Prototype module".
3 
# There are described all of FPGA used pins. Some of nets are
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# duplicated in many groups with different net names. If you need,
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# you can change name of the nets.
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#
7 
# Roman Bartosinski (bartosr@centrum.cz)
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# Revision 1.1, 2003-07-29
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12 
###################################################
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# Main board - Virtex-II V2MB1000 Development kit #
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###################################################
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16 
# DDR Memory 32MB - Address[12:0],Data[15:0],BS[1:0],LDM,UDM,LDQS,UDQS,CSn,RASn,CASn,WEn,CLKE,CLKn,CLK
17 
NET "ddr_ad(0)"     LOC =  B18 | IOSTANDARD = SSTL2_I; # Address 0
18 
NET "ddr_ad(1)"     LOC =  A18 | IOSTANDARD = SSTL2_I; # Address 1
19 
NET "ddr_ad(2)"     LOC =  B17 | IOSTANDARD = SSTL2_I; # Address 2
20 
NET "ddr_ad(3)"     LOC =  A17 | IOSTANDARD = SSTL2_I; # Address 3
21 
NET "ddr_ad(4)"     LOC =  N17 | IOSTANDARD = SSTL2_I; # Address 4
22 
NET "ddr_ad(5)"     LOC =  P18 | IOSTANDARD = SSTL2_I; # Address 5
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NET "ddr_ad(6)"     LOC =  P17 | IOSTANDARD = SSTL2_I; # Address 6
24 
NET "ddr_ad(7)"     LOC =  M18 | IOSTANDARD = SSTL2_I; # Address 7
25 
NET "ddr_ad(8)"     LOC =  M19 | IOSTANDARD = SSTL2_I; # Address 8
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NET "ddr_ad(9)"     LOC =  M20 | IOSTANDARD = SSTL2_I; # Address 9
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NET "ddr_ad(10)"    LOC =  A19 | IOSTANDARD = SSTL2_I; # Address 10
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NET "ddr_ad(11)"    LOC =  N18 | IOSTANDARD = SSTL2_I; # Address 11
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NET "ddr_ad(12)"    LOC =  N20 | IOSTANDARD = SSTL2_I; # Address 12
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NET "ddr_dq(0)"     LOC =  Y21 | IOSTANDARD = SSTL2_II; # Data 0
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NET "ddr_dq(1)"     LOC =  Y22 | IOSTANDARD = SSTL2_II; # Data 1
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NET "ddr_dq(2)"     LOC =  W21 | IOSTANDARD = SSTL2_II; # Data 2
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NET "ddr_dq(3)"     LOC =  V21 | IOSTANDARD = SSTL2_II; # Data 3
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NET "ddr_dq(4)"     LOC =  V22 | IOSTANDARD = SSTL2_II; # Data 4
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NET "ddr_dq(5)"     LOC =  U21 | IOSTANDARD = SSTL2_II; # Data 5
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NET "ddr_dq(6)"     LOC =  U22 | IOSTANDARD = SSTL2_II; # Data 6
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NET "ddr_dq(7)"     LOC =  T21 | IOSTANDARD = SSTL2_II; # Data 7
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NET "ddr_dq(8)"     LOC =  R20 | IOSTANDARD = SSTL2_II; # Data 8
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NET "ddr_dq(9)"     LOC =  R19 | IOSTANDARD = SSTL2_II; # Data 9
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NET "ddr_dq(10)"    LOC =  T20 | IOSTANDARD = SSTL2_II; # Data 10
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NET "ddr_dq(11)"    LOC =  T19 | IOSTANDARD = SSTL2_II; # Data 11
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NET "ddr_dq(12)"    LOC =  U19 | IOSTANDARD = SSTL2_II; # Data 12
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NET "ddr_dq(13)"    LOC =  V20 | IOSTANDARD = SSTL2_II; # Data 13
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NET "ddr_dq(14)"    LOC =  V19 | IOSTANDARD = SSTL2_II; # Data 14
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NET "ddr_dq(15)"    LOC =  W20 | IOSTANDARD = SSTL2_II; # Data 15
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NET "ddr_ba(0)"       LOC =  M21 | IOSTANDARD = SSTL2_I; # Bank Select 0
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NET "ddr_ba(1)"       LOC =  B19 | IOSTANDARD = SSTL2_I; # Bank Select 1
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NET "ddr_dm(0)"         LOC =  R21 | IOSTANDARD = SSTL2_I; # Low Write Mask
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NET "ddr_dm(1)"         LOC =  T22 | IOSTANDARD = SSTL2_I; # High Write Mask
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NET "ddr_dqs(0)"        LOC =  P20 | IOSTANDARD = SSTL2_I; # Low Write/ReadData Strobe
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NET "ddr_dqs(1)"        LOC =  P19 | IOSTANDARD = SSTL2_I; # High Write/Read Data Strobe
52 
NET "ddr_cs0b"          LOC =  N22 | IOSTANDARD = SSTL2_I; # Chip Select
53 
NET "ddr_rasb"         LOC =  N21 | IOSTANDARD = SSTL2_I; # Row Address Strobe
54 
NET "ddr_casb"         LOC =  P21 | IOSTANDARD = SSTL2_I; # Column Adress Strobe
55 
NET "ddr_web"          LOC =  R22 | IOSTANDARD = SSTL2_I; # Write Enable
56 
NET "ddr_clk0"         LOC =  D12 | IOSTANDARD = SSTL2_I; # Clock
57 
NET "ddr_clk0b"        LOC =  E12 | IOSTANDARD = SSTL2_I; # Clock
58 
NET "ddr_cke0"         LOC =  N19 | IOSTANDARD = SSTL2_I; # Clock Enable
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NET "ddr_clk_fb"       LOC =  F13 | IOSTANDARD = SSTL2_I; # Clock feed-back
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61 
# Clock generation - on-board oscillators 100Mhz and 24MHz
62 
NET "clk_100mhz"      LOC =  B11; # On-board 100 MHz Oscillator
63 
NET "clk_24"          LOC =  A11; # On-board 24 MHz Oscillator
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65 
# Reset circuit - RESETn
66 
NET "resetn"          LOC =  B6 ; # FPGA_RESETn (push-button switch SW3)
67 
 
68 
# User 7-segment display (common cathode - active high)
69 
#    - A2 -     - A1 -
70 
#   |      |   |      |
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#   F2    B2   F2    B1
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#   |      |   |      |
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#    - G2 -     - G1 -
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#   |      |   |      |
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#   E2    C2   E1    C1
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#   |      |   |      |
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#    - D2 -     - D1 -
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NET "segm_lo(0)"       LOC =  D9 ; # 7-segment LED display1, Segment A
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NET "segm_lo(1)"       LOC =  C9 ; # 7-segment LED display1, Segment B
80 
NET "segm_lo(2)"       LOC =  F11; # 7-segment LED display1, Segment C
81 
NET "segm_lo(3)"       LOC =  F9 ; # 7-segment LED display1, Segment D
82 
NET "segm_lo(4)"       LOC =  F10; # 7-segment LED display1, Segment E
83 
NET "segm_lo(5)"       LOC =  D10; # 7-segment LED display1, Segment F
84 
NET "segm_lo(6)"       LOC =  C10; # 7-segment LED display1, Segment G
85 
NET "segm_hi(0)"       LOC =  B9 ; # 7-segment LED display2, Segment A
86 
NET "segm_hi(1)"       LOC =  A8 ; # 7-segment LED display2, Segment B
87 
NET "segm_hi(2)"       LOC =  B8 ; # 7-segment LED display2, Segment C
88 
NET "segm_hi(3)"       LOC =  E7 ; # 7-segment LED display2, Segment D
89 
NET "segm_hi(4)"       LOC =  E8 ; # 7-segment LED display2, Segment E
90 
NET "segm_hi(5)"       LOC =  E10; # 7-segment LED display2, Segment F
91 
NET "segm_hi(6)"       LOC =  E9 ; # 7-segment LED display2, Segment G
92 
 
93 
# User LED (active high)
94 
NET "dsuact"             LOC =  A9 ; # User LED
95 
 
96 
# User push button switches (SW5, SW6)
97 
NET "dsubre"           LOC =  D7 ; # User Push Button Switch Input 1 (SW5)
98 
NET "btn_2"           LOC =  A6 ; # User Push Button Switch Input 2 (SW6)
99 
 
100 
# User DIP switch (SW2)
101 
# They are sorted from left to right as DIP(0)..DIP(7)
102 
NET "dip(0)"          LOC =  B4 ; # User Switch Input 1
103 
NET "dip(1)"          LOC =  A4 ; # User Switch Input 2
104 
NET "dip(2)"          LOC =  C4 ; # User Switch Input 3
105 
NET "dip(3)"          LOC =  C5 ; # User Switch Input 4
106 
NET "dip(4)"          LOC =  B5 ; # User Switch Input 5
107 
NET "dip(5)"          LOC =  A5 ; # User Switch Input 6
108 
NET "dip(6)"          LOC =  D6 ; # User Switch Input 7
109 
NET "dip(7)"          LOC =  C6 ; # User Switch Input 8
110 
 
111 
# RS232 Port
112 
NET "dsurx"       LOC =  B7 ; # Received Data, RD to DB9 (pin 2)   - From the PC side ( send data from FPGA )
113 
NET "dsutx"       LOC =  A7 ; # Transmit Data, TD from DB9 (pin 3) -
114 
 
115 
# Virtex-II VBAT
116 
NET "vbat"            LOC =  A21; # VBAT input pin - connected to 3.3V through the JP15
117 
 
118 
# LVDS Port Signals
119 
# - Transmit port
120 
#NET "lvds_out_1n"     LOC =  H2 ; # Negative Data Transmit Bit 1 (J4 - pin 1)
121 
#NET "lvds_out_1p"     LOC =  H1 ; # Positive Data Transmit Bit 1 (J4 - pin 2)
122 
#NET "lvds_out_2n"     LOC =  J2 ; # Negative Data Transmit Bit 2 (J4 - pin 3)
123 
#NET "lvds_out_2p"     LOC =  J1 ; # Positive Data Transmit Bit 2 (J4 - pin 4)
124 
#NET "lvds_out_3n"     LOC =  K2 ; # Negative Data Transmit Bit 3 (J4 - pin 5)
125 
#NET "lvds_out_3p"     LOC =  K1 ; # Positive Data Transmit Bit 3 (J4 - pin 6)
126 
#NET "lvds_out_4n"     LOC =  E4 ; # Negative Data Transmit Bit 4 (J4 - pin 7)
127 
#NET "lvds_out_4p"     LOC =  E3 ; # Positive Data Transmit Bit 4 (J4 - pin 8)
128 
#NET "lvds_out_5n"     LOC =  F4 ; # Negative Data Transmit Bit 5 (J4 - pin 11)
129 
#NET "lvds_out_5p"     LOC =  F3 ; # Positive Data Transmit Bit 5 (J4 - pin 12)
130 
#NET "lvds_out_6n"     LOC =  G4 ; # Negative Data Transmit Bit 6 (J4 - pin 13)
131 
#NET "lvds_out_6p"     LOC =  G3 ; # Positive Data Transmit Bit 6 (J4 - pin 14)
132 
#NET "lvds_out_7n"     LOC =  H4 ; # Negative Data Transmit Bit 7 (J4 - pin 15)
133 
#NET "lvds_out_7p"     LOC =  H3 ; # Positive Data Transmit Bit 7 (J4 - pin 16)
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#NET "lvds_out_8n"     LOC =  J4 ; # Negative Data Transmit Bit 8 (J4 - pin 17)
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#NET "lvds_out_8p"     LOC =  J3 ; # Positive Data Transmit Bit 8 (J4 - pin 18)
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#NET "lvds_out_9n"     LOC =  K4 ; # Negative Data Transmit Bit 9 (J4 - pin 21)
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#NET "lvds_out_9p"     LOC =  K3 ; # Positive Data Transmit Bit 9 (J4 - pin 22)
138 
#NET "lvds_out_10n"    LOC =  L3 ; # Negative Data Transmit Bit 10 (J4 - pin 23)
139 
#NET "lvds_out_10p"    LOC =  L2 ; # Positive Data Transmit Bit 10 (J4 - pin 24)
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#NET "lvds_out_11n"    LOC =  L5 ; # Negative Data Transmit Bit 11 (J4 - pin 25)
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#NET "lvds_out_11p"    LOC =  L4 ; # Positive Data Transmit Bit 11 (J4 - pin 26)
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#NET "lvds_out_12n"    LOC =  E6 ; # Negative Data Transmit Bit 12 (J4 - pin 27)
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#NET "lvds_out_12p"    LOC =  E5 ; # Positive Data Transmit Bit 12 (J4 - pin 28)
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#NET "lvds_out_13n"    LOC =  F5 ; # Negative Data Transmit Bit 13 (J4 - pin 31)
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#NET "lvds_out_13p"    LOC =  G5 ; # Positive Data Transmit Bit 13 (J4 - pin 32)
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#NET "lvds_out_14n"    LOC =  H5 ; # Negative Data Transmit Bit 14 (J4 - pin 33)
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#NET "lvds_out_14p"    LOC =  J6 ; # Positive Data Transmit Bit 14 (J4 - pin 34)
148 
#NET "lvds_out_15n"    LOC =  J5 ; # Negative Data Transmit Bit 15 (J4 - pin 35)
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#NET "lvds_out_15p"    LOC =  K5 ; # Positive Data Transmit Bit 15 (J4 - pin 36)
150 
#NET "lvds_out_16n"    LOC =  K6 ; # Negative Data Transmit Bit 16 (J4 - pin 37)
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#NET "lvds_out_16p"    LOC =  L6 ; # Positive Data Transmit Bit 16 (J4 - pin 38)
152 
## - Receive port
153 
#NET "lvds_in_1p"     LOC =  M2 ; # Positive Data Receive Bit 1 (J6 - pin 3)
154 
#NET "lvds_in_1n"     LOC =  M1 ; # Negative Data Receive Bit 1 (J6 - pin 4)
155 
#NET "lvds_in_2p"     LOC =  N2 ; # Positive Data Receive Bit 2 (J6 - pin 5)
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#NET "lvds_in_2n"     LOC =  N1 ; # Negative Data Receive Bit 2 (J6 - pin 6)
157 
#NET "lvds_in_3p"     LOC =  P2 ; # Positive Data Receive Bit 3 (J6 - pin 7)
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#NET "lvds_in_3n"     LOC =  P1 ; # Negative Data Receive Bit 3 (J6 - pin 8)
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#NET "lvds_in_4p"     LOC =  R2 ; # Positive Data Receive Bit 4 (J6 - pin 9)
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#NET "lvds_in_4n"     LOC =  R1 ; # Negative Data Receive Bit 4 (J6 - pin 10)
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#NET "lvds_in_5p"     LOC =  T2 ; # Positive Data Receive Bit 5 (J6 - pin 13)
162 
#NET "lvds_in_5n"     LOC =  T1 ; # Negative Data Receive Bit 5 (J6 - pin 14)
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#NET "lvds_in_6p"     LOC =  U2 ; # Positive Data Receive Bit 6 (J6 - pin 15)
164 
#NET "lvds_in_6n"     LOC =  U1 ; # Negative Data Receive Bit 6 (J6 - pin 16)
165 
#NET "lvds_in_7p"     LOC =  V2 ; # Positive Data Receive Bit 7 (J6 - pin 17)
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#NET "lvds_in_7n"     LOC =  V1 ; # Negative Data Receive Bit 7 (J6 - pin 18)
167 
#NET "lvds_in_8p"     LOC =  W2 ; # Positive Data Receive Bit 8 (J6 - pin 19)
168 
#NET "lvds_in_8n"     LOC =  W1 ; # Negative Data Receive Bit 8 (J6 - pin 20)
169 
#NET "lvds_in_9p"     LOC =  Y2 ; # Positive Data Receive Bit 9 (J6 - pin 23)
170 
#NET "lvds_in_9n"     LOC =  Y1 ; # Negative Data Receive Bit 9 (J6 - pin 24)
171 
#NET "lvds_in_10p"    LOC =  M6 ; # Positive Data Receive Bit 10 (J6 - pin 25)
172 
#NET "lvds_in_10n"    LOC =  M5 ; # Negative Data Receive Bit 10 (J6 - pin 26)
173 
#NET "lvds_in_11p"    LOC =  M4 ; # Positive Data Receive Bit 11 (J6 - pin 27)
174 
#NET "lvds_in_11n"    LOC =  M3 ; # Negative Data Receive Bit 11 (J6 - pin 28)
175 
#NET "lvds_in_12p"    LOC =  N4 ; # Positive Data Receive Bit 12 (J6 - pin 29)
176 
#NET "lvds_in_12n"    LOC =  N3 ; # Negative Data Receive Bit 12 (J6 - pin 30)
177 
#NET "lvds_in_13p"    LOC =  P4 ; # Positive Data Receive Bit 13 (J6 - pin 33)
178 
#NET "lvds_in_13n"    LOC =  P3 ; # Negative Data Receive Bit 13 (J6 - pin 34)
179 
#NET "lvds_in_14p"    LOC =  R4 ; # Positive Data Receive Bit 14 (J6 - pin 35)
180 
#NET "lvds_in_14n"    LOC =  R3 ; # Negative Data Receive Bit 14 (J6 - pin 36)
181 
#NET "lvds_in_15p"    LOC =  T4 ; # Positive Data Receive Bit 15 (J6 - pin 37)
182 
#NET "lvds_in_15n"    LOC =  T3 ; # Negative Data Receive Bit 15 (J6 - pin 38)
183 
#NET "lvds_in_16p"    LOC =  U4 ; # Positive Data Receive Bit 16 (J6 - pin 39)
184 
#NET "lvds_in_16n"    LOC =  U3 ; # Negative Data Receive Bit 16 (J6 - pin 40)
185 
## - Transmit control port
186 
#NET "lvds_out_clkp"  LOC =  C1 ; # Positive Transmit Clock (J7 - pin 1)
187 
#NET "lvds_out_clkn"  LOC =  C2 ; # Negative Transmit Clock (J7 - pin 2)
188 
#NET "lvds_out_sclkp" LOC =  D1 ; # Positive Transmit Status Clock (J7 - pin 5)
189 
#NET "lvds_out_sclkn" LOC =  D2 ; # Negative Transmit Status Clock (J7 - pin 6)
190 
#NET "lvds_out_st_1p" LOC =  E1 ; # Positive Transmit Status 1 (J7 - pin 9)
191 
#NET "lvds_out_st_1n" LOC =  E2 ; # Negative Transmit Status 1 (J7 - pin 10)
192 
#NET "lvds_out_st_2p" LOC =  F1 ; # Positive Transmit Status 2 (J7 - pin 11)
193 
#NET "lvds_out_st_2n" LOC =  F2 ; # Negative Transmit Status 2 (J7 - pin 12)
194 
#NET "lvds_out_ctrlp" LOC =  G1 ; # Positive Transmit Control (J7 - pin 13)
195 
#NET "lvds_out_ctrln" LOC =  G2 ; # Negative Transmit Control (J7 - pin 14)
196 
## - Receive control port
197 
#NET "lvds_in_ctrln" LOC =  V3 ; # Negative Receive Control (J8 - pin 1)
198 
#NET "lvds_in_ctrlp" LOC =  V4 ; # Positive Receive Control (J8 - pin 2)
199 
#NET "lvds_in_st_2n" LOC =  N5 ; # Negative Receive Status 2 (J8 - pin 3)
200 
#NET "lvds_in_st_2p" LOC =  N6 ; # Positive Receive Status 2 (J8 - pin 4)
201 
#NET "lvds_in_st_1n" LOC =  P5 ; # Negative Receive Status 1 (J8 - pin 5)
202 
#NET "lvds_in_st_1p" LOC =  P6 ; # Positive Receive Status 1 (J8 - pin 6)
203 
#NET "lvds_in_sclkn" LOC =  W11; # Negative Receive Status Clock (J8 - pin 9)
204 
#NET "lvds_in_sclkp" LOC =  V11; # Positive Receive Status Clock (J8 - pin 10)
205 
#NET "lvds_in_clkn"  LOC = AA11; # Negative Receive Clock (J8 - pin 13)
206 
#NET "lvds_in_clkp"  LOC =  Y11; # Positive Receive Clock (J8 - pin 14)
207 
#
208 
## P160 Expansion Module Connectors
209 
## JX1 User I/O Connector
210 
#NET "jx1_a1"  LOC =  C19; # JX1 pin A1 - TCK
211 
#NET "jx1_a3"  LOC =  B20; # JX1 pin A3 - TMS
212 
#NET "jx1_a9"  LOC =  K22; # JX1 pin A9 - LIOA9
213 
#NET "jx1_a11" LOC =  J21; # JX1 pin A11 - LIOA11
214 
#NET "jx1_a13" LOC =  G22; # JX1 pin A13 - LIOA13
215 
#NET "jx1_a15" LOC =  F21; # JX1 pin A15 - LIOA15
216 
#NET "jx1_a17" LOC =  D22; # JX1 pin A17 - LIOA17
217 
#NET "jx1_a19" LOC =  C21; # JX1 pin A19 - LIOA19
218 
#NET "jx1_a21" LOC =  L20; # JX1 pin A21 - LIOA21
219 
#NET "jx1_a23" LOC =  K19; # JX1 pin A23 - LIOA23
220 
#NET "jx1_a25" LOC =  H20; # JX1 pin A25 - LIOA25
221 
#NET "jx1_a27" LOC =  G19; # JX1 pin A27 - LIOA27
222 
#NET "jx1_a29" LOC =  F20; # JX1 pin A29 - LIOA29
223 
NET "jx1_a31" LOC =  F19; # JX1 pin A31 - LIOA31
224 
NET "jx1_a33" LOC =  D11; # JX1 pin A33 - LIOA33
225 
NET "jx1_a35" LOC =  C11; # JX1 pin A35 - LIOA35
226 
NET "jx1_a37" LOC =  C8 ; # JX1 pin A37 - LIOA37
227 
#NET "jx1_a39" LOC =  D8 ; # JX1 pin A39 - LIOA39
228 
#NET "jx1_b1"  LOC =  V18; # JX1 pin B1 - FPGA.BITSTREAM
229 
#NET "jx1_b2"  LOC = AB19; # JX1 pin B2 - SM.DOUT/BUSY
230 
#NET "jx1_b3"  LOC =  Y19; # JX1 pin B3 - FPGA.CCLK
231 
#NET "jx1_b4"  LOC = AB20; # JX1 pin B4 - DONE
232 
#NET "jx1_b5"  LOC = AA19; # JX1 pin B5 - INITn
233 
#NET "jx1_b6"  LOC =  A2 ; # JX1 pin B6 - PROGRAMn
234 
#NET "jx1_b8"  LOC =  L22; # JX1 pin B8 - LIOB8
235 
#NET "jx1_b9"  LOC =  L21; # JX1 pin B9 - LIOB9
236 
#NET "jx1_b10" LOC =  K21; # JX1 pin B10 - LIOB10
237 
#NET "jx1_b11" LOC =  J22; # JX1 pin B11 - LIOB11
238 
#NET "jx1_b12" LOC =  H22; # JX1 pin B12 - LIOB12
239 
#NET "jx1_b13" LOC =  H21; # JX1 pin B13 - LIOB13
240 
#NET "jx1_b14" LOC =  G21; # JX1 pin B14 - LIOB14
241 
#NET "jx1_b15" LOC =  F22; # JX1 pin B15 - LIOB15
242 
#NET "jx1_b16" LOC =  E22; # JX1 pin B16 - LIOB16
243 
#NET "jx1_b17" LOC =  E21; # JX1 pin B17 - LIOB17
244 
#NET "jx1_b18" LOC =  D21; # JX1 pin B18 - LIOB18
245 
#NET "jx1_b19" LOC =  C22; # JX1 pin B19 - LIOB19
246 
#NET "jx1_b20" LOC =  L18; # JX1 pin B20 - LIOB20
247 
#NET "jx1_b21" LOC =  L19; # JX1 pin B21 - LIOB21
248 
#NET "jx1_b22" LOC =  K18; # JX1 pin B22 - LIOB22
249 
#NET "jx1_b23" LOC =  K20; # JX1 pin B23 - LIOB23
250 
#NET "jx1_b24" LOC =  J20; # JX1 pin B24 - LIOB24
251 
#NET "jx1_b25" LOC =  J19; # JX1 pin B25 - LIOB25
252 
#NET "jx1_b26" LOC =  H19; # JX1 pin B26 - LIOB26
253 
#NET "jx1_b27" LOC =  G20; # JX1 pin B27 - LIOB27
254 
#NET "jx1_b28" LOC =  E19; # JX1 pin B28 - LIOB28
255 
#NET "jx1_b29" LOC =  E20; # JX1 pin B29 - LIOB29
256 
#NET "jx1_b30" LOC =  L17; # JX1 pin B30 - LIOB30
257 
#NET "jx1_b31" LOC =  K17; # JX1 pin B31 - LIOB31
258 
#NET "jx1_b32" LOC =  J17; # JX1 pin B32 - LIOB32
259 
#NET "jx1_b33" LOC =  J18; # JX1 pin B33 - LIOB33
260 
#NET "jx1_b34" LOC =  H18; # JX1 pin B34 - LIOB34
261 
#NET "jx1_b35" LOC =  G18; # JX1 pin B35 - LIOB35
262 
#NET "jx1_b36" LOC =  F18; # JX1 pin B36 - LIOB36
263 
#NET "jx1_b37" LOC =  E18; # JX1 pin B37 - LIOB37
264 
#NET "jx1_b38" LOC =  E11; # JX1 pin B38 - LIOB38
265 
#NET "jx1_b39" LOC =  A10; # JX1 pin B39 - LIOB39
266 
#NET "jx1_b40" LOC =  B10; # JX1 pin B40 - LIOB40
267 
## JX2 User I/O Connector
268 
#NET "jx2_a1"  LOC = AB10; # JX2 pin A1 - RIOA1
269 
#NET "jx2_a2"  LOC = AA16; # JX2 pin A2 - RIOA2
270 
#NET "jx2_a3"  LOC = AA17; # JX2 pin A3 - RIOA3
271 
#NET "jx2_a4"  LOC = AB16; # JX2 pin A4 - RIOA4
272 
#NET "jx2_a5"  LOC = AB17; # JX2 pin A5 - RIOA5
273 
#NET "jx2_a6"  LOC = AA15; # JX2 pin A6 - RIOA6
274 
#NET "jx2_a7"  LOC =  W17; # JX2 pin A7 - RIOA7
275 
#NET "jx2_a8"  LOC = AB15; # JX2 pin A8 - RIOA8
276 
#NET "jx2_a9"  LOC =  Y17; # JX2 pin A9 - RIOA9
277 
#NET "jx2_a10" LOC = AA14; # JX2 pin A10 - RIOA10
278 
#NET "jx2_a11" LOC =  W16; # JX2 pin A11 - RIOA11
279 
#NET "jx2_a12" LOC = AB14; # JX2 pin A12 - RIOA12
280 
#NET "jx2_a13" LOC =  Y16; # JX2 pin A13 - RIOA13
281 
#NET "jx2_a14" LOC = AA13; # JX2 pin A14 - RIOA14
282 
#NET "jx2_a15" LOC =  V16; # JX2 pin A15 - RIOA15
283 
#NET "jx2_a16" LOC = AB13; # JX2 pin A16 - RIOA16
284 
#NET "jx2_a17" LOC =  W15; # JX2 pin A17 - RIOA17
285 
#NET "jx2_a18" LOC = AA12; # JX2 pin A18 - RIOA18
286 
#NET "jx2_a19" LOC =  V14; # JX2 pin A19 - RIOA19
287 
#NET "jx2_a20" LOC = AB12; # JX2 pin A20 - RIOA20
288 
#NET "jx2_a21" LOC =  U14; # JX2 pin A21 - RIOA21
289 
#NET "jx2_a22" LOC = AB9 ; # JX2 pin A22 - RIOA22
290 
#NET "jx2_a23" LOC =  U13; # JX2 pin A23 - RIOA23
291 
#NET "jx2_a24" LOC = AA9 ; # JX2 pin A24 - RIOA24
292 
#NET "jx2_a25" LOC =  U12; # JX2 pin A25 - RIOA25
293 
#NET "jx2_a26" LOC = AB8 ; # JX2 pin A26 - RIOA26
294 
#NET "jx2_a27" LOC =  U11; # JX2 pin A27 - RIOA27
295 
#NET "jx2_a28" LOC = AA8 ; # JX2 pin A28 - RIOA28
296 
#NET "jx2_a29" LOC =  U10; # JX2 pin A29 - RIOA29
297 
#NET "jx2_a30" LOC = AB7 ; # JX2 pin A30 - RIOA30
298 
#NET "jx2_a31" LOC =  U9 ; # JX2 pin A31 - RIOA31
299 
#NET "jx2_a32" LOC = AA7 ; # JX2 pin A32 - RIOA32
300 
#NET "jx2_a33" LOC =  V9 ; # JX2 pin A33 - RIOA33
301 
#NET "jx2_a34" LOC = AB6 ; # JX2 pin A34 - RIOA34
302 
#NET "jx2_a35" LOC =  V8 ; # JX2 pin A35 - RIOA35
303 
#NET "jx2_a36" LOC = AA6 ; # JX2 pin A36 - RIOA36
304 
#NET "jx2_a37" LOC =  V7 ; # JX2 pin A37 - RIOA37
305 
#NET "jx2_a38" LOC = AB5 ; # JX2 pin A38 - RIOA38
306 
#NET "jx2_a39" LOC =  V6 ; # JX2 pin A39 - RIOA39
307 
#NET "jx2_a40" LOC = AA5 ; # JX2 pin A40 - RIOA40
308 
#NET "jx2_b2"  LOC =  Y15; # JX2 pin B2 - RIOB2
309 
#NET "jx2_b4"  LOC =  W14; # JX2 pin B4 - RIOB4
310 
#NET "jx2_b6"  LOC =  Y14; # JX2 pin B6 - RIOB6
311 
#NET "jx2_b8"  LOC =  W13; # JX2 pin B8 - RIOB8
312 
#NET "jx2_b10" LOC =  Y13; # JX2 pin B10 - RIOB10
313 
#NET "jx2_b12" LOC =  V13; # JX2 pin B12 - RIOB12
314 
#NET "jx2_b14" LOC =  Y12; # JX2 pin B14 - RIOB14
315 
#NET "jx2_b16" LOC =  W12; # JX2 pin B16 - RIOB16
316 
#NET "jx2_b18" LOC =  V12; # JX2 pin B18 - RIOB18
317 
#NET "jx2_b20" LOC =  V10; # JX2 pin B20 - RIOB20
318 
#NET "jx2_b22" LOC =  Y10; # JX2 pin B22 - RIOB22
319 
#NET "jx2_b24" LOC =  W10; # JX2 pin B24 - RIOB24
320 
#NET "jx2_b26" LOC =  Y9 ; # JX2 pin B26 - RIOB26
321 
#NET "jx2_b28" LOC =  W9 ; # JX2 pin B28 - RIOB28
322 
#NET "jx2_b30" LOC =  Y8 ; # JX2 pin B30 - RIOB30
323 
#NET "jx2_b32" LOC =  W8 ; # JX2 pin B32 - RIOB32
324 
#NET "jx2_b34" LOC =  Y7 ; # JX2 pin B34 - RIOB34
325 
#NET "jx2_b36" LOC =  W7 ; # JX2 pin B36 - RIOB36
326 
#NET "jx2_b38" LOC =  Y6 ; # JX2 pin B38 - RIOB38
327 
#NET "jx2_b40" LOC =  W6 ; # JX2 pin B40 - RIOB40
328 
#
329 
#
330 
#
331 
###############################################################
332 
## P160 Prototype module - Virtex-II V2MB1000 Development kit #
333 
###############################################################
334 
#
335 
## J3 Connector
336 
#   #"j3_1"  - Vin
337 
#   #"j3_2"  - 3.3V
338 
#   #"j3_3"  - 2.5V
339 
#   #"j3_4"  - GND
340 
#NET "j3_5"   LOC = AB10; # J3 pin 5 - RIOA1
341 
#   #"j3_6"  - NC
342 
#NET "j3_7"   LOC = AA16; # J3 pin 7 - RIOA2
343 
#NET "j3_8"   LOC =  L22; # J3 pin 8 - LIOB8
344 
#NET "j3_9"   LOC =  L21; # J3 pin 9 - LIOB9
345 
#NET "j3_10"  LOC =  K21; # J3 pin 10 - LIOB10
346 
#NET "j3_11"  LOC =  J22; # J3 pin 11 - LIOB11
347 
#NET "j3_12"  LOC =  H22; # J3 pin 12 - LIOB12
348 
#NET "j3_13"  LOC =  H21; # J3 pin 13 - LIOB13
349 
#NET "j3_14"  LOC =  G21; # J3 pin 14 - LIOB14
350 
#NET "j3_15"  LOC =  F22; # J3 pin 15 - LIOB15
351 
#NET "j3_16"  LOC =  E22; # J3 pin 16 - LIOB16
352 
#NET "j3_17"  LOC =  E21; # J3 pin 17 - LIOB17
353 
#NET "j3_18"  LOC =  D21; # J3 pin 18 - LIOB18
354 
#NET "j3_19"  LOC =  C22; # J3 pin 19 - LIOB19
355 
#NET "j3_20"  LOC =  L18; # J3 pin 20 - LIOB20
356 
#NET "j3_21"  LOC =  L19; # J3 pin 21 - LIOB21
357 
#NET "j3_22"  LOC =  K18; # J3 pin 22 - LIOB22
358 
#NET "j3_23"  LOC =  K20; # J3 pin 23 - LIOB23
359 
#NET "j3_24"  LOC =  J20; # J3 pin 24 - LIOB24
360 
#NET "j3_25"  LOC =  J19; # J3 pin 25 - LIOB25
361 
#NET "j3_26"  LOC =  H19; # J3 pin 26 - LIOB26
362 
#NET "j3_27"  LOC =  G20; # J3 pin 27 - LIOB27
363 
#NET "j3_28"  LOC =  E19; # J3 pin 28 - LIOB28
364 
#NET "j3_29"  LOC =  E20; # J3 pin 29 - LIOB29
365 
#NET "j3_30"  LOC =  L17; # J3 pin 30 - LIOB30
366 
#NET "j3_31"  LOC =  K17; # J3 pin 31 - LIOB31
367 
#NET "j3_32"  LOC =  J17; # J3 pin 32 - LIOB32
368 
#NET "j3_33"  LOC =  J18; # J3 pin 33 - LIOB33
369 
#NET "j3_34"  LOC =  H18; # J3 pin 34 - LIOB34
370 
#NET "j3_35"  LOC =  G18; # J3 pin 35 - LIOB35
371 
#NET "j3_36"  LOC =  F18; # J3 pin 36 - LIOB36
372 
#NET "j3_37"  LOC =  E18; # J3 pin 37 - LIOB37
373 
#NET "j3_38"  LOC =  E11; # J3 pin 38 - LIOB38
374 
#NET "j3_39"  LOC =  A10; # J3 pin 39 - LIOB39
375 
#NET "j3_40"  LOC =  B10; # J3 pin 40 - LIOB40
376 
#
377 
## J4   Connector
378 
#   #"j4_1"  - Vin
379 
#   #"j4_2"  - 3.3V
380 
#   #"j4_3"  - 2.5V
381 
#NET "j4_4"   LOC =  Y15; # J4 pin 4 - RIOB2
382 
#NET "j4_5"   LOC =  C19; # J4 pin 5 - TCK
383 
#NET "j4_6"   LOC =  K22; # J4 pin 6 - LIOA9
384 
#   #"j4_7"  - TDO
385 
#NET "j4_8"   LOC =  J21; # J4 pin 8 - LIOA11
386 
#   #"j4_9"  - TDI
387 
#NET "j4_10"  LOC =  G22; # J4 pin 10 - LIOA13
388 
#NET "j4_11"  LOC =  B20; # J4 pin 11 - TMS
389 
#NET "j4_12"  LOC =  F21; # J4 pin 12 - LIOA15
390 
#NET "j4_13"  LOC =  V18; # J4 pin 13 - FPGA.BITSTREAM
391 
#NET "j4_14"  LOC =  D22; # J4 pin 14 - LIOA17
392 
#NET "j4_15"  LOC = AB19; # J4 pin 15 - SM.DOUT/BUSY
393 
#NET "j4_16"  LOC =  C21; # J4 pin 16 - LIOA19
394 
#NET "j4_17"  LOC =  Y19; # J4 pin 17 - FPGA.CCLK
395 
#NET "j4_18"  LOC =  L20; # J4 pin 18 - LIOA21
396 
#NET "j4_19"  LOC = AB20; # J4 pin 19 - DONE
397 
#NET "j4_20"  LOC =  K19; # J4 pin 20 - LIOA23
398 
#NET "j4_21"  LOC = AA19; # J4 pin 21 - INITn
399 
#NET "j4_22"  LOC =  H20; # J4 pin 22 - LIOA25
400 
#NET "j4_23"  LOC =  A2 ; # J4 pin 23 - PROGRAMn
401 
#NET "j4_24"  LOC =  G19; # J4 pin 24 - LIOA27
402 
#   #"j4_25"  - GND
403 
#NET "j4_26"  LOC =  F20; # J4 pin 26 - LIOA29
404 
#   #"j4_27"  - GND
405 
#NET "j4_28"  LOC =  F19; # J4 pin 28 - LIOA31
406 
#   #"j4_29"  - GND
407 
#NET "j4_30"  LOC =  D11; # J4 pin 30 - LIOA33
408 
#   #"j4_31"  - GND
409 
#NET "j4_32"  LOC =  C11; # J4 pin 32 - LIOA35
410 
#   #"j4_33"  - GND
411 
#NET "j4_34"  LOC =  C8 ; # J4 pin 34 - LIOA37
412 
#   #"j4_35"  - GND
413 
#NET "j4_36"  LOC =  D8 ; # J4 pin 36 - LIOA39
414 
#   #"j4_37"  - GND
415 
#NET "j4_38"  LOC =  V6 ; # J4 pin 38 - RIOA39
416 
#   #"j4_39"  - GND
417 
#NET "j4_40"  LOC = AA5 ; # J4 pin 40 - RIOA40
418 
#
419 
## J5 Connector
420 
#   #"j5_1"  - Vin
421 
#   #"j5_2"  - 3.3V
422 
#   #"j5_3"  - 2.5V
423 
#NET "j5_4"   LOC =  W14; # J5 pin 4 - RIOB4
424 
#   #"j5_5"  - NC
425 
#NET "j5_6"   LOC =  Y14; # J5 pin 6 - RIOB6
426 
#   #"j5_7"  - JTAG_LOOPBACK
427 
#NET "j5_8"   LOC =  W13; # J5 pin 8 - RIOB8
428 
#   #"j5_9"  - JTAG_LOOPBACK
429 
#NET "j5_10"  LOC =  Y13; # J5 pin 10 - RIOB10
430 
#   #"j5_11"  - NC
431 
#NET "j5_12"  LOC =  V13; # J5 pin 12 - RIOB12
432 
#   #"j5_13"  - NC
433 
#NET "j5_14"  LOC =  Y12; # J5 pin 14 - RIOB14
434 
#   #"j5_15"  - NC
435 
#NET "j5_16"  LOC =  W12; # J5 pin 16 - RIOB16
436 
#   #"j5_17"  - NC
437 
#NET "j5_18"  LOC =  V12; # J5 pin 18 - RIOB18
438 
#   #"j5_19"  - NC
439 
#NET "j5_20"  LOC =  V10; # J5 pin 20 - RIOB20
440 
#   #"j5_21"  - NC
441 
#NET "j5_22"  LOC =  Y10; # J5 pin 22 - RIOB22
442 
#   #"j5_23"  - NC
443 
#NET "j5_24"  LOC =  W10; # J5 pin 24 - RIOB24
444 
#   #"j5_25"  - GND
445 
#NET "j5_26"  LOC =  Y9 ; # J5 pin 26 - RIOB26
446 
#   #"j5_27"  - GND
447 
#NET "j5_28"  LOC =  W9 ; # J5 pin 28 - RIOB28
448 
#   #"j5_29"  - GND
449 
#NET "j5_30"  LOC =  Y8 ; # J5 pin 30 - RIOB30
450 
#   #"j5_31"  - GND
451 
#NET "j5_32"  LOC =  W8 ; # J5 pin 32 - RIOB32
452 
#   #"j5_33"  - GND
453 
#NET "j5_34"  LOC =  Y7 ; # J5 pin 34 - RIOB34
454 
#   #"j5_35"  - GND
455 
#NET "j5_36"  LOC =  W7 ; # J5 pin 36 - RIOB36
456 
#   #"j5_37"  - GND
457 
#NET "j5_38"  LOC =  Y6 ; # J5 pin 38 - RIOB38
458 
#   #"j5_39"  - GND
459 
#NET "j5_40"  LOC =  W6 ; # J5 pin 40 - RIOB40
460 
#
461 
## J6 Connector
462 
#   #"j6_1"  - Vin
463 
#   #"j6_2"  - 3.3V
464 
#   #"j6_3"  - 2.5V
465 
#   #"j6_4"  - GND
466 
#NET "j6_5"   LOC = AB16; # J6 pin 5 - RIOA4
467 
#NET "j6_6"   LOC = AA17; # J6 pin 6 - RIOA3 - User LED
468 
#NET "j6_7"   LOC = AA15; # J6 pin 7 - RIOA6
469 
#NET "j6_8"   LOC = AB17; # J6 pin 8 - RIOA5
470 
#NET "j6_9"   LOC = AB15; # J6 pin 9 - RIOA8
471 
#NET "j6_10"  LOC =  W17; # J6 pin 10 - RIOA7
472 
#NET "j6_11"  LOC = AA14; # J6 pin 11 - RIOA10
473 
#NET "j6_12"  LOC =  Y17; # J6 pin 12 - RIOA9
474 
#NET "j6_13"  LOC = AB14; # J6 pin 13 - RIOA12
475 
#NET "j6_14"  LOC =  W16; # J6 pin 14 - RIOA11
476 
#NET "j6_15"  LOC = AA13; # J6 pin 15 - RIOA14
477 
#NET "j6_16"  LOC =  Y16; # J6 pin 16 - RIOA13
478 
#NET "j6_17"  LOC = AB13; # J6 pin 17 - RIOA16
479 
#NET "j6_18"  LOC =  V16; # J6 pin 18 - RIOA15
480 
#NET "j6_19"  LOC = AA12; # J6 pin 19 - RIOA18
481 
#NET "j6_20"  LOC =  W15; # J6 pin 20 - RIOA17
482 
#NET "j6_21"  LOC = AB12; # J6 pin 21 - RIOA20
483 
#NET "j6_22"  LOC =  V14; # J6 pin 22 - RIOA19
484 
#NET "j6_23"  LOC = AB9 ; # J6 pin 23 - RIOA22
485 
#NET "j6_24"  LOC =  U14; # J6 pin 24 - RIOA21
486 
#NET "j6_25"  LOC = AA9 ; # J6 pin 25 - RIOA24
487 
#NET "j6_26"  LOC =  U13; # J6 pin 26 - RIOA23
488 
#NET "j6_27"  LOC = AB8 ; # J6 pin 27 - RIOA26
489 
#NET "j6_28"  LOC =  U12; # J6 pin 28 - RIOA25
490 
#NET "j6_29"  LOC = AA8 ; # J6 pin 29 - RIOA28
491 
#NET "j6_30"  LOC =  U11; # J6 pin 30 - RIOA27
492 
#NET "j6_31"  LOC = AB7 ; # J6 pin 31 - RIOA30
493 
#NET "j6_32"  LOC =  U10; # J6 pin 32 - RIOA29
494 
#NET "j6_33"  LOC = AA7 ; # J6 pin 33 - RIOA32
495 
#NET "j6_34"  LOC =  U9 ; # J6 pin 34 - RIOA31
496 
#NET "j6_35"  LOC = AB6 ; # J6 pin 35 - RIOA34
497 
#NET "j6_36"  LOC =  V9 ; # J6 pin 36 - RIOA33
498 
#NET "j6_37"  LOC = AA6 ; # J6 pin 37 - RIOA36
499 
#NET "j6_38"  LOC =  V8 ; # J6 pin 38 - RIOA35
500 
#NET "j6_39"  LOC = AB5 ; # J6 pin 39 - RIOA38
501 
#NET "j6_40"  LOC =  V7 ; # J6 pin 40 - RIOA37
502 
 
503 
 
504 
###################################################################
505 
# P160 Communications module - Virtex-II V2MB1000 Development kit #
506 
###################################################################
507 
 
508 
# 10/100 Ethernet
509 
NET "erstn"    LOC =  K17; # JX1 pin B31 - LIOB31 - ETH_PHY_RESETn
510 
NET "emdio"   LOC =  G22; # JX1 pin A13 - LIOA13 - ETH_MDIO
511 
NET "emdc"    LOC =  G21; # JX1 pin B14 - LIOB14 - ETH_MDC
512 
NET "erx_col"    LOC =  J20; # JX1 pin B24 - LIOB24 - ETH_COL
513 
NET "erx_crs"    LOC =  J19; # JX1 pin B25 - LIOB25 - ETH_CRS
514 
NET "etxd(0)"   LOC =  L20; # JX1 pin A21 - LIOA21 - ETH_TXD0
515 
NET "etxd(1)"   LOC =  K18; # JX1 pin B22 - LIOB22 - ETH_TXD1
516 
NET "etxd(2)"   LOC =  K20; # JX1 pin B23 - LIOB23 - ETH_TXD2
517 
NET "etxd(3)"   LOC =  K19; # JX1 pin A23 - LIOA23 - ETH_TDX3
518 
NET "etx_clk"    LOC =  C11; # JX1 pin A35 - LIOA35 - ETH_TXC
519 
NET "etx_er"   LOC =  C21; # JX1 pin A19 - LIOA19 - ETH_TXER
520 
NET "etx_en"   LOC =  L19; # JX1 pin B21 - LIOB21 - ETH_TXEN
521 
NET "erxd(0)"   LOC =  E21; # JX1 pin B17 - LIOB17 - ETH_RXD0
522 
NET "erxd(1)"   LOC =  E22; # JX1 pin B16 - LIOB16 - ETH_RXD1
523 
NET "erxd(2)"   LOC =  F21; # JX1 pin A15 - LIOA15 - ETH_RXD2
524 
NET "erxd(3)"   LOC =  F22; # JX1 pin B15 - LIOB15 - ETH_RXD3
525 
NET "erx_clk"    LOC =  D11; # JX1 pin A33 - LIOA33 - ETH_RXC
526 
NET "erx_er"   LOC =  C22; # JX1 pin B19 - LIOB19 - ETH_RXER
527 
NET "erx_dv"   LOC =  D22; # JX1 pin A17 - LIOA17 - ETH_RXDV
528 
 
529 
# USB Port
530 
NET "usb_vpo"    LOC =  L22; # JX1 pin B8  - LIOB8  - USB_VPO
531 
NET "usb_vmo"    LOC =  L21; # JX1 pin B9  - LIOB9  - USB_VMO
532 
NET "usb_oe"     LOC =  J21; # JX1 pin A11 - LIOA11 - USB_OEn
533 
NET "usb_rcv"    LOC =  J22; # JX1 pin B11 - LIOB11 - USB_RCV
534 
NET "usb_vp"     LOC =  K21; # JX1 pin B10 - LIOB10 - USB_VP
535 
NET "usb_vm"     LOC =  K22; # JX1 pin A9  - LIOA9  - USB_VM
536 
 
537 
# RS232 Port
538 
NET "rxd1" LOC =  H21; # JX1 pin B13 - LIOB13 - RS232_RX (to JP5 pin 2)
539 
NET "txd1" LOC =  H22; # JX1 pin B12 - LIOB12 - RS232_TX (from JP5 pin 3)
540 
 
541 
# I2C Port
542 
NET "i2c_data"   LOC =  J17; # JX1 pin B32 - LIOB32 - I2C_DATA (JP6 pin 1)
543 
NET "i2c_clk"    LOC =  J18; # JX1 pin B33 - LIOB33 - I2C_CLK (JP6 pin 2)
544 
 
545 
# SPI Port
546 
NET "spi_clk"    LOC =  F18; # JX1 pin B36 - LIOB36 - SPI_CLK (JP4 pin 1)
547 
NET "spi_out"    LOC =  H18; # JX1 pin B34 - LIOB34 - SPI_OUT (JP4 pin 2)
548 
NET "spi_in"     LOC =  G18; # JX1 pin B35 - LIOB35 - SPI_IN (JP4 pin 3)
549 
 
550 
# FLASH and SRAM
551 
NET "address(0)"    LOC =  W8 ; # JX2 pin B32 - RIOB32 - A0
552 
NET "address(1)"    LOC = AB6 ; # JX2 pin A34 - RIOA34 - A1
553 
NET "address(2)"    LOC =  V8 ; # JX2 pin A35 - RIOA35 - A2
554 
NET "address(3)"    LOC =  W7 ; # JX2 pin B36 - RIOB36 - A3
555 
NET "address(4)"    LOC =  V9 ; # JX2 pin A33 - RIOA33 - A4
556 
NET "address(5)"    LOC = AA6 ; # JX2 pin A36 - RIOA36 - A5
557 
NET "address(6)"    LOC =  V7 ; # JX2 pin A37 - RIOA37 - A6
558 
NET "address(7)"    LOC = AB5 ; # JX2 pin A38 - RIOA38 - A7
559 
NET "address(8)"    LOC = AB10; # JX2 pin A1  - RIOA1  - A8
560 
NET "address(9)"    LOC = AA17; # JX2 pin A3  - RIOA3  - A9
561 
NET "address(10)"   LOC =  Y14; # JX2 pin B6  - RIOB6  - A10
562 
NET "address(11)"   LOC =  Y15; # JX2 pin B2  - RIOB2  - A11
563 
NET "address(12)"   LOC = AB16; # JX2 pin A4  - RIOA4  - A12
564 
NET "address(13)"   LOC = AB17; # JX2 pin A5  - RIOA5  - A13
565 
NET "address(14)"   LOC = AB15; # JX2 pin A8  - RIOA8  - A14
566 
NET "address(15)"   LOC =  W14; # JX2 pin B4  - RIOB4  - A15
567 
NET "address(16)"   LOC =  W13; # JX2 pin B8  - RIOB8  - A16
568 
NET "address(17)"   LOC =  Y7 ; # JX2 pin B34 - RIOB34 - A17
569 
NET "address(18)"   LOC =  Y6 ; # JX2 pin B38 - RIOB38 - A18
570 
NET "address(19)"   LOC = AA16; # JX2 pin A2  - RIOA2  - A19
571 
NET "address(20)"   LOC =  W6 ; # JX2 pin B40 - RIOB40 - A20
572 
NET "address(21)"   LOC = AA15; # JX2 pin A6  - RIOA6  - A21
573 
NET "address(22)"   LOC =  W17; # JX2 pin A7  - RIOA7  - A22
574 
NET "data(0)"    LOC = AA12; # JX2 pin A18 - RIOA18 - D0
575 
NET "data(1)"    LOC =  U14; # JX2 pin A21 - RIOA21 - D1
576 
NET "data(2)"    LOC =  W15; # JX2 pin A17 - RIOA17 - D2
577 
NET "data(3)"    LOC =  Y12; # JX2 pin B14 - RIOB14 - D3
578 
NET "data(4)"    LOC =  Y16; # JX2 pin A13 - RIOA13 - D4
579 
NET "data(5)"    LOC = AA13; # JX2 pin A14 - RIOA14 - D5
580 
NET "data(6)"    LOC =  Y17; # JX2 pin A9  - RIOA9  - D6
581 
NET "data(7)"    LOC =  W16; # JX2 pin A11 - RIOA11 - D7
582 
NET "data(8)"    LOC =  V12; # JX2 pin B18 - RIOB18 - D8
583 
NET "data(9)"    LOC = AB13; # JX2 pin A16 - RIOA16 - D9
584 
NET "data(10)"   LOC =  W12; # JX2 pin B16 - RIOB16 - D10
585 
NET "data(11)"   LOC =  V16; # JX2 pin A15 - RIOA15 - D11
586 
NET "data(12)"   LOC = AB14; # JX2 pin A12 - RIOA12 - D12
587 
NET "data(13)"   LOC =  Y13; # JX2 pin B10 - RIOB10 - D13
588 
NET "data(14)"   LOC =  V13; # JX2 pin B12 - RIOB12 - D14
589 
NET "data(15)"   LOC = AA14; # JX2 pin A10 - RIOA10 - D15
590 
NET "data(16)"   LOC =  Y8 ; # JX2 pin B30 - RIOB30 - D16
591 
NET "data(17)"   LOC = AA7 ; # JX2 pin A32 - RIOA32 - D17
592 
NET "data(18)"   LOC =  W9 ; # JX2 pin B28 - RIOB28 - D18
593 
NET "data(19)"   LOC =  U11; # JX2 pin A27 - RIOA27 - D19
594 
NET "data(20)"   LOC =  Y9 ; # JX2 pin B26 - RIOB26 - D20
595 
NET "data(21)"   LOC = AB8 ; # JX2 pin A26 - RIOA26 - D21
596 
NET "data(22)"   LOC = AB9 ; # JX2 pin A22 - RIOA22 - D22
597 
NET "data(23)"   LOC =  U13; # JX2 pin A23 - RIOA23 - D23
598 
NET "data(24)"   LOC = AB7 ; # JX2 pin A30 - RIOA30 - D24
599 
NET "data(25)"   LOC =  U9 ; # JX2 pin A31 - RIOA31 - D25
600 
NET "data(26)"   LOC =  U10; # JX2 pin A29 - RIOA29 - D26
601 
NET "data(27)"   LOC = AA8 ; # JX2 pin A28 - RIOA28 - D27
602 
NET "data(28)"   LOC =  U12; # JX2 pin A25 - RIOA25 - D28
603 
NET "data(29)"   LOC = AA9 ; # JX2 pin A24 - RIOA24 - D29
604 
NET "data(30)"   LOC =  W10; # JX2 pin B24 - RIOB24 - D30
605 
NET "data(31)"   LOC =  Y10; # JX2 pin B22 - RIOB22 - D31
606 
NET "ramsn"   LOC = AB12; # JX2 pin A20 - RIOA20 - MEM.CE1Sn
607 
NET "romsn"    LOC =  V10; # JX2 pin B20 - RIOB20 - MEM.CEFn
608 
NET "oen"     LOC =  V14; # JX2 pin A19 - RIOA19 - MEM.OEn
609 
NET "writen"     LOC = AA5 ; # JX2 pin A40 - RIOA40 - MEM.WEn
610 
NET "mem_rdy"    LOC =  V6 ; # JX2 pin A39 - RIOA39 - MEM.RY/BY ???
611 
NET "romrstn"    LOC =  E18; # JX1 pin B37 - LIOB37 - MEM_RESETn
612 
NET "mben(0)"    LOC =  H19; # JX1 pin B26 - LIOB26 - MEM.BLBn
613 
NET "mben(1)"    LOC =  G20; # JX1 pin B27 - LIOB27 - MEM.BUBn
614 
NET "mben(2)"    LOC =  H20; # JX1 pin A25 - LIOA25 - MEM.ALBn
615 
NET "mben(3)"    LOC =  G19; # JX1 pin A27 - LIOA27 - MEM.AUBn
616 
 
617 
# PS/2 Keybord Interface
618 
NET "ps2_data"   LOC =  F20; # JX1 pin A29 - LIOA29 - PLD_KB_DATA (JP3 pin 1)
619 
NET "ps2_clk"    LOC =  F19; # JX1 pin A31 - LIOA31 - PLD_KB_CLK        (JP3 pin 5)
620 
 
621 
# LCD Interface
622 
NET "data(0)"    LOC = AA12; # JX2 pin A18 - RIOA18 - D0 (JP12 pin 8)
623 
NET "data(1)"    LOC =  U14; # JX2 pin A21 - RIOA21 - D1 (JP12 pin 7)
624 
NET "data(2)"    LOC =  W15; # JX2 pin A17 - RIOA17 - D2 (JP12 pin 6)
625 
NET "data(3)"    LOC =  Y12; # JX2 pin B14 - RIOB14 - D3 (JP12 pin 5)
626 
NET "data(4)"    LOC =  Y16; # JX2 pin A13 - RIOA13 - D4 (JP12 pin 4)
627 
NET "data(5)"    LOC = AA13; # JX2 pin A14 - RIOA14 - D5 (JP12 pin 3)
628 
NET "data(6)"    LOC =  Y17; # JX2 pin A9  - RIOA9  - D6 (JP12 pin 2)
629 
NET "data(7)"    LOC =  W16; # JX2 pin A11 - RIOA11 - D7 (JP12 pin 1)
630 
NET "lcd_en"     LOC =  E19; # JX1 pin B28 - LIOB28 - PLD_LCD_EN        (JP12 pin 9)
631 
NET "lcd_rs"     LOC =  E20; # JX1 pin B29 - LIOB29 - PLD_LCD_RS        (JP12 pin 11)
632 
NET "lcd_rw"     LOC =  L17; # JX1 pin B30 - LIOB30 - PLD_LCD_R/Wn (JP12 pin 10)
633 
 
634 
# ??? CoolRunner CPLD ???
635 
NET "pld_clk0"    LOC =  A10; # JX1 pin B39 - LIOB39 - PLD_CLK2
636 
NET "pld_clk2"    LOC =  B10; # JX1 pin B40 - LIOB40 - PLD_CLK0
637 
 
638 
 
639 
NET erx_clk PERIOD = 40.000 ;
640 
OFFSET = IN : 10.000 : BEFORE erx_clk ;
641 
NET etx_clk PERIOD = 40.000 ;
642 
OFFSET = OUT : 20.000 : AFTER etx_clk ;
643 
OFFSET = IN : 8.000 : BEFORE etx_clk ;
644 
 
645 
 
646 
NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc2v.ddr_phy0/rclk90b" TNM_NET = "rclk90b";
647 
TIMEGRP "rclk270b_rise" = FALLING "rclk90b";
648 
NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
649 
TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 8.00 ns HIGH 50 %;
650 
 
651 
NET "clkm"               TNM_NET = "clkm";
652 
NET "clkml"              TNM_NET = "clkml";
653 
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
654 
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
655 
NET "lock"  TIG;
656 
 
657 
 
658 
#NET "ddrsp0.ddrc/ddr_phy0/ddr_phy0/xc2v.ddr_phy0/rclk270b" TNM_NET = "rclk270b";
659 
#TIMEGRP "rclk270b_rise" = RISING "rclk270b";
660 
TIMEGRP "clkml_rise" = RISING "clkml";
661 
TIMESPEC "TS_rclk270b_clkml_rise" = FROM "rclk270b_rise" TO "clkml_rise" 3.500;
662 
 

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