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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-memec-v2mb1000/] [leon3mp.xcf] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali
 
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NET clk_100mhz PERIOD = 10.000 ;
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NET erx_clk PERIOD = 40.000 ;
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OFFSET = IN : 10.000 : BEFORE erx_clk ;
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NET etx_clk PERIOD = 40.000 ;
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OFFSET = OUT : 20.000 : AFTER etx_clk ;
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OFFSET = IN : 8.000 : BEFORE etx_clk ;
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#NET ddr_clk0 FEEDBACK = 1.0 NET ddr_clk_fb;
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#TIMESPEC "TS_sepclk1" = FROM "clkgen0_clkin" TO "ddrsp0_ddr_phy0_clk" TIG;
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#TIMESPEC "TS_sepclk2" = FROM "ddrsp0_ddr_phy0_clk" TO "clkgen0_clkin" TIG;
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NET "clkm"               TNM_NET = "clkm";
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NET "clkml"              TNM_NET = "clkml";
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TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
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TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
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NET "lock"  TIG;
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NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
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TIMESPEC "TS_ddr_clk_fb" = PERIOD "ddr_clk_fb" 8.000 ns HIGH 50.00%;

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