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dimamali |
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This leon3 design is tailored to the Xilinx Virtex4 ML401/2 boards
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---------------------------------------------------------------------
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Design specifics:
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* Select the board type in xconfig 'Board' menu. The default is ML401.
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* System reset is mapped to the CPU RESET button
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* The serial port is connected to the console UART (UART 1) when
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dip switch 1 on the GPIO DIP switch is off. Otherwise it is
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connected to the DSU UART. The DSU BREAK input is mapped
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on the 'south' push-button.
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* The JTAG DSU interface is enabled and works well with
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GRMON and Xilinx parallel cables. Grmon-1.0.24 and later
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also work with the Xilinx Platform USB cable.
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* The 100 Mbit version of GRETH is enabled. Ethernet debug link
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is also enabled, but will only work on a 100 Mbit connection.
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The 1000 Mbit version of GRETH is not enabled but works well on
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the board. Note that this core is not available in the GPL version
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of GRLIB. If the 1000 Mbit version is enabled, the IOBDELAY
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constraints for phy_rx_data(7 downto 4) should be uncommented
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in leon3mp.ucf. These constraints must not be present for designs
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without the 1000 Mbit GRETH due to a bug in Xilinx's map tool.
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* DDR is mapped at address 0x40000000, using the DDRSPA core.
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The DDR runs OK up to 120 MHz, higher frequencies can give
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data errors and is not recommended.
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* The LEON3 processor can run up to 70 - 80 MHz on the board
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in the typical configuration.
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* The SSRAM can be interfaced with either the SSRAM controller
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or the LEON2 Memory controller. Start GRMON with -ramws 1
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when the LEON2 controller is used.
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* The I2C-master is enabled and is connected to the boards I2C
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bus which contains an EEPROM (24LC04B-I/ST) with I2C address
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0b1010--B (where B selects one of two 256-word blocks and '-'
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is don't care).
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* The FLASH memory can be programmed using GRMON, regardless
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of which memory controller that is used.
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* If the VGA core is enabled its constraints should be
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uncommented in leon3mp.ucf.
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* Sample output from GRMON is:
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GRMON LEON debug monitor v1.1.19c
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Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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using JTAG cable on parallel port
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JTAG chain: xc95144xl xc4vlx25 xcf32p xccace
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GRLIB build version: 2314
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initialising .............
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detected frequency: 65 MHz
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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GR Ethernet MAC Gaisler Research
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DDR266 Controller Gaisler Research
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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LEON2 Memory Controller European Space Agency
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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General purpose I/O port Gaisler Research
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AMBA Wrapper for OC I2C-master Gaisler Research
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AHB status register Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> inf sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
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ahb master 1
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02.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
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ahb master 2, irq 12
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apb: 80000b00 - 80000c00
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edcl ip 192.168.0.69, buffer 2 kbyte
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00.01:025 Gaisler Research DDR266 Controller (ver 0x0)
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ahb: 40000000 - 50000000
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ahb: fff00100 - fff00200
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32-bit DDR : 1 * 64 Mbyte @ 0x40000000
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120 MHz, col 9, ref 7.8 us
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 128 lines, stack pointer 0x43fffff0
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CPU#0 win 8, hwbp 2, itrace 128, srmmu, lddel 1
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icache 4 * 4 kbyte, 32 byte/line lru
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dcache 4 * 4 kbyte, 16 byte/line lru
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03.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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ahb: 20000000 - 40000000
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ahb: c0000000 - c1000000
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apb: 80000000 - 80000100
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32-bit prom @ 0x00000000
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38400
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 65
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08.01:01a Gaisler Research General purpose I/O port (ver 0x0)
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apb: 80000800 - 80000900
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0c.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x0)
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irq 11
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apb: 80000c00 - 80000d00
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0f.01:052 Gaisler Research AHB status register (ver 0x0)
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irq 7
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apb: 80000f00 - 80001000
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grlib> fla
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Intel-style 32-bit (2x16-bit) flash
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Manuf. Intel Intel
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Type MT28F320J3 MT28F320J3
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Device ID 81210928c438f018 d13909b886afd4e6
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User ID a003ffffbb35ce9b ffffffffffffffff
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2 x 4 Mbyte = 8 Mbyte total @ 0x00000000
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CFI information
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flash family : 1
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flash size : 32 Mbit
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erase regions : 1
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erase blocks : 32
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write buffer : 32 bytes
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region 0 : 32 blocks of 128 Kbytes
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grlib> i2c read 0x50 0x00 8
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00: 48 57 2d 56
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04: 34 2d 4d 4c
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grlib> i2c read 0x51 0x00 8
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00: 00 00 00 00
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04: 00 00 00 00
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grlib>
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