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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-xilinx-ml40x/] [leon3mp.vhd] - Blame information for rev 2

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1 2 dimamali
-----------------------------------------------------------------------------
2
--  LEON3 Demonstration design
3
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4
--
5
--  This program is free software; you can redistribute it and/or modify
6
--  it under the terms of the GNU General Public License as published by
7
--  the Free Software Foundation; either version 2 of the License, or
8
--  (at your option) any later version.
9
--
10
--  This program is distributed in the hope that it will be useful,
11
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
--  GNU General Public License for more details.
14
--
15
--  You should have received a copy of the GNU General Public License
16
--  along with this program; if not, write to the Free Software
17
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18
------------------------------------------------------------------------------
19
 
20
 
21
library ieee;
22
use ieee.std_logic_1164.all;
23
library grlib, techmap;
24
use grlib.amba.all;
25
use grlib.devices.all;
26
use grlib.stdlib.all;
27
use techmap.gencomp.all;
28
use techmap.allclkgen.all;
29
library gaisler;
30
use gaisler.memctrl.all;
31
use gaisler.leon3.all;
32
use gaisler.uart.all;
33
use gaisler.misc.all;
34
use gaisler.net.all;
35
use gaisler.jtag.all;
36
use gaisler.spacewire.all;
37
 
38
library esa;
39
use esa.memoryctrl.all;
40
use work.config.all;
41
 
42
entity leon3mp is
43
  generic (
44
    fabtech   : integer := CFG_FABTECH;
45
    memtech   : integer := CFG_MEMTECH;
46
    padtech   : integer := CFG_PADTECH;
47
    ncpu      : integer := CFG_NCPU;
48
    disas     : integer := CFG_DISAS;   -- Enable disassembly to console
49
    dbguart   : integer := CFG_DUART;   -- Print UART on console
50
    pclow     : integer := CFG_PCLOW
51
  );
52
  port (
53
    sys_rst_in  : in  std_ulogic;
54
    sys_clk     : in  std_ulogic;       -- 100 MHz main clock
55
    plb_error   : out std_logic;        -- IU error mode
56
    opb_error   : out std_logic;        -- DSU active
57
    flash_a23   : out std_ulogic;
58
    sram_flash_addr : out std_logic_vector(22 downto 0);
59
    sram_flash_data : inout std_logic_vector(31 downto 0);
60
    sram_cen    : out std_logic;
61
    sram_bw     : out std_logic_vector (0 to 3);
62
    sram_flash_oe_n : out std_ulogic;
63
    sram_flash_we_n     : out std_ulogic;
64
    flash_ce    : out std_logic;
65
    sram_clk    : out std_ulogic;
66
    sram_clk_fb : in  std_ulogic;
67
    sram_mode   : out std_ulogic;
68
    sram_adv_ld_n : out std_ulogic;
69
--pragma translate_off
70
    iosn    : out std_ulogic;
71
--pragma translate_on
72
 
73
    ddr_clk     : out std_logic;
74
    ddr_clkb    : out std_logic;
75
    ddr_clk_fb  : in std_logic;
76
    ddr_cke     : out std_logic;
77
    ddr_csb     : out std_logic;
78
    ddr_web     : out std_ulogic;                       -- ddr write enable
79
    ddr_rasb    : out std_ulogic;                       -- ddr ras
80
    ddr_casb    : out std_ulogic;                       -- ddr cas
81
    ddr_dm      : out std_logic_vector (3 downto 0);    -- ddr dm
82
    ddr_dqs     : inout std_logic_vector (3 downto 0);    -- ddr dqs
83
    ddr_ad      : out std_logic_vector (12 downto 0);   -- ddr address
84
    ddr_ba      : out std_logic_vector (1 downto 0);    -- ddr bank address
85
    ddr_dq      : inout std_logic_vector (31 downto 0); -- ddr data
86
 
87
    txd1        : out std_ulogic;                       -- UART1 tx data
88
    rxd1        : in  std_ulogic;                       -- UART1 rx data
89
 
90
    gpio        : inout std_logic_vector(26 downto 0);   -- I/O port
91
 
92
    phy_gtx_clk : out std_logic;
93
    phy_mii_data: inout std_logic;              -- ethernet PHY interface
94
    phy_tx_clk  : in std_ulogic;
95
    phy_rx_clk  : in std_ulogic;
96
    phy_rx_data : in std_logic_vector(7 downto 0);
97
    phy_dv      : in std_ulogic;
98
    phy_rx_er   : in std_ulogic;
99
    phy_col     : in std_ulogic;
100
    phy_crs     : in std_ulogic;
101
    phy_tx_data : out std_logic_vector(7 downto 0);
102
    phy_tx_en   : out std_ulogic;
103
    phy_tx_er   : out std_ulogic;
104
    phy_mii_clk : out std_ulogic;
105
    phy_rst_n   : out std_ulogic;
106
 
107
    ps2_keyb_clk   : inout std_logic;
108
    ps2_keyb_data  : inout std_logic;
109
    ps2_mouse_clk  : inout std_logic;
110
    ps2_mouse_data : inout std_logic;
111
 
112
    tft_lcd_clk : out std_ulogic;
113
    vid_blankn  : out std_ulogic;
114
    vid_syncn   : out std_ulogic;
115
    vid_hsync   : out std_ulogic;
116
    vid_vsync   : out std_ulogic;
117
    vid_r       : out std_logic_vector(7 downto 0);
118
    vid_g       : out std_logic_vector(7 downto 0);
119
    vid_b       : out std_logic_vector(7 downto 0);
120
 
121
    usb_csn : out std_logic;
122
 
123
    iic_scl : inout std_ulogic;
124
    iic_sda : inout std_ulogic
125
   );
126
end;
127
 
128
architecture rtl of leon3mp is
129
 
130
constant blength : integer := 12;
131
constant fifodepth : integer := 8;
132
constant maxahbm : integer := NCPU+CFG_AHB_UART
133
        +CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
134
 
135
signal vcc, gnd   : std_logic_vector(4 downto 0);
136
signal memi  : memory_in_type;
137
signal memo  : memory_out_type;
138
signal wpo   : wprot_out_type;
139
signal sdi   : sdctrl_in_type;
140
signal sdo   : sdctrl_out_type;
141
signal sdo2, sdo3 : sdctrl_out_type;
142
 
143
signal apbi  : apb_slv_in_type;
144
signal apbo  : apb_slv_out_vector := (others => apb_none);
145
signal ahbsi : ahb_slv_in_type;
146
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
147
signal ahbmi : ahb_mst_in_type;
148
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
149
 
150
signal clkm, rstn, rstraw, srclkl : std_ulogic;
151
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
152
 
153
signal cgi, cgi2   : clkgen_in_type;
154
signal cgo, cgo2   : clkgen_out_type;
155
signal u1i, u2i, dui : uart_in_type;
156
signal u1o, u2o, duo : uart_out_type;
157
 
158
signal irqi : irq_in_vector(0 to NCPU-1);
159
signal irqo : irq_out_vector(0 to NCPU-1);
160
 
161
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
162
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
163
 
164
signal dsui : dsu_in_type;
165
signal dsuo : dsu_out_type;
166
 
167
signal ethi, ethi1, ethi2 : eth_in_type;
168
signal etho, etho1, etho2 : eth_out_type;
169
 
170
signal gpti : gptimer_in_type;
171
 
172
signal gpioi : gpio_in_type;
173
signal gpioo : gpio_out_type;
174
 
175
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
176
signal tck, tckn, tms, tdi, tdo : std_ulogic;
177
signal ddrclk, ddrrst : std_ulogic;
178
 
179
 
180
signal ethclk, egtx_clk_fb : std_ulogic;
181
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
182
 
183
signal kbdi  : ps2_in_type;
184
signal kbdo  : ps2_out_type;
185
signal moui  : ps2_in_type;
186
signal mouo  : ps2_out_type;
187
signal vgao  : apbvga_out_type;
188
signal clk_sel : std_logic_vector(1 downto 0);
189
signal clkval : std_logic_vector(1 downto 0);
190
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
191
 
192
signal i2ci : i2c_in_type;
193
signal i2co : i2c_out_type;
194
 
195
constant BOARD_FREQ : integer := 100000;   -- input frequency in KHz
196
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;  -- cpu frequency in KHz
197
constant IOAEN : integer := CFG_DDRSP;
198
 
199
signal stati : ahbstat_in_type;
200
 
201
signal ddsi  : ddrmem_in_type;
202
signal ddso  : ddrmem_out_type;
203
 
204
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
205
signal ddr_clkv         : std_logic_vector(2 downto 0);
206
signal ddr_clkbv        : std_logic_vector(2 downto 0);
207
signal ddr_ckev         : std_logic_vector(1 downto 0);
208
signal ddr_csbv         : std_logic_vector(1 downto 0);
209
signal ddr_adl          : std_logic_vector (13 downto 0);
210
 
211
attribute syn_keep : boolean;
212
attribute syn_preserve : boolean;
213
attribute syn_keep of clkml : signal is true;
214
attribute syn_preserve of clkml : signal is true;
215
attribute syn_keep of egtx_clk : signal is true;
216
attribute syn_preserve of egtx_clk : signal is true;
217
attribute keep : boolean;
218
attribute keep of lock : signal is true;
219
attribute keep of clkml : signal is true;
220
attribute keep of clkm : signal is true;
221
attribute keep of egtx_clk : signal is true;
222
 
223
signal romsn   : std_ulogic;
224
constant SPW_LOOP_BACK : integer := 0;
225
 
226
begin
227
 
228
  usb_csn <= '1';
229
----------------------------------------------------------------------
230
---  Reset and Clock generation  -------------------------------------
231
----------------------------------------------------------------------
232
 
233
  vcc <= (others => '1'); gnd <= (others => '0');
234
  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
235
 
236
  ssrref_pad : clkpad generic map (tech => padtech)
237
        port map (sram_clk_fb, ssrclkfb);
238
  clk_pad : clkpad generic map (tech => padtech, arch => 2)
239
        port map (sys_clk, lclk);
240
 
241
  srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
242
        port map (sram_clk, srclkl);
243
 
244
  clkgen0 : clkgen              -- system clock generator
245
    generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
246
    port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
247
 
248
 
249
  clkgen1 : clkgen              -- Ethernet 1G PHY clock generator
250
    generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
251
    port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
252
  cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
253
  egtx_clk_pad : outpad generic map (tech => padtech)
254
    port map (phy_gtx_clk, egtx_clk);
255
 
256
  resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
257
  rst0 : rstgen                 -- reset generator
258
  port map (rst, clkm, clklock, rstn, rstraw);
259
  clklock <= lock and cgo2.clklock;
260
 
261
----------------------------------------------------------------------
262
---  AHB CONTROLLER --------------------------------------------------
263
----------------------------------------------------------------------
264
 
265
  ahb0 : ahbctrl                -- AHB arbiter/multiplexer
266
  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
267
        rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
268
        ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
269
  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
270
 
271
----------------------------------------------------------------------
272
---  LEON3 processor and DSU -----------------------------------------
273
----------------------------------------------------------------------
274
 
275
  l3 : if CFG_LEON3 = 1 generate
276
    cpu : for i in 0 to NCPU-1 generate
277
      u0 : leon3s                       -- LEON3 processor      
278
      generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279
        0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280
        CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281
        CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282
        CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283
        CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
284
      port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285
                irqi(i), irqo(i), dbgi(i), dbgo(i));
286
    end generate;
287
    errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
288
 
289
    dsugen : if CFG_DSU = 1 generate
290
      dsu0 : dsu3                       -- LEON3 Debug Support Unit
291
      generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
292
         ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
293
      port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
294
--    dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); 
295
      dsui.enable <= '1';
296
--    dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); 
297
       dsui.break <= gpioo.val(11); --  South Button
298
--    dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
299
      dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
300
      ndsuact <= not dsuo.active;
301
    end generate;
302
  end generate;
303
 
304
  nodsu : if CFG_DSU = 0 generate
305
    dsuo.tstop <= '0'; dsuo.active <= '0';
306
  end generate;
307
 
308
  dcomgen : if CFG_AHB_UART = 1 generate
309
    dcom0: ahbuart              -- Debug UART
310
    generic map (hindex => NCPU, pindex => 7, paddr => 7)
311
    port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
312
--    dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd); 
313
--    dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
314
    dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
315
  end generate;
316
 
317
  txd1 <= duo.txd when  gpioo.val(21) = '1' else u1o.txd;
318
 
319
  ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
320
    ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
321
      port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
322
               open, open, open, open, open, open, open, gnd(0));
323
  end generate;
324
 
325
----------------------------------------------------------------------
326
---  Memory controllers ----------------------------------------------
327
----------------------------------------------------------------------
328
 
329
  memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
330
  memi.brdyn <= '1'; memi.bexcn <= '1';
331
 
332
  ssr0 : if CFG_SSCTRL = 1 generate
333
    ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
334
    port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
335
  end generate;
336
 
337
  mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
338
    mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
339
        ramaddr => 16#C00#, rammask => 16#FF0#,
340
        paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
341
        ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
342
        invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
343
    port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
344
  end generate;
345
 
346
  romsn <= not memo.romsn(0);
347
 
348
  sram_adv_ld_n_pad : outpad generic map (tech => padtech)
349
        port map (sram_adv_ld_n, gnd(0));
350
  sram_mode_pad : outpad generic map (tech => padtech)
351
        port map (sram_mode, gnd(0));
352
  addr_pad : outpadv generic map (width => 23, tech => padtech)
353
        port map (sram_flash_addr, memo.address(24 downto 2));
354
  addr23_pad : outpad generic map (tech => padtech)
355
        port map (flash_a23, gnd(0));
356
  rams_pad : outpad generic map ( tech => padtech)
357
        port map (sram_cen, memo.ramsn(0));
358
  roms_pad : outpad generic map (tech => padtech)
359
        port map (flash_ce, romsn);
360
  oen_pad  : outpad generic map (tech => padtech)
361
        port map (sram_flash_oe_n, memo.oen);
362
--pragma translate_off
363
  iosn_pad  : outpad generic map (tech => padtech)
364
        port map (iosn, memo.iosn);
365
--pragma translate_on
366
  rwen_pad : outpadv generic map (width => 4, tech => padtech)
367
        port map (sram_bw, memo.wrn);
368
  wri_pad  : outpad generic map (tech => padtech)
369
        port map (sram_flash_we_n, memo.writen);
370
  data_pads : iopadvv generic map (tech => padtech, width => 32)
371
      port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
372
 
373
  ddrsp0 : if (CFG_DDRSP /= 0) generate
374
 
375
    ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
376
        hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
377
        pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
378
        clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
379
        col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32)
380
     port map (
381
        rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
382
        ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
383
        ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
384
        ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
385
        ddr_ad <= ddr_adl(12 downto 0);
386
        ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
387
        ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
388
  end generate;
389
 
390
  noddr :  if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
391
 
392
----------------------------------------------------------------------
393
---  APB Bridge and various periherals -------------------------------
394
----------------------------------------------------------------------
395
 
396
  bpromgen : if CFG_AHBROMEN /= 0 generate
397
    brom : entity work.ahbrom
398
      generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
399
      port map ( rstn, clkm, ahbsi, ahbso(6));
400
  end generate;
401
 
402
----------------------------------------------------------------------
403
---  APB Bridge and various periherals -------------------------------
404
----------------------------------------------------------------------
405
 
406
  apb0 : apbctrl                                -- AHB/APB bridge
407
  generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
408
  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
409
 
410
  ua1 : if CFG_UART1_ENABLE /= 0 generate
411
    uart1 : apbuart                     -- UART 1
412
    generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
413
        fifosize => CFG_UART1_FIFO)
414
    port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
415
    u1i.extclk <= '0'; u1i.ctsn <= '0';
416
    u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
417
  end generate;
418
 
419
  irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
420
    irqctrl0 : irqmp                    -- interrupt controller
421
    generic map (pindex => 2, paddr => 2, ncpu => NCPU)
422
    port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
423
  end generate;
424
  irq3 : if CFG_IRQ3_ENABLE = 0 generate
425
    x : for i in 0 to NCPU-1 generate
426
      irqi(i).irl <= "0000";
427
    end generate;
428
    apbo(2) <= apb_none;
429
  end generate;
430
 
431
  gpt : if CFG_GPT_ENABLE /= 0 generate
432
    timer0 : gptimer                    -- timer unit
433
    generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
434
        sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
435
        nbits => CFG_GPT_TW)
436
    port map (rstn, clkm, apbi, apbo(3), gpti, open);
437
    gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
438
  end generate;
439
 
440
  nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
441
 
442
  kbd : if CFG_KBD_ENABLE /= 0 generate
443
    ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
444
      port map(rstn, clkm, apbi, apbo(4), moui, mouo);
445
    ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
446
      port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
447
  end generate;
448
  nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
449
  kbdclk_pad : iopad generic map (tech => padtech)
450
      port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
451
  kbdata_pad : iopad generic map (tech => padtech)
452
        port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
453
  mouclk_pad : iopad generic map (tech => padtech)
454
      port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
455
  mouata_pad : iopad generic map (tech => padtech)
456
        port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
457
 
458
  vga : if CFG_VGA_ENABLE /= 0 generate
459
    vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
460
      port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
461
      clk_sel <= "00";
462
  end generate;
463
 
464
  svga : if CFG_SVGA_ENABLE /= 0 generate
465
    svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
466
        hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
467
        clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
468
        clk2 => 1000000000/CPU_FREQ, burstlen => 6)
469
       port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
470
                ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
471
  end generate;
472
 
473
  vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
474
    clkdiv : process(clk1x, rstn)
475
    begin
476
        if rstn = '0' then clkval <= "00";
477
        elsif rising_edge(clk1x) then
478
          clkval <= clkval + 1;
479
        end if;
480
    end process;
481
    video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
482
    b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
483
    dac_clk <= not clkvga;
484
  end generate;
485
 
486
  novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
487
     apbo(6) <= apb_none; vgao <= vgao_none;
488
  end generate;
489
 
490
  blank_pad : outpad generic map (tech => padtech)
491
        port map (vid_blankn, vgao.blank);
492
  comp_sync_pad : outpad generic map (tech => padtech)
493
        port map (vid_syncn, vgao.comp_sync);
494
  vert_sync_pad : outpad generic map (tech => padtech)
495
        port map (vid_vsync, vgao.vsync);
496
  horiz_sync_pad : outpad generic map (tech => padtech)
497
        port map (vid_hsync, vgao.hsync);
498
  video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
499
        port map (vid_r, vgao.video_out_r);
500
  video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
501
        port map (vid_g, vgao.video_out_g);
502
  video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
503
        port map (vid_b, vgao.video_out_b);
504
  video_clock_pad : outpad generic map ( tech => padtech)
505
        port map (tft_lcd_clk, dac_clk);
506
 
507
  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate     -- GPIO unit
508
    grgpio0: grgpio
509
    generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
510
    port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
511
    gpioi => gpioi, gpioo => gpioo);
512
    gpio_pads : iopadvv generic map (tech => padtech, width => 27)
513
      port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
514
                gpioi.din(26 downto 0));
515
  end generate;
516
 
517
  ahbs : if CFG_AHBSTAT = 1 generate    -- AHB status register
518
    ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
519
        nftslv => CFG_AHBSTATN)
520
      port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
521
  end generate;
522
 
523
  i2cm: if CFG_I2C_ENABLE = 1 generate  -- I2C master
524
    i2c0 : i2cmst
525
      generic map (pindex => 12, paddr => 12, pmask => 16#FFF#, pirq => 11)
526
      port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
527
    i2c_scl_pad : iopad generic map (tech => padtech)
528
      port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
529
    i2c_sda_pad : iopad generic map (tech => padtech)
530
      port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
531
  end generate i2cm;
532
 
533
-----------------------------------------------------------------------
534
---  ETHERNET ---------------------------------------------------------
535
-----------------------------------------------------------------------
536
 
537
    eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
538
      e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
539
        pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
540
        mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
541
        nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
542
        macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
543
        ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
544
      port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
545
        ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
546
        apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
547
 
548
      emdio_pad : iopad generic map (tech => padtech)
549
      port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
550
      etxc_pad : clkpad generic map (tech => padtech, arch => 2)
551
        port map (phy_tx_clk, ethi.tx_clk);
552
      erxc_pad : clkpad generic map (tech => padtech, arch => 2)
553
        port map (phy_rx_clk, ethi.rx_clk);
554
      erxd_pad : inpadv generic map (tech => padtech, width => 8)
555
        port map (phy_rx_data, ethi.rxd(7 downto 0));
556
      erxdv_pad : inpad generic map (tech => padtech)
557
        port map (phy_dv, ethi.rx_dv);
558
      erxer_pad : inpad generic map (tech => padtech)
559
        port map (phy_rx_er, ethi.rx_er);
560
      erxco_pad : inpad generic map (tech => padtech)
561
        port map (phy_col, ethi.rx_col);
562
      erxcr_pad : inpad generic map (tech => padtech)
563
        port map (phy_crs, ethi.rx_crs);
564
 
565
      etxd_pad : outpadv generic map (tech => padtech, width => 8)
566
        port map (phy_tx_data, etho.txd(7 downto 0));
567
      etxen_pad : outpad generic map (tech => padtech)
568
        port map ( phy_tx_en, etho.tx_en);
569
      etxer_pad : outpad generic map (tech => padtech)
570
        port map (phy_tx_er, etho.tx_er);
571
      emdc_pad : outpad generic map (tech => padtech)
572
        port map (phy_mii_clk, etho.mdc);
573
      erst_pad : outpad generic map (tech => padtech)
574
        port map (phy_rst_n, rstn);
575
 
576
      ethi.gtx_clk <= egtx_clk;
577
 
578
    end generate;
579
 
580
-----------------------------------------------------------------------
581
---  AHB RAM ----------------------------------------------------------
582
-----------------------------------------------------------------------
583
 
584
  ocram : if CFG_AHBRAMEN = 1 generate
585
    ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
586
        tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
587
    port map ( rstn, clkm, ahbsi, ahbso(7));
588
  end generate;
589
 
590
-----------------------------------------------------------------------
591
---  AHB DEBUG --------------------------------------------------------
592
-----------------------------------------------------------------------
593
 
594
--  dma0 : ahbdma
595
--    generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
596
--      pindex => 13, paddr => 13, dbuf => 6)
597
--    port map (rstn, clkm, apbi, apbo(13), ahbmi, 
598
--      ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
599
 
600
--  at0 : ahbtrace
601
--  generic map ( hindex  => 7, ioaddr => 16#200#, iomask => 16#E00#,
602
--    tech    => memtech, irq     => 0, kbytes  => 8) 
603
--  port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
604
 
605
-----------------------------------------------------------------------
606
---  Drive unused bus elements  ---------------------------------------
607
-----------------------------------------------------------------------
608
 
609
--  nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
610
--    ahbmo(i) <= ahbm_none;
611
--  end generate;
612
--  nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
613
--  nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
614
 
615
-----------------------------------------------------------------------
616
---  Boot message  ----------------------------------------------------
617
-----------------------------------------------------------------------
618
 
619
-- pragma translate_off
620
  x : report_version
621
  generic map (
622
   msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
623
   msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
624
      & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
625
   msg3 => "Target technology: " & tech_table(fabtech) & ",  memory library: " & tech_table(memtech),
626
   mdel => 1
627
  );
628
-- pragma translate_on
629
end;

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