1 |
2 |
dimamali |
-- Technology and synthesis options
|
2 |
|
|
constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
|
3 |
|
|
constant CFG_MEMTECH : integer := CFG_RAM_TECH;
|
4 |
|
|
constant CFG_PADTECH : integer := CFG_PAD_TECH;
|
5 |
|
|
constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
|
6 |
|
|
constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
|
7 |
|
|
|
8 |
|
|
-- Clock generator
|
9 |
|
|
constant CFG_CLKTECH : integer := CFG_CLK_TECH;
|
10 |
|
|
constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
|
11 |
|
|
constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
|
12 |
|
|
constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
|
13 |
|
|
constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
|
14 |
|
|
constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
|
15 |
|
|
constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
|
16 |
|
|
|
17 |
|
|
-- LEON3 processor core
|
18 |
|
|
constant CFG_LEON3 : integer := CONFIG_LEON3;
|
19 |
|
|
constant CFG_NCPU : integer := CONFIG_PROC_NUM;
|
20 |
|
|
constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
|
21 |
|
|
constant CFG_V8 : integer := CFG_IU_V8;
|
22 |
|
|
constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
|
23 |
|
|
constant CFG_SVT : integer := CONFIG_IU_SVT;
|
24 |
|
|
constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
|
25 |
|
|
constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
|
26 |
|
|
constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
|
27 |
|
|
constant CFG_PWD : integer := CONFIG_PWD*2;
|
28 |
|
|
constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
|
29 |
|
|
constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
|
30 |
|
|
constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
|
31 |
|
|
constant CFG_ISETS : integer := CFG_IU_ISETS;
|
32 |
|
|
constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
|
33 |
|
|
constant CFG_ILINE : integer := CFG_ILINE_SZ;
|
34 |
|
|
constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
|
35 |
|
|
constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
|
36 |
|
|
constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
|
37 |
|
|
constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
|
38 |
|
|
constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
|
39 |
|
|
constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
|
40 |
|
|
constant CFG_DSETS : integer := CFG_IU_DSETS;
|
41 |
|
|
constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
|
42 |
|
|
constant CFG_DLINE : integer := CFG_DLINE_SZ;
|
43 |
|
|
constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
|
44 |
|
|
constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
|
45 |
|
|
constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
|
46 |
|
|
constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
|
47 |
|
|
constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
|
48 |
|
|
constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
|
49 |
|
|
constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
|
50 |
|
|
constant CFG_MMUEN : integer := CONFIG_MMUEN;
|
51 |
|
|
constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
|
52 |
|
|
constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
|
53 |
|
|
constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
|
54 |
|
|
constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
|
55 |
|
|
constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
|
56 |
|
|
constant CFG_ITBSZ : integer := CFG_DSU_ITB;
|
57 |
|
|
constant CFG_ATBSZ : integer := CFG_DSU_ATB;
|
58 |
|
|
constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
|
59 |
|
|
constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
|
60 |
|
|
constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
|
61 |
|
|
constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
|
62 |
|
|
constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
|
63 |
|
|
constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
|
64 |
|
|
constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
|
65 |
|
|
constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
|
66 |
|
|
constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
|
67 |
|
|
|
68 |
|
|
-- AMBA settings
|
69 |
|
|
constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
|
70 |
|
|
constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
|
71 |
|
|
constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
|
72 |
|
|
constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
|
73 |
|
|
constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
|
74 |
|
|
constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
|
75 |
|
|
constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
|
76 |
|
|
constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
|
77 |
|
|
|
78 |
|
|
-- DSU UART
|
79 |
|
|
constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
|
80 |
|
|
|
81 |
|
|
-- JTAG based DSU interface
|
82 |
|
|
constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
|
83 |
|
|
|
84 |
|
|
-- Ethernet DSU
|
85 |
|
|
constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
|
86 |
|
|
constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
|
87 |
|
|
constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
|
88 |
|
|
constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
|
89 |
|
|
constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
|
90 |
|
|
constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
|
91 |
|
|
|
92 |
|
|
-- LEON2 memory controller
|
93 |
|
|
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
|
94 |
|
|
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
|
95 |
|
|
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
|
96 |
|
|
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
|
97 |
|
|
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
|
98 |
|
|
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
|
99 |
|
|
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
|
100 |
|
|
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
|
101 |
|
|
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
102 |
|
|
|
103 |
|
|
-- DDR controller
|
104 |
|
|
constant CFG_DDR2SP : integer := CONFIG_DDR2SP;
|
105 |
|
|
constant CFG_DDR2SP_INIT : integer := CONFIG_DDR2SP_INIT;
|
106 |
|
|
constant CFG_DDR2SP_FREQ : integer := CONFIG_DDR2SP_FREQ;
|
107 |
|
|
constant CFG_DDR2SP_TRFC : integer := CONFIG_DDR2SP_TRFC;
|
108 |
|
|
constant CFG_DDR2SP_DATAWIDTH : integer := CONFIG_DDR2SP_DATAWIDTH;
|
109 |
|
|
constant CFG_DDR2SP_COL : integer := CONFIG_DDR2SP_COL;
|
110 |
|
|
constant CFG_DDR2SP_SIZE : integer := CONFIG_DDR2SP_MBYTE;
|
111 |
|
|
constant CFG_DDR2SP_DELAY0 : integer := CONFIG_DDR2SP_DELAY0;
|
112 |
|
|
constant CFG_DDR2SP_DELAY1 : integer := CONFIG_DDR2SP_DELAY1;
|
113 |
|
|
constant CFG_DDR2SP_DELAY2 : integer := CONFIG_DDR2SP_DELAY2;
|
114 |
|
|
constant CFG_DDR2SP_DELAY3 : integer := CONFIG_DDR2SP_DELAY3;
|
115 |
|
|
constant CFG_DDR2SP_DELAY4 : integer := CONFIG_DDR2SP_DELAY4;
|
116 |
|
|
constant CFG_DDR2SP_DELAY5 : integer := CONFIG_DDR2SP_DELAY5;
|
117 |
|
|
constant CFG_DDR2SP_DELAY6 : integer := CONFIG_DDR2SP_DELAY6;
|
118 |
|
|
constant CFG_DDR2SP_DELAY7 : integer := CONFIG_DDR2SP_DELAY7;
|
119 |
|
|
|
120 |
|
|
-- AHB status register
|
121 |
|
|
constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE;
|
122 |
|
|
constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV;
|
123 |
|
|
|
124 |
|
|
-- AHB ROM
|
125 |
|
|
constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
|
126 |
|
|
constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
|
127 |
|
|
constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
|
128 |
|
|
constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
|
129 |
|
|
constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
|
130 |
|
|
|
131 |
|
|
-- AHB RAM
|
132 |
|
|
constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
|
133 |
|
|
constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
|
134 |
|
|
constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
|
135 |
|
|
|
136 |
|
|
-- Gaisler Ethernet core
|
137 |
|
|
constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
|
138 |
|
|
constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
|
139 |
|
|
constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
|
140 |
|
|
|
141 |
|
|
-- UART 1
|
142 |
|
|
constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
|
143 |
|
|
constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
|
144 |
|
|
|
145 |
|
|
-- LEON3 interrupt controller
|
146 |
|
|
constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
|
147 |
|
|
constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
|
148 |
|
|
|
149 |
|
|
-- Modular timer
|
150 |
|
|
constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
|
151 |
|
|
constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
|
152 |
|
|
constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
|
153 |
|
|
constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
|
154 |
|
|
constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
|
155 |
|
|
constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
|
156 |
|
|
constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
|
157 |
|
|
constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
|
158 |
|
|
|
159 |
|
|
-- GPIO port
|
160 |
|
|
constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
|
161 |
|
|
constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
|
162 |
|
|
constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
|
163 |
|
|
|
164 |
|
|
-- I2C master
|
165 |
|
|
constant CFG_I2C_ENABLE : integer := CONFIG_I2C_ENABLE;
|
166 |
|
|
|
167 |
|
|
-- VGA and PS2/ interface
|
168 |
|
|
constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE;
|
169 |
|
|
constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE;
|
170 |
|
|
constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
|
171 |
|
|
|
172 |
|
|
-- GRLIB debugging
|
173 |
|
|
constant CFG_DUART : integer := CONFIG_DEBUG_UART;
|
174 |
|
|
|