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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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library techmap;
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use techmap.gencomp.all;
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library micron;
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use micron.components.all;
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library cypress;
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use cypress.components.all;
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use work.debug.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 10; -- system clock period
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romwidth : integer := 32; -- rom data width (8/32)
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romdepth : integer := 16; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 18; -- ram address depth
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srambanks : integer := 2 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal sys_clk : std_logic := '0';
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signal sys_rst_in : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal bus_error : std_logic_vector (1 downto 0);
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signal sram_flash_addr : std_logic_vector(23 downto 0);
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signal address : std_logic_vector(24 downto 0);
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signal sram_flash_data, data : std_logic_vector(31 downto 0);
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signal sram_cen : std_logic;
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signal sram_bw : std_logic_vector (3 downto 0);
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signal sram_oen : std_ulogic;
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signal flash_oen : std_ulogic;
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signal sram_flash_we_n : std_ulogic;
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signal flash_cen : std_logic;
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signal flash_adv_n : std_logic;
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signal sram_clk : std_ulogic;
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signal sram_clk_fb : std_ulogic;
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signal sram_mode : std_ulogic;
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signal sram_adv_ld_n : std_ulogic;
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signal iosn : std_ulogic;
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signal ddr_clk : std_logic_vector(1 downto 0);
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signal ddr_clkb : std_logic_vector(1 downto 0);
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signal ddr_cke : std_logic_vector(1 downto 0);
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signal ddr_csb : std_logic_vector(1 downto 0);
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signal ddr_odt : std_logic_vector(1 downto 0);
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signal ddr_web : std_ulogic; -- ddr write enable
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signal ddr_rasb : std_ulogic; -- ddr ras
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signal ddr_casb : std_ulogic; -- ddr cas
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signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
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signal ddr_dqsp : std_logic_vector (7 downto 0); -- ddr dqs
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signal ddr_dqsn : std_logic_vector (7 downto 0); -- ddr dqs
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signal ddr_rdqs : std_logic_vector (7 downto 0); -- ddr dqs
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signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
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signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
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signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
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signal txd1 : std_ulogic; -- UART1 tx data
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signal rxd1 : std_ulogic; -- UART1 rx data
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signal gpio : std_logic_vector(12 downto 0); -- I/O port
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signal led : std_logic_vector(12 downto 0); -- I/O port
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signal phy_mii_data: std_logic; -- ethernet PHY interface
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signal phy_tx_clk : std_ulogic;
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signal phy_rx_clk : std_ulogic;
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signal phy_rx_data : std_logic_vector(7 downto 0);
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signal phy_dv : std_ulogic;
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signal phy_rx_er : std_ulogic;
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signal phy_col : std_ulogic;
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signal phy_crs : std_ulogic;
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signal phy_tx_data : std_logic_vector(7 downto 0);
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signal phy_tx_en : std_ulogic;
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signal phy_tx_er : std_ulogic;
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signal phy_mii_clk : std_ulogic;
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signal phy_rst_n : std_ulogic;
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signal phy_gtx_clk : std_ulogic;
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signal ps2_keyb_clk: std_logic;
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signal ps2_keyb_data: std_logic;
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signal ps2_mouse_clk: std_logic;
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signal ps2_mouse_data: std_logic;
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signal tft_lcd_clk : std_ulogic;
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signal vid_blankn : std_ulogic;
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signal vid_syncn : std_ulogic;
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signal vid_hsync : std_ulogic;
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signal vid_vsync : std_ulogic;
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signal vid_r : std_logic_vector(7 downto 0);
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signal vid_g : std_logic_vector(7 downto 0);
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signal vid_b : std_logic_vector(7 downto 0);
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signal usb_csn, usb_rstn : std_logic;
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signal iic_scl_main, iic_sda_main : std_logic;
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk_200_p : std_ulogic := '0';
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signal clk_200_n : std_ulogic := '1';
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constant lresp : boolean := false;
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begin
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-- clock and reset
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sys_clk <= not sys_clk after ct * 1 ns;
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sys_rst_in <= '0', '1' after 200 ns;
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clk_200_p <= not clk_200_p after 8 ns;
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clk_200_n <= not clk_200_n after 8 ns;
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rxd1 <= 'H';
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sram_clk_fb <= sram_clk;
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ps2_keyb_data <= 'H'; ps2_keyb_clk <= 'H';
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ps2_mouse_clk <= 'H'; ps2_mouse_data <= 'H';
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iic_scl_main <= 'H'; iic_sda_main <= 'H';
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cpu : entity work.leon3mp
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generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
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port map ( sys_rst_in, sys_clk, clk_200_p, clk_200_n, sram_flash_addr,
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sram_flash_data, sram_cen, sram_bw, sram_oen, sram_flash_we_n,
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flash_cen, flash_oen, flash_adv_n,sram_clk, sram_clk_fb, sram_mode,
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sram_adv_ld_n, iosn,
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ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_odt, ddr_web,
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ddr_rasb, ddr_casb, ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq,
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txd1, rxd1, gpio, led, bus_error,
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phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
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phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs,
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phy_tx_data, phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n,
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ps2_keyb_clk, ps2_keyb_data, ps2_mouse_clk, ps2_mouse_data,
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usb_csn, usb_rstn,
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iic_scl_main, iic_sda_main
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);
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ddr2mem : for i in 0 to 3 generate
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u1 : ddr2
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PORT MAP(
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ck => ddr_clk(0), ck_n => ddr_clkb(0), cke => ddr_cke(0), cs_n => ddr_csb(0),
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ras_n => ddr_rasb, cas_n => ddr_casb, we_n => ddr_web,
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dm_rdqs => ddr_dm(i*2+1 downto i*2), ba => ddr_ba,
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addr => ddr_ad(12 downto 0), dq => ddr_dq(i*16+15 downto i*16),
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dqs => ddr_dqsp(i*2+1 downto i*2), dqs_n => ddr_dqsn(i*2+1 downto i*2),
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rdqs_n => ddr_rdqs(i*2+1 downto i*2), odt => ddr_odt(0));
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end generate;
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sram01 : for i in 0 to 1 generate
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sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
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port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(15-i*8 downto 8-i*8),
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sram_cen, sram_bw(i+2), sram_oen);
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end generate;
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sram23 : for i in 2 to 3 generate
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sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
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port map (sram_flash_addr(sramdepth downto 1), sram_flash_data(47-i*8 downto 40-i*8),
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sram_cen, sram_bw(i-2), sram_oen);
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end generate;
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prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
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port map (sram_flash_addr(romdepth-1 downto 0), sram_flash_data(15 downto 0),
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gnd, gnd, flash_cen, sram_flash_we_n, flash_oen);
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-- p0: phy
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-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
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-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
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i0: i2c_slave_model
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port map (iic_scl_main, iic_sda_main);
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iuerr : process
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begin
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wait for 5000 ns;
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if to_x01(bus_error(0)) = '0' then wait on bus_error; end if;
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assert (to_x01(bus_error(0)) = '0')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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data <= sram_flash_data(15 downto 0) & sram_flash_data(31 downto 16);
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address <= sram_flash_addr & '0';
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test0 : grtestmod
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port map ( sys_rst_in, sys_clk, bus_error(0), sram_flash_addr(20 downto 1), data,
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iosn, flash_oen, sram_bw(0), open);
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sram_flash_data <= buskeep(sram_flash_data), (others => 'H') after 250 ns;
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ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
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data <= buskeep(data), (others => 'H') after 250 ns;
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end ;
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