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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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sys_rst_in : in std_ulogic;
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clk_100 : in std_ulogic; -- 100 MHz main clock
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clk_200_p : in std_ulogic; -- 200 MHz
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clk_200_n : in std_ulogic; -- 200 MHz
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sram_flash_addr : out std_logic_vector(23 downto 0);
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sram_flash_data : inout std_logic_vector(31 downto 0);
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sram_cen : out std_logic;
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sram_bw : out std_logic_vector (0 to 3);
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sram_oen : out std_ulogic;
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sram_flash_we_n : out std_ulogic;
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flash_ce : out std_logic;
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flash_oen : out std_logic;
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flash_adv_n : out std_logic;
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sram_clk : out std_ulogic;
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sram_clk_fb : in std_ulogic;
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sram_mode : out std_ulogic;
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sram_adv_ld_n : out std_ulogic;
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--pragma translate_off
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iosn : out std_ulogic;
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--pragma translate_on
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ddr_clk : out std_logic_vector(1 downto 0);
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ddr_clkb : out std_logic_vector(1 downto 0);
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_odt : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
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ddr_dqsp : inout std_logic_vector (7 downto 0); -- ddr dqs
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ddr_dqsn : inout std_logic_vector (7 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
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txd1 : out std_ulogic; -- UART1 tx data
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rxd1 : in std_ulogic; -- UART1 rx data
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txd2 : out std_ulogic; -- UART2 tx data
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rxd2 : in std_ulogic; -- UART2 rx data
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gpio : inout std_logic_vector(12 downto 0); -- I/O port
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led : out std_logic_vector(12 downto 0);
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bus_error : out std_logic_vector(1 downto 0);
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phy_gtx_clk : out std_logic;
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phy_mii_data: inout std_logic; -- ethernet PHY interface
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phy_tx_clk : in std_ulogic;
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phy_rx_clk : in std_ulogic;
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phy_rx_data : in std_logic_vector(7 downto 0);
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phy_dv : in std_ulogic;
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phy_rx_er : in std_ulogic;
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phy_col : in std_ulogic;
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phy_crs : in std_ulogic;
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phy_tx_data : out std_logic_vector(7 downto 0);
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phy_tx_en : out std_ulogic;
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phy_tx_er : out std_ulogic;
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phy_mii_clk : out std_ulogic;
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phy_rst_n : out std_ulogic;
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ps2_keyb_clk: inout std_logic;
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ps2_keyb_data: inout std_logic;
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ps2_mouse_clk: inout std_logic;
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ps2_mouse_data: inout std_logic;
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-- tft_lcd_clk : out std_ulogic;
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-- vid_blankn : out std_ulogic;
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-- vid_syncn : out std_ulogic;
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-- vid_hsync : out std_ulogic;
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-- vid_vsync : out std_ulogic;
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-- vid_r : out std_logic_vector(7 downto 0);
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-- vid_g : out std_logic_vector(7 downto 0);
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-- vid_b : out std_logic_vector(7 downto 0);
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usb_csn : out std_logic;
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usb_rstn : out std_logic;
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iic_scl_main : inout std_ulogic;
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iic_sda_main : inout std_ulogic
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := NCPU+CFG_AHB_UART
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+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
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signal ddr_clk_fb : std_logic;
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdctrl_out_type;
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signal sdo2, sdo3 : sdctrl_out_type;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clkm, rstn, rstraw, srclkl : std_ulogic;
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signal clkm_90, clkm_180, clkm_270 : std_ulogic;
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signal clk_200 : std_ulogic;
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signal cgi, cgi2 : clkgen_in_type;
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signal cgo, cgo2 : clkgen_out_type;
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signal u1i, u2i, dui : uart_in_type;
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signal u1o, u2o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to NCPU-1);
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signal irqo : irq_out_vector(0 to NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal ethi, ethi1, ethi2 : eth_in_type;
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signal etho, etho1, etho2 : eth_out_type;
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signal gpti : gptimer_in_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
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signal tck, tckn, tms, tdi, tdo : std_ulogic;
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signal ddrclk, ddrrst : std_ulogic;
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signal ethclk, egtx_clk_fb : std_ulogic;
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signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
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signal kbdi : ps2_in_type;
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signal kbdo : ps2_out_type;
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signal moui : ps2_in_type;
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signal mouo : ps2_out_type;
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signal vgao : apbvga_out_type;
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signal clk_sel : std_logic_vector(1 downto 0);
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signal clkval : std_logic_vector(1 downto 0);
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signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
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signal i2ci : i2c_in_type;
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signal i2co : i2c_out_type;
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constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
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constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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constant IOAEN : integer := CFG_DDR2SP;
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signal stati : ahbstat_in_type;
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signal ddsi : ddrmem_in_type;
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signal ddso : ddrmem_out_type;
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signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
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signal ddr_clkv : std_logic_vector(2 downto 0);
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signal ddr_clkbv : std_logic_vector(2 downto 0);
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signal ddr_ckev : std_logic_vector(1 downto 0);
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signal ddr_csbv : std_logic_vector(1 downto 0);
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signal ddr_adl : std_logic_vector (13 downto 0);
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of clkml : signal is true;
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attribute syn_preserve of clkml : signal is true;
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attribute syn_keep of egtx_clk : signal is true;
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attribute syn_preserve of egtx_clk : signal is true;
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attribute keep : boolean;
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attribute keep of lock : signal is true;
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attribute keep of clkml : signal is true;
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attribute keep of clkm : signal is true;
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attribute keep of egtx_clk : signal is true;
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signal romsn : std_ulogic;
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constant SPW_LOOP_BACK : integer := 0;
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begin
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usb_csn <= '1';
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usb_rstn <= rstn;
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
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ssrref_pad : clkpad generic map (tech => padtech)
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port map (sram_clk_fb, ssrclkfb);
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clk_pad : clkpad generic map (tech => padtech, arch => 2)
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port map (clk_100, lclk);
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clk200_pad : clkpad_ds generic map (tech => padtech, level => lvds, voltage => x25v)
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port map (clk_200_p, clk_200_n, clk_200);
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srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
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port map (sram_clk, srclkl);
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clkgen0 : clkgen -- system clock generator
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generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
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port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
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clkgen1 : clkgen -- Ethernet 1G PHY clock generator
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generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
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port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
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cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
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egtx_clk_pad : outpad generic map (tech => padtech)
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port map (phy_gtx_clk, egtx_clk);
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resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
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rst0 : rstgen -- reset generator
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port map (rst, clkm, clklock, rstn, rstraw);
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clklock <= lock and cgo2.clklock;
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML506,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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bus_error(0) <= not dbgo(0).error;
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dsugen : if CFG_DSU = 1 generate
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|
|
dsu0 : dsu3 -- LEON3 Debug Support Unit
|
304 |
|
|
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
|
305 |
|
|
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
|
306 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
|
307 |
|
|
dsui.enable <= '1';
|
308 |
|
|
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
|
309 |
|
|
dsui.break <= gpioo.val(24); -- South Button
|
310 |
|
|
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
|
311 |
|
|
led(4) <= dsuo.active;
|
312 |
|
|
end generate;
|
313 |
|
|
end generate;
|
314 |
|
|
|
315 |
|
|
nodsu : if CFG_DSU = 0 generate
|
316 |
|
|
dsuo.tstop <= '0'; dsuo.active <= '0';
|
317 |
|
|
end generate;
|
318 |
|
|
|
319 |
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
320 |
|
|
dcom0: ahbuart -- Debug UART
|
321 |
|
|
generic map (hindex => NCPU, pindex => 7, paddr => 7)
|
322 |
|
|
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
|
323 |
|
|
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
|
324 |
|
|
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
|
325 |
|
|
dui.rxd <= rxd1 when gpioo.val(0) = '1' else '1';
|
326 |
|
|
end generate;
|
327 |
|
|
|
328 |
|
|
txd1 <= duo.txd when gpioo.val(0) = '1' else u1o.txd;
|
329 |
|
|
|
330 |
|
|
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
|
331 |
|
|
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
|
332 |
|
|
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
|
333 |
|
|
open, open, open, open, open, open, open, gnd(0));
|
334 |
|
|
end generate;
|
335 |
|
|
|
336 |
|
|
----------------------------------------------------------------------
|
337 |
|
|
--- Memory controllers ----------------------------------------------
|
338 |
|
|
----------------------------------------------------------------------
|
339 |
|
|
|
340 |
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
|
341 |
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
342 |
|
|
|
343 |
|
|
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
|
344 |
|
|
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
|
345 |
|
|
ramaddr => 16#400# + CFG_DDR2SP*16#800#, rammask => 16#FE0#,
|
346 |
|
|
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
|
347 |
|
|
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
|
348 |
|
|
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
|
349 |
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
|
350 |
|
|
end generate;
|
351 |
|
|
|
352 |
|
|
flash_adv_n_pad : outpad generic map (tech => padtech)
|
353 |
|
|
port map (flash_adv_n, gnd(0));
|
354 |
|
|
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
|
355 |
|
|
port map (sram_adv_ld_n, gnd(0));
|
356 |
|
|
sram_mode_pad : outpad generic map (tech => padtech)
|
357 |
|
|
port map (sram_mode, gnd(0));
|
358 |
|
|
addr_pad : outpadv generic map (width => 24, tech => padtech)
|
359 |
|
|
port map (sram_flash_addr, memo.address(24 downto 1));
|
360 |
|
|
rams_pad : outpad generic map ( tech => padtech)
|
361 |
|
|
port map (sram_cen, memo.ramsn(0));
|
362 |
|
|
roms_pad : outpad generic map (tech => padtech)
|
363 |
|
|
port map (flash_ce, memo.romsn(0));
|
364 |
|
|
ramoen_pad : outpad generic map (tech => padtech)
|
365 |
|
|
port map (sram_oen, memo.ramoen(0));
|
366 |
|
|
flash_oen_pad : outpad generic map (tech => padtech)
|
367 |
|
|
port map (flash_oen, memo.oen);
|
368 |
|
|
--pragma translate_off
|
369 |
|
|
iosn_pad : outpad generic map (tech => padtech)
|
370 |
|
|
port map (iosn, memo.iosn);
|
371 |
|
|
--pragma translate_on
|
372 |
|
|
rwen_pad : outpadv generic map (width => 2, tech => padtech)
|
373 |
|
|
port map (sram_bw(0 to 1), memo.wrn(3 downto 2));
|
374 |
|
|
rwen_pad2 : outpadv generic map (width => 2, tech => padtech)
|
375 |
|
|
port map (sram_bw(2 to 3), memo.wrn(1 downto 0));
|
376 |
|
|
wri_pad : outpad generic map (tech => padtech)
|
377 |
|
|
port map (sram_flash_we_n, memo.writen);
|
378 |
|
|
data_pads : iopadvv generic map (tech => padtech, width => 16)
|
379 |
|
|
port map (sram_flash_data(15 downto 0), memo.data(31 downto 16),
|
380 |
|
|
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
|
381 |
|
|
data_pads2 : iopadvv generic map (tech => padtech, width => 16)
|
382 |
|
|
port map (sram_flash_data(31 downto 16), memo.data(15 downto 0),
|
383 |
|
|
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
|
384 |
|
|
|
385 |
|
|
ddrsp0 : if (CFG_DDR2SP /= 0) generate
|
386 |
|
|
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
|
387 |
|
|
hindex => 0, haddr => 16#400#, hmask => 16#E00#, ioaddr => 1,
|
388 |
|
|
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ_200/1000, TRFC => CFG_DDR2SP_TRFC,
|
389 |
|
|
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => 20, ahbfreq => CPU_FREQ/1000,
|
390 |
|
|
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64,
|
391 |
|
|
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
|
392 |
|
|
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
|
393 |
|
|
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
|
394 |
|
|
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
|
395 |
|
|
numidelctrl => 3, norefclk => 0, odten => 3)
|
396 |
|
|
port map ( rst, rstn, clk_200, clkm, clk_200, lock, clkml, clkml, ahbsi, ahbso(0),
|
397 |
|
|
ddr_clkv, ddr_clkbv, ddr_clk_fb, ddr_clk_fb, ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
|
398 |
|
|
ddr_dm, ddr_dqsp, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_odt);
|
399 |
|
|
ddr_clk <= ddr_clkv(1 downto 0); ddr_clkb <= ddr_clkbv(1 downto 0);
|
400 |
|
|
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
|
401 |
|
|
end generate;
|
402 |
|
|
|
403 |
|
|
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
|
404 |
|
|
|
405 |
|
|
----------------------------------------------------------------------
|
406 |
|
|
--- APB Bridge and various periherals -------------------------------
|
407 |
|
|
----------------------------------------------------------------------
|
408 |
|
|
|
409 |
|
|
bpromgen : if CFG_AHBROMEN /= 0 generate
|
410 |
|
|
brom : entity work.ahbrom
|
411 |
|
|
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
|
412 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(6));
|
413 |
|
|
end generate;
|
414 |
|
|
|
415 |
|
|
----------------------------------------------------------------------
|
416 |
|
|
--- APB Bridge and various periherals -------------------------------
|
417 |
|
|
----------------------------------------------------------------------
|
418 |
|
|
|
419 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
420 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
|
421 |
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
|
422 |
|
|
|
423 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
424 |
|
|
uart1 : apbuart -- UART 1
|
425 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
426 |
|
|
fifosize => CFG_UART1_FIFO)
|
427 |
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
428 |
|
|
u1i.extclk <= '0'; u1i.ctsn <= '0';
|
429 |
|
|
u1i.rxd <= rxd1 when gpioo.val(0) = '0' else '1';
|
430 |
|
|
end generate;
|
431 |
|
|
|
432 |
|
|
led(0) <= gpioo.val(0); led(1) <= not rxd1;
|
433 |
|
|
led(2) <= not duo.txd when gpioo.val(0) = '1' else not u1o.txd;
|
434 |
|
|
|
435 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
436 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
437 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
|
438 |
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
439 |
|
|
end generate;
|
440 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
441 |
|
|
x : for i in 0 to NCPU-1 generate
|
442 |
|
|
irqi(i).irl <= "0000";
|
443 |
|
|
end generate;
|
444 |
|
|
apbo(2) <= apb_none;
|
445 |
|
|
end generate;
|
446 |
|
|
|
447 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
448 |
|
|
timer0 : gptimer -- timer unit
|
449 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
450 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
451 |
|
|
nbits => CFG_GPT_TW)
|
452 |
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
453 |
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
454 |
|
|
end generate;
|
455 |
|
|
|
456 |
|
|
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
457 |
|
|
|
458 |
|
|
kbd : if CFG_KBD_ENABLE /= 0 generate
|
459 |
|
|
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
|
460 |
|
|
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
|
461 |
|
|
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
|
462 |
|
|
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
|
463 |
|
|
end generate;
|
464 |
|
|
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
|
465 |
|
|
kbdclk_pad : iopad generic map (tech => padtech)
|
466 |
|
|
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
|
467 |
|
|
kbdata_pad : iopad generic map (tech => padtech)
|
468 |
|
|
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
|
469 |
|
|
mouclk_pad : iopad generic map (tech => padtech)
|
470 |
|
|
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
|
471 |
|
|
mouata_pad : iopad generic map (tech => padtech)
|
472 |
|
|
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
|
473 |
|
|
|
474 |
|
|
vga : if CFG_VGA_ENABLE /= 0 generate
|
475 |
|
|
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
|
476 |
|
|
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
|
477 |
|
|
clk_sel <= "00";
|
478 |
|
|
end generate;
|
479 |
|
|
|
480 |
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate
|
481 |
|
|
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
|
482 |
|
|
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
483 |
|
|
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
|
484 |
|
|
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
|
485 |
|
|
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
|
486 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
|
487 |
|
|
end generate;
|
488 |
|
|
|
489 |
|
|
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
|
490 |
|
|
clkdiv : process(clk1x, rstn)
|
491 |
|
|
begin
|
492 |
|
|
if rstn = '0' then clkval <= "00";
|
493 |
|
|
elsif rising_edge(clk1x) then
|
494 |
|
|
clkval <= clkval + 1;
|
495 |
|
|
end if;
|
496 |
|
|
end process;
|
497 |
|
|
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
|
498 |
|
|
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
|
499 |
|
|
dac_clk <= not clkvga;
|
500 |
|
|
end generate;
|
501 |
|
|
|
502 |
|
|
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
|
503 |
|
|
apbo(6) <= apb_none; vgao <= vgao_none;
|
504 |
|
|
end generate;
|
505 |
|
|
|
506 |
|
|
-- blank_pad : outpad generic map (tech => padtech)
|
507 |
|
|
-- port map (vid_blankn, vgao.blank);
|
508 |
|
|
-- comp_sync_pad : outpad generic map (tech => padtech)
|
509 |
|
|
-- port map (vid_syncn, vgao.comp_sync);
|
510 |
|
|
-- vert_sync_pad : outpad generic map (tech => padtech)
|
511 |
|
|
-- port map (vid_vsync, vgao.vsync);
|
512 |
|
|
-- horiz_sync_pad : outpad generic map (tech => padtech)
|
513 |
|
|
-- port map (vid_hsync, vgao.hsync);
|
514 |
|
|
-- video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
|
515 |
|
|
-- port map (vid_r, vgao.video_out_r);
|
516 |
|
|
-- video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
|
517 |
|
|
-- port map (vid_g, vgao.video_out_g);
|
518 |
|
|
-- video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
|
519 |
|
|
-- port map (vid_b, vgao.video_out_b);
|
520 |
|
|
-- video_clock_pad : outpad generic map ( tech => padtech)
|
521 |
|
|
-- port map (tft_lcd_clk, dac_clk);
|
522 |
|
|
|
523 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
|
524 |
|
|
grgpio0: grgpio
|
525 |
|
|
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 13)
|
526 |
|
|
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
|
527 |
|
|
gpioi => gpioi, gpioo => gpioo);
|
528 |
|
|
gpio_pads : iopadvv generic map (tech => padtech, width => 13)
|
529 |
|
|
port map (gpio, gpioo.dout(12 downto 0), gpioo.oen(12 downto 0),
|
530 |
|
|
gpioi.din(12 downto 0));
|
531 |
|
|
end generate;
|
532 |
|
|
|
533 |
|
|
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
|
534 |
|
|
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
|
535 |
|
|
nftslv => CFG_AHBSTATN)
|
536 |
|
|
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
|
537 |
|
|
end generate;
|
538 |
|
|
|
539 |
|
|
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
|
540 |
|
|
i2c0 : i2cmst
|
541 |
|
|
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#, pirq => 11)
|
542 |
|
|
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
|
543 |
|
|
i2c_scl_pad : iopad generic map (tech => padtech)
|
544 |
|
|
port map (iic_scl_main, i2co.scl, i2co.scloen, i2ci.scl);
|
545 |
|
|
i2c_sda_pad : iopad generic map (tech => padtech)
|
546 |
|
|
port map (iic_sda_main, i2co.sda, i2co.sdaoen, i2ci.sda);
|
547 |
|
|
end generate i2cm;
|
548 |
|
|
|
549 |
|
|
-----------------------------------------------------------------------
|
550 |
|
|
--- ETHERNET ---------------------------------------------------------
|
551 |
|
|
-----------------------------------------------------------------------
|
552 |
|
|
|
553 |
|
|
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
|
554 |
|
|
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
|
555 |
|
|
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
|
556 |
|
|
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
|
557 |
|
|
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
|
558 |
|
|
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
|
559 |
|
|
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
|
560 |
|
|
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
|
561 |
|
|
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
|
562 |
|
|
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
|
563 |
|
|
|
564 |
|
|
emdio_pad : iopad generic map (tech => padtech)
|
565 |
|
|
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
|
566 |
|
|
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
567 |
|
|
port map (phy_tx_clk, ethi.tx_clk);
|
568 |
|
|
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
|
569 |
|
|
port map (phy_rx_clk, ethi.rx_clk);
|
570 |
|
|
erxd_pad : inpadv generic map (tech => padtech, width => 8)
|
571 |
|
|
port map (phy_rx_data, ethi.rxd(7 downto 0));
|
572 |
|
|
erxdv_pad : inpad generic map (tech => padtech)
|
573 |
|
|
port map (phy_dv, ethi.rx_dv);
|
574 |
|
|
erxer_pad : inpad generic map (tech => padtech)
|
575 |
|
|
port map (phy_rx_er, ethi.rx_er);
|
576 |
|
|
erxco_pad : inpad generic map (tech => padtech)
|
577 |
|
|
port map (phy_col, ethi.rx_col);
|
578 |
|
|
erxcr_pad : inpad generic map (tech => padtech)
|
579 |
|
|
port map (phy_crs, ethi.rx_crs);
|
580 |
|
|
|
581 |
|
|
etxd_pad : outpadv generic map (tech => padtech, width => 8)
|
582 |
|
|
port map (phy_tx_data, etho.txd(7 downto 0));
|
583 |
|
|
etxen_pad : outpad generic map (tech => padtech)
|
584 |
|
|
port map ( phy_tx_en, etho.tx_en);
|
585 |
|
|
etxer_pad : outpad generic map (tech => padtech)
|
586 |
|
|
port map (phy_tx_er, etho.tx_er);
|
587 |
|
|
emdc_pad : outpad generic map (tech => padtech)
|
588 |
|
|
port map (phy_mii_clk, etho.mdc);
|
589 |
|
|
erst_pad : outpad generic map (tech => padtech)
|
590 |
|
|
port map (phy_rst_n, rstn);
|
591 |
|
|
|
592 |
|
|
ethi.gtx_clk <= egtx_clk;
|
593 |
|
|
|
594 |
|
|
end generate;
|
595 |
|
|
|
596 |
|
|
-----------------------------------------------------------------------
|
597 |
|
|
--- AHB RAM ----------------------------------------------------------
|
598 |
|
|
-----------------------------------------------------------------------
|
599 |
|
|
|
600 |
|
|
ocram : if CFG_AHBRAMEN = 1 generate
|
601 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
602 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
603 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(7));
|
604 |
|
|
end generate;
|
605 |
|
|
|
606 |
|
|
-----------------------------------------------------------------------
|
607 |
|
|
--- AHB DEBUG --------------------------------------------------------
|
608 |
|
|
-----------------------------------------------------------------------
|
609 |
|
|
|
610 |
|
|
-- dma0 : ahbdma
|
611 |
|
|
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
|
612 |
|
|
-- pindex => 13, paddr => 13, dbuf => 6)
|
613 |
|
|
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
|
614 |
|
|
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
|
615 |
|
|
|
616 |
|
|
-- at0 : ahbtrace
|
617 |
|
|
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
|
618 |
|
|
-- tech => memtech, irq => 0, kbytes => 8)
|
619 |
|
|
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
|
620 |
|
|
|
621 |
|
|
-----------------------------------------------------------------------
|
622 |
|
|
--- Drive unused bus elements ---------------------------------------
|
623 |
|
|
-----------------------------------------------------------------------
|
624 |
|
|
|
625 |
|
|
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
|
626 |
|
|
-- ahbmo(i) <= ahbm_none;
|
627 |
|
|
-- end generate;
|
628 |
|
|
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
629 |
|
|
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
630 |
|
|
|
631 |
|
|
-----------------------------------------------------------------------
|
632 |
|
|
--- Boot message ----------------------------------------------------
|
633 |
|
|
-----------------------------------------------------------------------
|
634 |
|
|
|
635 |
|
|
-- pragma translate_off
|
636 |
|
|
x : report_version
|
637 |
|
|
generic map (
|
638 |
|
|
msg1 => system_table(XILINX_ML506),
|
639 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
640 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
641 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
642 |
|
|
mdel => 1
|
643 |
|
|
);
|
644 |
|
|
-- pragma translate_on
|
645 |
|
|
end;
|