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dimamali |
This leon3 design is tailored to the Xilinx XtremeDSP Starter Platform, Spartan-3A DSP 1800A Edition
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http://www.xilinx.com/s3adspstarter
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This design can not be simulated without making some small
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modifications to the design. The reason for this is that the
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simulation model of the DDR2 memory does not support preloading of
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data and can thus not be used as main memory (at least not without
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excessive simulation time for loading instructions/data into memory).
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The DDR2 memory is mapped to address 0x60000000 during simulation,
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instead of 0x40000000 that is used during synthesis. The reason for
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this is that the DDR2 memory simulation model can not be initialized
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with data. So to avoid excessive simulation times, where data has to
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be written to the memory, an SDRAM is mapped to address 0x40000000
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during simulation.
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Synplify version 9.4 is prefered for synthesis, since earlier versions
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have shown tendencies to create incorrect results.
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Design specifics:
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* System reset is mapped to SW5 (reset)
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* DSU break is mapped to SW6
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* LED 13/14 indicates DSU UART TX and RX activity.
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* LED 12 indicates processor in debug mode
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* LED 11 indicates if the DLL in the DDR2 memory controller is locked
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to the system clock
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* LED 7 indicates processor in error mode
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* The GRETH core is enabled and runs without problems at 100 Mbit.
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Ethernet debug link is enabled, default IP is 192.168.0.51.
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* 8-bit flash prom can be read at address 0. It can be programmed
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with GRMON version 1.1.16 or later.
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* DDR2 is mapped at address 0x40000000 (128 Mbyte) and is clocked
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at 125 MHz. The processor and AMBA system runs on a different
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clock, and can typically reach 40 MHz. The processor clock
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is generated from the 125 MHz clock oscillator, scaled with the
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DCM factors (7/20) in xconfig.
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* The application UART1 is connected to the male RS232 connector.
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* The JTAG DSU interface is enabled.
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* Output from GRMON info sys is:
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grmon -eth -u
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GRMON LEON debug monitor v1.1.31
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Copyright (C) 2004-2008 Gaisler Research - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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Xilinx cable: Cable type/rev : 0x3
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JTAG chain: xc3sd1800a
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GRLIB build version: 3107
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initialising ............
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detected frequency: 45 MHz
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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SVGA frame buffer Gaisler Research
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GR Ethernet MAC Gaisler Research
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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DDR2 Controller Gaisler Research
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LEON2 Memory Controller European Space Agency
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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General purpose I/O port Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> info sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
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ahb master 1
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02.01:063 Gaisler Research SVGA frame buffer (ver 0x0)
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ahb master 2
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apb: 80000600 - 80000700
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clk0: 25.00 MHz
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03.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
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ahb master 3, irq 12
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apb: 80000f00 - 80001000
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edcl ip 192.168.0.51, buffer 2 kbyte
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 256 lines, stack pointer 0x47fffff0
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CPU#0 win 8, itrace 256, V8 mul/div, srmmu, lddel 1
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icache 2 * 4 kbyte, 32 byte/line rnd
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dcache 2 * 4 kbyte, 16 byte/line rnd
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04.01:02e Gaisler Research DDR2 Controller (ver 0x0)
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ahb: 40000000 - 48000000
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ahb: fff00100 - fff00200
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32-bit DDR2 : 1 * 128 Mbyte @ 0x40000000
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125 MHz, col 10, ref 7.8 us
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05.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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ahb: 20000000 - 40000000
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apb: 80000000 - 80000100
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8-bit prom @ 0x00000000
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38527
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 45
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0b.01:01a Gaisler Research General purpose I/O port (ver 0x0)
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apb: 80000b00 - 80000c00
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grlib>
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