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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.pci.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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use gaisler.spacewire.all;
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library esa;
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use esa.memoryctrl.all;
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use esa.pcicomp.all;
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use work.config.all;
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use work.config.all;
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entity core is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic;
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errorn : out std_ulogic;
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address : out std_logic_vector(27 downto 0);
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datain : in std_logic_vector(31 downto 0);
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dataout : out std_logic_vector(31 downto 0);
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dataen : out std_logic_vector(31 downto 0);
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cbin : in std_logic_vector(7 downto 0);
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cbout : out std_logic_vector(7 downto 0);
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cben : out std_logic_vector(7 downto 0);
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sdclk : out std_ulogic;
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sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
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sdwen : out std_ulogic; -- sdram write enable
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sdrasn : out std_ulogic; -- sdram ras
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sdcasn : out std_ulogic; -- sdram cas
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sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
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dsutx : out std_ulogic; -- DSU tx data
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dsurx : in std_ulogic; -- DSU rx data
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dsuen : in std_ulogic;
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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txd1 : out std_ulogic; -- UART1 tx data
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rxd1 : in std_ulogic; -- UART1 rx data
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ramsn : out std_logic_vector (4 downto 0);
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ramoen : out std_logic_vector (4 downto 0);
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rwen : out std_logic_vector (3 downto 0);
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oen : out std_ulogic;
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writen : out std_ulogic;
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read : out std_ulogic;
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iosn : out std_ulogic;
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romsn : out std_logic_vector (1 downto 0);
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brdyn : in std_ulogic;
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bexcn : in std_ulogic;
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wdogn : out std_ulogic;
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gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
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writefb : in std_ulogic;
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emdi : in std_logic; -- ethernet PHY interface
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emdo : out std_logic; -- ethernet PHY interface
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emden : out std_logic; -- ethernet PHY interface
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etx_clk : in std_ulogic;
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erx_clk : in std_ulogic;
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erxd : in std_logic_vector(3 downto 0);
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erx_dv : in std_ulogic;
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erx_er : in std_ulogic;
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erx_col : in std_ulogic;
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erx_crs : in std_ulogic;
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etxd : out std_logic_vector(3 downto 0);
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etx_en : out std_ulogic;
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etx_er : out std_ulogic;
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emdc : out std_ulogic;
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pciclk : in std_ulogic;
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pcii_rst : in std_ulogic;
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pcii_gnt : in std_ulogic;
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pcii_idsel : in std_ulogic;
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pcii_ad : in std_logic_vector(31 downto 0);
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pcii_cbe : in std_logic_vector(3 downto 0);
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pcii_frame : in std_ulogic;
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pcii_irdy : in std_ulogic;
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pcii_trdy : in std_ulogic;
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pcii_devsel : in std_ulogic;
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pcii_stop : in std_ulogic;
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pcii_perr : in std_ulogic;
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pcii_par : in std_ulogic;
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pcii_host : in std_ulogic;
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pcio_vaden : out std_logic_vector(31 downto 0);
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pcio_cbeen : out std_logic_vector(3 downto 0);
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pcio_frameen : out std_ulogic;
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pcio_irdyen : out std_ulogic;
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pcio_trdyen : out std_ulogic;
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pcio_devselen: out std_ulogic;
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pcio_stopen : out std_ulogic;
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pcio_perren : out std_ulogic;
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pcio_paren : out std_ulogic;
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pcio_reqen : out std_ulogic;
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pcio_locken : out std_ulogic;
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pcio_req : out std_ulogic;
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pcio_ad : out std_logic_vector(31 downto 0);
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pcio_cbe : out std_logic_vector(3 downto 0);
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pcio_frame : out std_ulogic;
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pcio_irdy : out std_ulogic;
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pcio_trdy : out std_ulogic;
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pcio_devsel : out std_ulogic;
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pcio_stop : out std_ulogic;
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pcio_perr : out std_ulogic;
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pcio_par : out std_ulogic;
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pcii_arb_req: in std_logic_vector(0 to CFG_PCI_ARB_NGNT-1);
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pcio_arb_gnt: out std_logic_vector(0 to CFG_PCI_ARB_NGNT-1);
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can_tx : out std_logic_vector(0 to CFG_CAN_NUM-1);
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can_rx : in std_logic_vector(0 to CFG_CAN_NUM-1);
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spw_clk : in std_ulogic;
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spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
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spw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
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tck : in std_ulogic;
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tms : in std_ulogic;
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tdi : in std_ulogic;
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tdo : out std_ulogic;
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trst : in std_ulogic;
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test : in std_ulogic;
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pllref : in std_ulogic
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);
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end;
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architecture rtl of core is
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constant ISASIC : boolean := (is_fpga(fabtech) = 0);
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signal lclk, lspw_clk, lpciclk : std_ulogic;
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signal letx_clk, lerx_clk, ltck : std_ulogic;
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signal lletx_clk, llerx_clk, llspw_clk, llpciclk : std_ulogic;
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signal gclk, pwd, lpwd : std_logic_vector(0 to 0);
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signal scanin, scanout, scanen, ldsutx, testrst : std_ulogic;
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signal ldataen : std_logic_vector(31 downto 0);
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signal lcben : std_logic_vector(7 downto 0);
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signal lemden : std_ulogic;
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signal lpcio_vaden : std_logic_vector(31 downto 0);
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signal lpcio_cbeen : std_logic_vector(3 downto 0);
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signal lpcio_frameen : std_ulogic;
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signal lpcio_irdyen : std_ulogic;
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signal lpcio_trdyen : std_ulogic;
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signal lpcio_devselen: std_ulogic;
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signal lpcio_stopen : std_ulogic;
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signal lpcio_perren : std_ulogic;
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signal lpcio_paren : std_ulogic;
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signal lpcio_reqen : std_ulogic;
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signal lpcio_locken : std_ulogic;
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begin
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ltck <= clk when (test = '1') and ISASIC else tck;
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lspw_clk <= clk when (test = '1') and ISASIC else spw_clk;
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sclk : techbuf generic map (tech => fabtech) port map (lspw_clk, llspw_clk);
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lpciclk <= clk when (test = '1') and ISASIC else pciclk;
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pclk : techbuf generic map (tech => fabtech) port map (lpciclk, llpciclk);
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letx_clk <= clk when (test = '1') and ISASIC else etx_clk;
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etclk : techbuf generic map (tech => fabtech) port map (letx_clk, lletx_clk);
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lerx_clk <= clk when (test = '1') and ISASIC else erx_clk;
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erclk : techbuf generic map (tech => fabtech) port map (lerx_clk, llerx_clk);
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dataen <= (others => rxd1) when (test = '1') and ISASIC else ldataen;
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cben <= (others => rxd1) when (test = '1') and ISASIC else lcben;
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emden <= rxd1 when (test = '1') and ISASIC else lemden;
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pcio_vaden <= (others => rxd1) when (test = '1') and ISASIC else lpcio_vaden;
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pcio_cbeen <= (others => rxd1) when (test = '1') and ISASIC else lpcio_cbeen;
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pcio_frameen <= rxd1 when (test = '1') and ISASIC else lpcio_frameen;
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pcio_irdyen <= rxd1 when (test = '1') and ISASIC else lpcio_irdyen;
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pcio_trdyen <= rxd1 when (test = '1') and ISASIC else lpcio_trdyen;
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pcio_devselen <= rxd1 when (test = '1') and ISASIC else lpcio_devselen;
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pcio_stopen <= rxd1 when (test = '1') and ISASIC else lpcio_stopen;
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pcio_perren <= rxd1 when (test = '1') and ISASIC else lpcio_perren;
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pcio_paren <= rxd1 when (test = '1') and ISASIC else lpcio_paren;
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pcio_reqen <= rxd1 when (test = '1') and ISASIC else lpcio_reqen;
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pcio_locken <= rxd1 when (test = '1') and ISASIC else lpcio_locken;
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dsutx <= scanout when test = '1' else ldsutx;
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scanin <= dsurx when test = '1' else '0';
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scanen <= dsubre when test = '1' else '0';
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testrst <= dsuen when test = '1' else '0';
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leon3core0 : entity work.leon3core
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generic map ( fabtech, memtech, padtech, clktech, disas, dbguart,
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pclow, 1 - is_fpga(fabtech) )
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port map (
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resetn, clk, errorn,
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address, datain, dataout, ldataen, cbin, cbout, lcben,
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sdcsn, sdwen, sdrasn, sdcasn, sddqm,
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ldsutx, dsurx, dsuen, dsubre, dsuact,
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txd1, rxd1,
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ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn,
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wdogn, gpioin, gpioout, gpioen, writefb,
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emdi, emdo, lemden, lletx_clk, llerx_clk, erxd, erx_dv, erx_er,
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erx_col, erx_crs, etxd, etx_en, etx_er, emdc,
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llpciclk, pcii_rst, pcii_gnt, pcii_idsel, pcii_ad, pcii_cbe, pcii_frame,
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pcii_irdy, pcii_trdy, pcii_devsel, pcii_stop, pcii_perr, pcii_par, pcii_host,
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lpcio_vaden, lpcio_cbeen, lpcio_frameen, lpcio_irdyen, lpcio_trdyen,
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lpcio_devselen, lpcio_stopen, lpcio_perren, lpcio_paren, lpcio_reqen,
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lpcio_locken, pcio_req, pcio_ad, pcio_cbe, pcio_frame, pcio_irdy,
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pcio_trdy, pcio_devsel, pcio_stop, pcio_perr, pcio_par,
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pcii_arb_req, pcio_arb_gnt, can_tx, can_rx,
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llspw_clk, spw_rxd, spw_rxs, spw_txd, spw_txs, spw_ten,
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ltck, tms, tdi, tdo, trst,
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scanin, scanen, test, testrst, scanout, sdclk, pllref);
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end;
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