1 |
2 |
dimamali |
CONFIG STEPPING="2";
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2 |
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3 |
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NET "clk" PERIOD = 20.000 ;
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4 |
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OFFSET = out : 37.000 : AFTER clk ;
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5 |
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OFFSET = in : 8.000 : BEFORE clk ;
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6 |
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7 |
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NET "pci_clk" PERIOD = 30.000 ;
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8 |
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OFFSET = OUT : 11.000 : AFTER pci_clk ;
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9 |
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OFFSET = IN : 7.000 : BEFORE pci_clk ;
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10 |
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NET pci_arb_req(0) OFFSET = IN : 10.000 : BEFORE pci_clk ;
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11 |
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NET pci_arb_req(1) OFFSET = IN : 10.000 : BEFORE pci_clk ;
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12 |
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NET pci_arb_req(2) OFFSET = IN : 10.000 : BEFORE pci_clk ;
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13 |
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NET pci_arb_req(3) OFFSET = IN : 10.000 : BEFORE pci_clk ;
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14 |
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NET pci_arb_gnt(0) OFFSET = OUT : 12.000 : AFTER pci_clk ;
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15 |
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NET pci_arb_gnt(1) OFFSET = OUT : 12.000 : AFTER pci_clk ;
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16 |
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NET pci_arb_gnt(2) OFFSET = OUT : 12.000 : AFTER pci_clk ;
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NET pci_arb_gnt(3) OFFSET = OUT : 12.000 : AFTER pci_clk ;
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18 |
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19 |
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NET "erx_clk" PERIOD = 40.000 ;
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OFFSET = IN : 8.000 : BEFORE erx_clk ;
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22 |
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NET "etx_clk" PERIOD = 40.000 ;
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OFFSET = OUT : 15.000 : AFTER etx_clk ;
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OFFSET = IN : 8.000 : BEFORE etx_clk ;
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######## Enable these if you have spw configured #############################
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28 |
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#NET "core0/leon3core0/clkm" TNM_NET = "clkm";
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29 |
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#NET "core0/leon3core0/clk2x" TNM_NET = "clk2x";
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#TIMESPEC "TS_clkm_clk2x" = FROM "clkm" TO "clk2x" TIG;
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#TIMESPEC "TS_clk2x_clkm" = FROM "clk2x" TO "clkm" TIG;
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#NET "core0/leon3core0/spw.swloop.3.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
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34 |
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#NET "core0/leon3core0/spw.swloop.2.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
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35 |
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#NET "core0/leon3core0/spw.swloop.1.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
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#NET "core0/leon3core0/spw.swloop.0.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
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37 |
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#INST "core0/leon3core0/spw.swloop.3.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
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39 |
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#INST "core0/leon3core0/spw.swloop.3.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
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40 |
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#INST "core0/leon3core0/spw.swloop.2.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
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#INST "core0/leon3core0/spw.swloop.2.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
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#INST "core0/leon3core0/spw.swloop.1.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
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#INST "core0/leon3core0/spw.swloop.1.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
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44 |
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#INST "core0/leon3core0/spw.swloop.0.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
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#INST "core0/leon3core0/spw.swloop.0.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
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###############################################################################
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48 |
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49 |
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NET resetn TIG;
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NET pci_rst TIG;
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NET pci_host TIG;
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# Main Device Control Inputs
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NET "clk" LOC = "F18" | IOSTANDARD = LVCMOS33 ; # Main System Clock (Input)
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NET "resetn" LOC = "AF5" | IOSTANDARD = LVCMOS33 ; # System Reset (Input)
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56 |
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# Local Memory Signals
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NET "address(0)" LOC = "AB6" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(1)" LOC = "AB5" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(2)" LOC = "AC3" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(3)" LOC = "AC2" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(4)" LOC = "Y11" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(5)" LOC = "AA11" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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64 |
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NET "address(6)" LOC = "AD2" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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65 |
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NET "address(7)" LOC = "AD1" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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66 |
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NET "address(8)" LOC = "Y14" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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67 |
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NET "address(9)" LOC = "AA13" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(10)" LOC = "AC5" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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69 |
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NET "address(11)" LOC = "AC4" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(12)" LOC = "AF1" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(13)" LOC = "AE1" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(14)" LOC = "AA9" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(15)" LOC = "AA8" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(16)" LOC = "Y13" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(17)" LOC = "Y12" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(18)" LOC = "AE3" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(19)" LOC = "AE2" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(20)" LOC = "AD6" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(21)" LOC = "AD5" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(22)" LOC = "AC7" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(23)" LOC = "AB8" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(24)" LOC = "Y16" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(25)" LOC = "AA15" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(26)" LOC = "AE4" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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NET "address(27)" LOC = "AD4" | IOSTANDARD = LVCMOS33 ; # Local Memory Address Bus
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86 |
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NET "data(0)" LOC = "AJ22" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(1)" LOC = "AJ21" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(2)" LOC = "AC15" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(3)" LOC = "AB15" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(4)" LOC = "AG22" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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92 |
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NET "data(5)" LOC = "AH22" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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93 |
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NET "data(6)" LOC = "AL14" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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94 |
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NET "data(7)" LOC = "AK14" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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95 |
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NET "data(8)" LOC = "AG21" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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96 |
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NET "data(9)" LOC = "AF20" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(10)" LOC = "AF14" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(11)" LOC = "AG13" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(12)" LOC = "AE21" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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100 |
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NET "data(13)" LOC = "AF21" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(14)" LOC = "AP15" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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102 |
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NET "data(15)" LOC = "AN15" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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103 |
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NET "data(16)" LOC = "AA25" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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104 |
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NET "data(17)" LOC = "AA26" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(18)" LOC = "AE32" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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106 |
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NET "data(19)" LOC = "AD32" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(20)" LOC = "AC28" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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108 |
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NET "data(21)" LOC = "AB28" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(22)" LOC = "AD30" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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110 |
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NET "data(23)" LOC = "AD31" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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111 |
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NET "data(24)" LOC = "AG32" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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112 |
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NET "data(25)" LOC = "AG33" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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113 |
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NET "data(26)" LOC = "AF33" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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114 |
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NET "data(27)" LOC = "AF34" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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115 |
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NET "data(28)" LOC = "AE29" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(29)" LOC = "AD29" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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NET "data(30)" LOC = "AF31" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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118 |
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NET "data(31)" LOC = "AE31" | IOSTANDARD = LVCMOS33 ; # Local Memory Data Bus
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119 |
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120 |
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NET "cb(0)" LOC = "AA23" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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NET "cb(1)" LOC = "AA24" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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122 |
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NET "cb(2)" LOC = "AJ34" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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123 |
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NET "cb(3)" LOC = "AH34" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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124 |
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NET "cb(4)" LOC = "AD27" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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125 |
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NET "cb(5)" LOC = "AC27" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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126 |
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NET "cb(6)" LOC = "AB25" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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127 |
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NET "cb(7)" LOC = "AB26" | IOSTANDARD = LVCMOS33 ; # EDAC Check bit (bi-direct)
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128 |
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129 |
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# PROM and I/O bus Control Signals
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130 |
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NET "writen" LOC = "AG30" | IOSTANDARD = LVCMOS33 ; # PROM/ I/O Space Write Enable (Output)
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131 |
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NET "oen" LOC = "AG31" | IOSTANDARD = LVCMOS33 ; # PROM I/O Space Output Enable (Output)
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132 |
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NET "iosn" LOC = "AH32" | IOSTANDARD = LVCMOS33 ; # I/O Space Chip Select (Output)
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133 |
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134 |
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NET "romsn(0)" LOC = "AH33" | IOSTANDARD = LVCMOS33 ; # PROM Chip Select bank 0 (Output)
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135 |
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NET "romsn(1)" LOC = "AC25" | IOSTANDARD = LVCMOS33 ; # PROM Chip Select bank 1 (Output)
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136 |
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137 |
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# SRAM Control Signals
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138 |
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NET "rwen(0)" LOC = "AK31" | IOSTANDARD = LVCMOS33 ; # SRAM Write Enable Byte 0 (Output)
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139 |
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NET "rwen(1)" LOC = "AK32" | IOSTANDARD = LVCMOS33 ; # SRAM Write Enable Byte 1 (Output)
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140 |
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NET "rwen(2)" LOC = "AK33" | IOSTANDARD = LVCMOS33 ; # SRAM Write Enable Byte 2 (Output)
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141 |
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NET "rwen(3)" LOC = "AK34" | IOSTANDARD = LVCMOS33 ; # SRAM Write Enable Byte 3 (Output)
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142 |
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143 |
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NET "ramoen(0)" LOC = "AB22" | IOSTANDARD = LVCMOS33 ; # SRAM Output Enable bank 0
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144 |
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NET "ramoen(1)" LOC = "AB23" | IOSTANDARD = LVCMOS33 ; # SRAM Output Enable bank 1
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145 |
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NET "ramoen(2)" LOC = "AL33" | IOSTANDARD = LVCMOS33 ; # SRAM Output Enable bank 2
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146 |
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NET "ramoen(3)" LOC = "AL34" | IOSTANDARD = LVCMOS33 ; # SRAM Output Enable bank 3
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147 |
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NET "ramoen(4)" LOC = "AM31" | IOSTANDARD = LVCMOS33 ; # SRAM Output Enable bank 4
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148 |
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149 |
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NET "ramsn(0)" LOC = "AM32" | IOSTANDARD = LVCMOS33 ; # SRAM Chip Enable bank 0
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150 |
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NET "ramsn(1)" LOC = "AM33" | IOSTANDARD = LVCMOS33 ; # SRAM Chip Enable bank 1
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151 |
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NET "ramsn(2)" LOC = "AJ31" | IOSTANDARD = LVCMOS33 ; # SRAM Chip Enable bank 2
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152 |
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NET "ramsn(3)" LOC = "AJ32" | IOSTANDARD = LVCMOS33 ; # SRAM Chip Enable bank 3
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153 |
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NET "ramsn(4)" LOC = "AH30" | IOSTANDARD = LVCMOS33 ; # SRAM Chip Enable bank 4
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154 |
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155 |
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# SDRAM Interface Signals
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156 |
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NET "sdclk" LOC = "AL3" | IOSTANDARD = LVCMOS33 ; # SDRAM CLK (Output)
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157 |
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NET "pllref" LOC = "H17" | IOSTANDARD = LVCMOS33 ; # feedback clock for SDRAM (Input)
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158 |
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NET "sdrasn" LOC = "AB13" | IOSTANDARD = LVCMOS33 ; # SDRAM RAS (Output)
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159 |
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NET "sdcasn" LOC = "AB12" | IOSTANDARD = LVCMOS33 ; # SDRAM CAS (Output)
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160 |
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NET "sdwen" LOC = "AM2" | IOSTANDARD = LVCMOS33 ; # SDRAM WREN (Output)
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161 |
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162 |
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NET "sdcsn(0)" LOC = "AM1" | IOSTANDARD = LVCMOS33 ; # SDRAM Chip Select bank 0
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163 |
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NET "sdcsn(1)" LOC = "AG8" | IOSTANDARD = LVCMOS33 ; # SDRAM Chip Select bank 1
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164 |
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165 |
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NET "sdcke(0)" LOC = "AG7" | IOSTANDARD = LVCMOS33 ; # SDRAM Clock Enable bank 0
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166 |
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NET "sdcke(1)" LOC = "AM3" | IOSTANDARD = LVCMOS33 ; # SDRAM Clock Enable bank 1
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167 |
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168 |
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NET "sddqm(0)" LOC = "AC10" | IOSTANDARD = LVCMOS33 ; # SDRAM Data Mask (Output)
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169 |
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NET "sddqm(1)" LOC = "AB10" | IOSTANDARD = LVCMOS33 ; # SDRAM Data Mask (Output)
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170 |
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NET "sddqm(2)" LOC = "AK3" | IOSTANDARD = LVCMOS33 ; # SDRAM Data Mask (Output)
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171 |
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NET "sddqm(3)" LOC = "AK2" | IOSTANDARD = LVCMOS33 ; # SDRAM Data Mask (Output)
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172 |
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173 |
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# Memory Bus Status Signals
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174 |
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NET "read" LOC = "AJ2" | IOSTANDARD = LVCMOS33 ; # Read cycle indicator ? Function
|
175 |
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NET "bexcn" LOC = "AC9" | IOSTANDARD = LVCMOS33 ; # Bus Error Exception (Input)
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176 |
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NET "brdyn" LOC = "AG3" | IOSTANDARD = LVCMOS33 ; # Bus Ready (Input)
|
177 |
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178 |
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# System Status Signals
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179 |
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NET "errorn" LOC = "AG5" | IOSTANDARD = LVCMOS33 ; # Processor Error (Output)
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180 |
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NET "wdogn" LOC = "AD7" | IOSTANDARD = LVCMOS33 ; # Timer 4 Watchdog timeout (output)
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181 |
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182 |
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183 |
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# CAN BUS 1
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184 |
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NET "can_rxd(0)" LOC = "K34" | IOSTANDARD = LVCMOS33 ; # CAN bus Receive data (Input)
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185 |
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NET "can_txd(0)" LOC = "J34" | IOSTANDARD = LVCMOS33 ; # CAN bus Transmit data (Output)
|
186 |
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187 |
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# CAN BUS 2
|
188 |
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NET "can_rxd(1)" LOC = "N30" | IOSTANDARD = LVCMOS33 ; # CAN bus Receive data (Input)
|
189 |
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NET "can_txd(1)" LOC = "N29" | IOSTANDARD = LVCMOS33 ; # CAN bus Transmit data (Output)
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190 |
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191 |
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192 |
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# DSU Debug Control Signals
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193 |
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NET "dsuact" LOC = "R24" | IOSTANDARD = LVCMOS33 ; # DSU Active (Output)
|
194 |
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NET "dsubre" LOC = "H32" | IOSTANDARD = LVCMOS33 ; # DSU Break (Input)
|
195 |
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NET "dsuen" LOC = "J32" | IOSTANDARD = LVCMOS33 ; # DSU Enable (Input)
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196 |
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197 |
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# DSU Debug UART
|
198 |
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NET "dsurx" LOC = "M32" | IOSTANDARD = LVCMOS33 ; # DSU Receive UART (Input)
|
199 |
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NET "dsutx" LOC = "M33" | IOSTANDARD = LVCMOS33 ; # DSU Transmit UART (Transmit)
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200 |
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201 |
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202 |
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# Ethernet Signals
|
203 |
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NET "emdc" LOC = "N23" | IOSTANDARD = LVCMOS33 ; # (EMCLK) Ethernet PHY Clock (Output)
|
204 |
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205 |
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NET "emdio" LOC = "N22" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface DIO (bi-direct)
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206 |
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207 |
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NET "erx_clk" LOC = "AK18" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receive Clock (Input)
|
208 |
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NET "erx_col" LOC = "H29" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Collision Detect (Input)
|
209 |
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NET "erx_crs" LOC = "L30" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Carrier Sense (Input)
|
210 |
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NET "erx_dv" LOC = "H34" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Data Valid (Input)
|
211 |
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NET "erx_er" LOC = "J31" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receiption Error (Input)
|
212 |
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213 |
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NET "erxd(0)" LOC = "J27" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receive Data (Input)
|
214 |
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NET "erxd(1)" LOC = "K27" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receive Data (Input)
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215 |
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NET "erxd(2)" LOC = "M25" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receive Data (Input)
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216 |
|
|
NET "erxd(3)" LOC = "M26" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Receive Data (Input)
|
217 |
|
|
|
218 |
|
|
NET "etx_clk" LOC = "AH19" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Clock (Input)
|
219 |
|
|
NET "etx_en" LOC = "C33" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Enable (Output)
|
220 |
|
|
NET "etx_er" LOC = "R22" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Error (Output)
|
221 |
|
|
|
222 |
|
|
NET "etxd(0)" LOC = "H27" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Data (Output)
|
223 |
|
|
NET "etxd(1)" LOC = "H28" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Data (Output)
|
224 |
|
|
NET "etxd(2)" LOC = "C32" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Data (Output)
|
225 |
|
|
NET "etxd(3)" LOC = "D32" | IOSTANDARD = LVCMOS33 ; # Ethernet Media Interface Transmit Data (Output)
|
226 |
|
|
|
227 |
|
|
NET "gpio(0)" LOC = "G30" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
228 |
|
|
NET "gpio(1)" LOC = "G31" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
229 |
|
|
NET "gpio(2)" LOC = "J29" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
230 |
|
|
NET "gpio(3)" LOC = "J30" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
231 |
|
|
NET "gpio(4)" LOC = "E32" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
232 |
|
|
NET "gpio(5)" LOC = "E33" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
233 |
|
|
NET "gpio(6)" LOC = "N25" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
234 |
|
|
NET "gpio(7)" LOC = "P26" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
235 |
|
|
NET "gpio(8)" LOC = "P22" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
236 |
|
|
NET "gpio(9)" LOC = "R21" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
237 |
|
|
NET "gpio(10)" LOC = "F33" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
238 |
|
|
NET "gpio(11)" LOC = "F34" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
239 |
|
|
NET "gpio(12)" LOC = "K28" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
240 |
|
|
NET "gpio(13)" LOC = "K29" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
241 |
|
|
NET "gpio(14)" LOC = "G32" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
242 |
|
|
NET "gpio(15)" LOC = "G33" | IOSTANDARD = LVCMOS33 ; # General Purpose I/O
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
# PCI Signals
|
246 |
|
|
NET "pci_ad(0)" LOC = "N4" | BYPASS ; # PCI Address/Data Bus
|
247 |
|
|
NET "pci_ad(1)" LOC = "P4" | BYPASS ; # PCI Address/Data Bus
|
248 |
|
|
NET "pci_ad(2)" LOC = "N3" | BYPASS ; # PCI Address/Data Bus
|
249 |
|
|
NET "pci_ad(3)" LOC = "N2" | BYPASS ; # PCI Address/Data Bus
|
250 |
|
|
NET "pci_ad(4)" LOC = "R8" | BYPASS ; # PCI Address/Data Bus
|
251 |
|
|
NET "pci_ad(5)" LOC = "T8" | BYPASS ; # PCI Address/Data Bus
|
252 |
|
|
NET "pci_ad(6)" LOC = "R7" | BYPASS ; # PCI Address/Data Bus
|
253 |
|
|
NET "pci_ad(7)" LOC = "R6" | BYPASS ; # PCI Address/Data Bus
|
254 |
|
|
NET "pci_ad(8)" LOC = "P2" | BYPASS ; # PCI Address/Data Bus
|
255 |
|
|
NET "pci_ad(9)" LOC = "P1" | BYPASS ; # PCI Address/Data Bus
|
256 |
|
|
NET "pci_ad(10)" LOC = "R4" | BYPASS ; # PCI Address/Data Bus
|
257 |
|
|
NET "pci_ad(11)" LOC = "T4" | BYPASS ; # PCI Address/Data Bus
|
258 |
|
|
NET "pci_ad(12)" LOC = "R3" | BYPASS ; # PCI Address/Data Bus
|
259 |
|
|
NET "pci_ad(13)" LOC = "R2" | BYPASS ; # PCI Address/Data Bus
|
260 |
|
|
NET "pci_ad(14)" LOC = "R1" | BYPASS ; # PCI Address/Data Bus
|
261 |
|
|
NET "pci_ad(15)" LOC = "T1" | BYPASS ; # PCI Address/Data Bus
|
262 |
|
|
NET "pci_ad(16)" LOC = "T6" | BYPASS ; # PCI Address/Data Bus
|
263 |
|
|
NET "pci_ad(17)" LOC = "T5" | BYPASS ; # PCI Address/Data Bus
|
264 |
|
|
NET "pci_ad(18)" LOC = "T3" | BYPASS ; # PCI Address/Data Bus
|
265 |
|
|
NET "pci_ad(19)" LOC = "U3" | BYPASS ; # PCI Address/Data Bus
|
266 |
|
|
NET "pci_ad(20)" LOC = "U8" | BYPASS ; # PCI Address/Data Bus
|
267 |
|
|
NET "pci_ad(21)" LOC = "U7" | BYPASS ; # PCI Address/Data Bus
|
268 |
|
|
NET "pci_ad(22)" LOC = "U2" | BYPASS ; # PCI Address/Data Bus
|
269 |
|
|
NET "pci_ad(23)" LOC = "U1" | BYPASS ; # PCI Address/Data Bus
|
270 |
|
|
NET "pci_ad(24)" LOC = "U12" | BYPASS ; # PCI Address/Data Bus
|
271 |
|
|
NET "pci_ad(25)" LOC = "U11" | BYPASS ; # PCI Address/Data Bus
|
272 |
|
|
NET "pci_ad(26)" LOC = "U10" | BYPASS ; # PCI Address/Data Bus
|
273 |
|
|
NET "pci_ad(27)" LOC = "V10" | BYPASS ; # PCI Address/Data Bus
|
274 |
|
|
NET "pci_ad(28)" LOC = "U6" | BYPASS ; # PCI Address/Data Bus
|
275 |
|
|
NET "pci_ad(29)" LOC = "U5" | BYPASS ; # PCI Address/Data Bus
|
276 |
|
|
NET "pci_ad(30)" LOC = "V3" | BYPASS ; # PCI Address/Data Bus
|
277 |
|
|
NET "pci_ad(31)" LOC = "V2" | BYPASS ; # PCI Address/Data Bus
|
278 |
|
|
|
279 |
|
|
|
280 |
|
|
NET "pci_clk" LOC = "AD16" ; # PCI Bus Clock (Input)
|
281 |
|
|
|
282 |
|
|
NET "pci_cbe(0)" LOC = "V9" | BYPASS ; # PCI Bus Command Byte Enable
|
283 |
|
|
NET "pci_cbe(1)" LOC = "V8" | BYPASS ; # PCI Bus Command Byte Enable
|
284 |
|
|
NET "pci_cbe(2)" LOC = "V5" | BYPASS ; # PCI Bus Command Byte Enable
|
285 |
|
|
NET "pci_cbe(3)" LOC = "V4" | BYPASS ; # PCI Bus Command Byte Enable
|
286 |
|
|
|
287 |
|
|
NET "pci_devsel" LOC = "AA5" | BYPASS | PULLUP ; # PCI Bus Device Select (bi-direct)
|
288 |
|
|
NET "pci_frame" LOC = "AA4" | BYPASS | PULLUP ; # PCI Bus Frame (bi-direct)
|
289 |
|
|
NET "pci_gnt" LOC = "AA1" ; # PCI Bus Grant (Input)
|
290 |
|
|
NET "pci_host" LOC = "Y1" | BYPASS | PULLUP ; # PCI Bus Host Enable (Input)
|
291 |
|
|
NET "pci_idsel" LOC = "AB3" | PULLUP ; # PCI
|
292 |
|
|
NET "pci_irdy" LOC = "AA3" | BYPASS | PULLUP ; # PCI Bus Initiator Ready (bi-direct)
|
293 |
|
|
NET "pci_par" LOC = "AB2" | BYPASS ; # PCI Bus Parity (bi-direct)
|
294 |
|
|
#NET pci_serr ; # PCI bus System Error, had to comment out due to logic trimming (found as not implemented in grlib doc)
|
295 |
|
|
#NET pci_lock ; # PCI bus System Lockn, had to comment out due to logic trimming
|
296 |
|
|
NET "pci_perr" LOC = "AB1" | BYPASS | PULLUP ; # PCI Bus Parity Error (Input)
|
297 |
|
|
NET "pci_req" LOC = "AA6" ; # PCI Bus Request (Output)
|
298 |
|
|
NET "pci_rst" LOC = "Y6" | PULLUP ; # PCI Bus Reset (Input)
|
299 |
|
|
NET "pci_stop" LOC = "Y8" | BYPASS | PULLUP ; # PCI Bus Stop (bi-direct)
|
300 |
|
|
NET "pci_trdy" LOC = "Y7" | BYPASS | PULLUP ; # PCI Bus Target Ready (bi-direct)
|
301 |
|
|
NET "pci_arb_gnt(0)" LOC = "E29" | FAST ; # PCI Bus arbiter grant 0
|
302 |
|
|
NET "pci_arb_gnt(1)" LOC = "L26" | FAST ; # PCI Bus arbiter grant 1
|
303 |
|
|
NET "pci_arb_gnt(2)" LOC = "B33" | FAST ; # PCI Bus arbiter grant 2
|
304 |
|
|
NET "pci_arb_gnt(3)" LOC = "F31" | FAST ; # PCI Bus arbiter grant 3
|
305 |
|
|
NET "pci_arb_req(0)" LOC = "D29" | PULLUP ; # PCI Bus arbiter request 0
|
306 |
|
|
NET "pci_arb_req(1)" LOC = "L25" | PULLUP ; # PCI Bus arbiter request 1
|
307 |
|
|
NET "pci_arb_req(2)" LOC = "B32" | PULLUP ; # PCI Bus arbiter request 2
|
308 |
|
|
NET "pci_arb_req(3)" LOC = "E31" | PULLUP ; # PCI Bus arbiter request 3
|
309 |
|
|
|
310 |
|
|
|
311 |
|
|
# General Purpose UART
|
312 |
|
|
NET "rxd1" LOC = "L33" | IOSTANDARD = LVCMOS33 ; # UART Receive data (Input)
|
313 |
|
|
NET "txd1" LOC = "L34" | IOSTANDARD = LVCMOS33 ; # UART Transmit data (Output)
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
# SpaceWire Interface
|
317 |
|
|
#NET "spw_clk" LOC = "C19" ; # SpaceWire Transmit Clock (Input)p
|
318 |
|
|
NET "spw_clkp" LOC = "C19" ; # SpaceWire Transmit Clock (Input)p
|
319 |
|
|
NET "spw_clkn" LOC = "C18" ; # SpaceWire Transmit Clock (Input)n
|
320 |
|
|
|
321 |
|
|
# SpaceWire Port 1
|
322 |
|
|
NET "spw_rxdp(0)" LOC = "T23" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS P
|
323 |
|
|
NET "spw_rxdn(0)" LOC = "U23" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS N
|
324 |
|
|
NET "spw_rxsp(0)" LOC = "R26" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS P
|
325 |
|
|
NET "spw_rxsn(0)" LOC = "T26" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS N
|
326 |
|
|
NET "spw_txdp(0)" LOC = "T24" ; # SpaceWire Transmit Data LVDS P
|
327 |
|
|
NET "spw_txdn(0)" LOC = "T25" ; # SpaceWire Transmit Data LVDS N
|
328 |
|
|
NET "spw_txsp(0)" LOC = "R27" ; # SpaceWire Transmit Strobe LVDS P
|
329 |
|
|
NET "spw_txsn(0)" LOC = "R28" ; # SpaceWire Transmit Strobe LVDS N
|
330 |
|
|
|
331 |
|
|
# SpaceWire Port 2
|
332 |
|
|
NET "spw_rxdp(1)" LOC = "T29" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS P
|
333 |
|
|
NET "spw_rxdn(1)" LOC = "T30" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS N
|
334 |
|
|
NET "spw_rxsp(1)" LOC = "T33" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS P
|
335 |
|
|
NET "spw_rxsn(1)" LOC = "T34" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS N
|
336 |
|
|
NET "spw_txdp(1)" LOC = "U26" ; # SpaceWire Transmit Data LVDS P
|
337 |
|
|
NET "spw_txdn(1)" LOC = "U27" ; # SpaceWire Transmit Data LVDS N
|
338 |
|
|
NET "spw_txsp(1)" LOC = "U30" ; # SpaceWire Transmit Strobe LVDS P
|
339 |
|
|
NET "spw_txsn(1)" LOC = "U31" ; # SpaceWire Transmit Strobe LVDS N
|
340 |
|
|
|
341 |
|
|
# SpaceWire Port 3
|
342 |
|
|
NET "spw_rxdp(2)" LOC = "V33" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS P
|
343 |
|
|
NET "spw_rxdn(2)" LOC = "V34" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS N
|
344 |
|
|
NET "spw_rxsp(2)" LOC = "U32" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS P
|
345 |
|
|
NET "spw_rxsn(2)" LOC = "U33" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS N
|
346 |
|
|
NET "spw_txdp(2)" LOC = "V25" ; # SpaceWire Transmit Data LVDS P
|
347 |
|
|
NET "spw_txdn(2)" LOC = "U25" ; # SpaceWire Transmit Data LVDS N
|
348 |
|
|
NET "spw_txsp(2)" LOC = "V28" ; # SpaceWire Transmit Strobe LVDS P
|
349 |
|
|
NET "spw_txsn(2)" LOC = "V29" ; # SpaceWire Transmit Strobe LVDS N
|
350 |
|
|
|
351 |
|
|
# SpaceWire Port 4
|
352 |
|
|
NET "spw_rxdp(3)" LOC = "AB32" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS P
|
353 |
|
|
NET "spw_rxdn(3)" LOC = "AB33" | IOBDELAY="NONE" ; # SpaceWire Receive Data LVDS N
|
354 |
|
|
NET "spw_rxsp(3)" LOC = "AA33" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS P
|
355 |
|
|
NET "spw_rxsn(3)" LOC = "AA34" | IOBDELAY="NONE" ; # SpaceWire Receive Strobe LVDS N
|
356 |
|
|
NET "spw_txdp(3)" LOC = "AB31" ; # SpaceWire Transmit Data LVDS P
|
357 |
|
|
NET "spw_txdn(3)" LOC = "AA31" ; # SpaceWire Transmit Data LVDS N
|
358 |
|
|
NET "spw_txsp(3)" LOC = "Y27" ; # SpaceWire Transmit Strobe LVDS P
|
359 |
|
|
NET "spw_txsn(3)" LOC = "Y28" ; # SpaceWire Transmit Strobe LVDS N
|