OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [cypress/] [ssram/] [cy7c1354b.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
-----------------------------------------------------------------------------------------
2
--
3
--     File Name:  CY7C1354B.VHD
4
--       Version:  2.0
5
--          Date:  Nov 22nd, 2004
6
--         Model:  BUS Functional
7
--     
8
-- 
9
--        Author:  RKF 
10
--       Company:  Cypress Semiconductor
11
--         Model:  CY7C1354B (256k x 36)
12
--          Mode:  Pipelined
13
--
14
--   Description:  NoBL SRAM VHDL Model
15
--
16
--    Limitation:  None
17
--
18
--          Note:  - BSDL Model available separately
19
--                 - Set simulator resolution to "ps" timescale
20
--
21
--    Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
22
--                 WHATSOEVER AND CYPRESS SPECIFICALLY DISCLAIMS ANY
23
--                 IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
24
--                 A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
25
--
26
--                 Copyright (c) 2004 Cypress Semiconductor 
27
--                 All rights reserved
28
--
29
--     Trademarks: NoBL and No Bus Latency are trademarks of Cypress Semiconductor
30
--
31
--  Rev  Author          Date        Changes
32
--  ---  --------       -------     ----------  
33
--  2.0  RKF            11/22/2004  - Second Release
34
--                                  - Fully Tested with New Test Bench and Test Vectors 
35
-----------------------------------------------------------------------------------------
36
 
37
LIBRARY ieee,work,grlib,gaisler;
38
        USE ieee.std_logic_1164.all;
39
--      USE ieee.std_logic_unsigned.all;
40
--      Use IEEE.Std_Logic_Arith.all;
41
--      Use work.all;   
42
        USE work.package_utility.all;
43
        use grlib.stdlib.all;
44
        use ieee.std_logic_1164.all;
45
        use std.textio.all;
46
        use gaisler.sim.all;
47
 
48
 
49
ENTITY cy7c1354 IS
50
 
51
    GENERIC (
52
 
53
        fname   : string := "prom.srec"; -- File to read from
54
 
55
        -- Constant parameters
56
        addr_bits : INTEGER := 18;
57
        data_bits : INTEGER := 36;
58
 
59
        -- Timing parameters for -5 (225 Mhz)
60
        tCYC    : TIME    := 4.4 ns;
61
        tCH     : TIME    :=  1.8 ns;
62
        tCL     : TIME    :=  1.8 ns;
63
        tCO     : TIME    :=  2.8 ns;
64
        tAS     : TIME    :=  1.4 ns;
65
        tCENS   : TIME    :=  1.4 ns;
66
        tWES    : TIME    :=  1.4 ns;
67
        tDS     : TIME    :=  1.4 ns;
68
        tAH     : TIME    :=  0.4 ns;
69
        tCENH   : TIME    :=  0.4 ns;
70
        tWEH    : TIME    :=  0.4 ns;
71
        tDH     : TIME    :=  0.4 ns
72
 
73
 
74
 
75
        -- Timing parameters for -5 (200 Mhz)
76
        --tCYC  : TIME    := 5.0 ns;
77
        --tCH   : TIME    :=  2.0 ns;
78
        --tCL   : TIME    :=  2.0 ns;
79
        --tCO   : TIME    :=  3.2 ns;
80
        --tAS   : TIME    :=  1.5 ns;
81
        --tCENS : TIME    :=  1.5 ns;
82
        --tWES  : TIME    :=  1.5 ns;
83
        --tDS   : TIME    :=  1.5 ns;
84
        --tAH   : TIME    :=  0.5 ns;
85
        --tCENH : TIME    :=  0.5 ns;
86
        --tWEH  : TIME    :=  0.5 ns;
87
        --tDH   : TIME    :=  0.5 ns
88
 
89
 
90
        -- Timing parameters for -5 (166 Mhz)
91
        --tCYC  : TIME    := 6.0 ns;
92
        --tCH   : TIME    :=  2.4 ns;
93
        --tCL   : TIME    :=  2.4 ns;
94
        --tCO   : TIME    :=  3.5 ns;
95
        --tAS   : TIME    :=  1.5 ns;
96
        --tCENS : TIME    :=  1.5 ns;
97
        --tWES  : TIME    :=  1.5 ns;
98
        --tDS   : TIME    :=  1.5 ns;
99
        --tAH   : TIME    :=  0.5 ns;
100
        --tCENH : TIME    :=  0.5 ns;
101
        --tWEH  : TIME    :=  0.5 ns;
102
        --tDH   : TIME    :=  0.5 ns
103
 
104
 
105
 
106
         );
107
 
108
    -- Port Declarations
109
    PORT (
110
        Dq      : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0);     -- Data I/O
111
        Addr    : IN    STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0);     -- Address
112
        Mode    : IN    STD_LOGIC       := '1';                         -- Burst Mode
113
        Clk     : IN    STD_LOGIC;                                   -- Clk
114
        CEN_n   : IN    STD_LOGIC;                                   -- CEN#
115
        AdvLd_n : IN    STD_LOGIC;                                   -- Adv/Ld#
116
        Bwa_n   : IN    STD_LOGIC;                                   -- Bwa#
117
        Bwb_n   : IN    STD_LOGIC;                                   -- BWb#
118
        Bwc_n   : IN    STD_LOGIC;                                   -- Bwc#
119
        Bwd_n   : IN    STD_LOGIC;                                   -- BWd#
120
        Rw_n    : IN    STD_LOGIC;                                   -- RW#
121
        Oe_n    : IN    STD_LOGIC;                                   -- OE#
122
        Ce1_n   : IN    STD_LOGIC;                                   -- CE1#
123
        Ce2     : IN    STD_LOGIC;                                   -- CE2
124
        Ce3_n   : IN    STD_LOGIC;                                   -- CE3#
125
        Zz      : IN    STD_LOGIC                                    -- Snooze Mode
126
    );
127
END cy7c1354;
128
 
129
ARCHITECTURE behave OF cy7c1354 IS
130
    SIGNAL ce : STD_LOGIC := '0';
131
    SIGNAL doe : STD_LOGIC := '0';
132
    SIGNAL dout : STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
133
    SIGNAL Addr_read_sig : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => 'Z');
134
 
135
BEGIN
136
 
137
 
138
    ce <= NOT(Ce1_n) AND NOT(Ce3_n) AND Ce2;
139
 
140
    doe <= NOT(Oe_n) AND NOT(Zz);
141
 
142
    -- Output Buffers
143
    WITH doe SELECT
144
        Dq <= TRANSPORT dout            AFTER (tCO) WHEN '1',
145
                        (OTHERS => 'Z') AFTER (tCO) WHEN OTHERS;
146
 
147
 
148
 
149
    -- Check for Clock Timing Violation
150
--    clk_check : PROCESS
151
--        VARIABLE clk_high, clk_low : TIME := 0 ns;
152
--    BEGIN
153
--        WAIT ON Clk;
154
--            IF Clk = '1' AND NOW >= tCYC THEN
155
--                ASSERT (NOW - clk_low >= tCH)
156
--                    REPORT "Clk width low - tCH violation"
157
--                    SEVERITY ERROR;
158
--                ASSERT (NOW - clk_high >= tCYC)
159
--                    REPORT "Clk period high - tCYC violation"
160
--                    SEVERITY ERROR;
161
--                clk_high := NOW;
162
--            ELSIF Clk = '0' AND NOW /= 0 ns THEN
163
--                ASSERT (NOW - clk_high >= tCL)
164
--                    REPORT "Clk width high - tCL violation"
165
--                    SEVERITY ERROR;
166
--                ASSERT (NOW - clk_low >= tCYC)
167
--                    REPORT "Clk period low - tCYC violation"
168
--                    SEVERITY ERROR;
169
--                clk_low := NOW;
170
--            END IF;
171
--    END PROCESS;
172
 
173
    -- Check for Setup Timing Violation
174
    setup_check : PROCESS
175
    BEGIN
176
        WAIT ON Clk;
177
        IF Clk = '1' THEN
178
            ASSERT (Addr'LAST_EVENT >= tAS)
179
                REPORT "Addr - tAS violation"
180
                SEVERITY ERROR;
181
            ASSERT (CEN_n'LAST_EVENT >= tCENS)
182
                REPORT "CKE# - tCENS violation"
183
                SEVERITY ERROR;
184
            ASSERT (Ce1_n'LAST_EVENT >= tWES)
185
                REPORT "CE1# - tWES violation"
186
                SEVERITY ERROR;
187
            ASSERT (Ce2'LAST_EVENT >= tWES)
188
                REPORT "CE2 - tWES violation"
189
                SEVERITY ERROR;
190
            ASSERT (Ce3_n'LAST_EVENT >= tWES)
191
                REPORT "CE3# - tWES violation"
192
                SEVERITY ERROR;
193
            ASSERT (AdvLd_n'LAST_EVENT >= tWES)
194
                REPORT "ADV/LD# - tWES violation"
195
                SEVERITY ERROR;
196
            ASSERT (Rw_n'LAST_EVENT >= tWES)
197
                REPORT "RW# - tWES violation"
198
                SEVERITY ERROR;
199
            ASSERT (Bwa_n'LAST_EVENT >= tWES)
200
                REPORT "BWa# - tWES violation"
201
                SEVERITY ERROR;
202
            ASSERT (Bwb_n'LAST_EVENT >= tWES)
203
                REPORT "BWb# - tWES violation"
204
                SEVERITY ERROR;
205
            ASSERT (Bwc_n'LAST_EVENT >= tWES)
206
                REPORT "BWc# - tWES violation"
207
                SEVERITY ERROR;
208
            ASSERT (Bwd_n'LAST_EVENT >= tWES)
209
                REPORT "BWd# - tWES violation"
210
                SEVERITY ERROR;
211
            --ASSERT (Dq'LAST_EVENT >= tDS)
212
            --    REPORT "Dq - tDS violation"
213
            --    SEVERITY ERROR;
214
        END IF;
215
    END PROCESS;
216
 
217
    -- Check for Hold Timing Violation
218
    hold_check : PROCESS
219
    BEGIN
220
        WAIT ON Clk'DELAYED(tAH), Clk'DELAYED(tCENH), Clk'DELAYED(tWEH), Clk'DELAYED(tDH);
221
        IF Clk'DELAYED(tAH) = '1' THEN
222
            ASSERT (Addr'LAST_EVENT > tAH)
223
                REPORT "Addr - tAH violation"
224
                SEVERITY ERROR;
225
        END IF;
226
        IF Clk'DELAYED(tCENH) = '1' THEN
227
            ASSERT (CEN_n'LAST_EVENT > tCENH)
228
                REPORT "CKE# - tCENH violation"
229
                SEVERITY ERROR;
230
        END IF;
231
        --IF Clk'DELAYED(tDH) = '1' THEN
232
        --    ASSERT (Dq'LAST_EVENT > tDH)
233
        --        REPORT "Dq - tDH violation"
234
        --        SEVERITY ERROR;
235
        --END IF;
236
        IF Clk'DELAYED(tWEH) = '1' THEN
237
            ASSERT (Ce1_n'LAST_EVENT > tWEH)
238
                REPORT "CE1# - tWEH violation"
239
                SEVERITY ERROR;
240
            ASSERT (Ce2'LAST_EVENT > tWEH)
241
                REPORT "CE2 - tWEH violation"
242
                SEVERITY ERROR;
243
            ASSERT (Ce3_n'LAST_EVENT > tWEH)
244
                REPORT "CE3 - tWEH violation"
245
                SEVERITY ERROR;
246
            ASSERT (AdvLd_n'LAST_EVENT > tWEH)
247
                REPORT "ADV/LD# - tWEH violation"
248
                SEVERITY ERROR;
249
            ASSERT (Rw_n'LAST_EVENT > tWEH)
250
                        REPORT "RW# - tWEH violation"
251
                SEVERITY ERROR;
252
            ASSERT (Bwa_n'LAST_EVENT > tWEH)
253
                REPORT "BWa# - tWEH violation"
254
                SEVERITY ERROR;
255
            ASSERT (Bwb_n'LAST_EVENT > tWEH)
256
                REPORT "BWb# - tWEH violation"
257
                SEVERITY ERROR;
258
            ASSERT (Bwc_n'LAST_EVENT > tWEH)
259
                REPORT "BWc# - tWEH violation"
260
                SEVERITY ERROR;
261
            ASSERT (Bwd_n'LAST_EVENT > tWEH)
262
                REPORT "BWd# - tWEH violation"
263
                SEVERITY ERROR;
264
        END IF;
265
 
266
    END PROCESS;
267
 
268
   -- Main Program
269
    main : PROCESS
270
 
271
--    TYPE memory_array IS ARRAY ((2**addr_bits) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR ((data_bits / 4) - 1 DOWNTO 0);
272
        TYPE memory_array IS ARRAY (0 TO (2**addr_bits) - 1) OF STD_LOGIC_VECTOR ((data_bits / 4) - 1 DOWNTO 0);
273
 
274
        VARIABLE Addr_in        : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
275
        VARIABLE first_Addr     : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
276
        VARIABLE Addr_read      : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
277
        VARIABLE Addr_write     : STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0) := (OTHERS => '0');
278
        VARIABLE bAddr0, bAddr1 : STD_LOGIC := '0';
279
        VARIABLE bank0          : memory_array;
280
        VARIABLE bank1          : memory_array;
281
        VARIABLE bank2          : memory_array;
282
        VARIABLE bank3          : memory_array;
283
 
284
        VARIABLE ce_in          : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
285
        VARIABLE rw_in          : STD_LOGIC_VECTOR (2 DOWNTO 0) := "111";
286
        VARIABLE bwa_in         : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
287
        VARIABLE bwb_in         : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
288
        VARIABLE bwc_in         : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
289
        VARIABLE bwd_in         : STD_LOGIC_VECTOR (2 DOWNTO 0) := "000";
290
        VARIABLE bcnt           : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
291
 
292
        variable FIRST          : boolean := true;
293
        file TCF : text open read_mode is fname;
294
        variable rectype : std_logic_vector(3 downto 0);
295
        variable recaddr : std_logic_vector(31 downto 0);
296
        variable reclen  : std_logic_vector(7 downto 0);
297
        variable recdata : std_logic_vector(0 to 16*8-1);
298
        variable CH : character;
299
        variable ai : integer := 0;
300
        variable L1 : line;
301
 
302
    BEGIN
303
      if FIRST then
304
 
305
      L1:= new string'("");
306
      while not endfile(TCF) loop
307
        readline(TCF,L1);
308
        if (L1'length /= 0) then
309
          while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
310
            std.textio.read(L1,CH);
311
          end loop;
312
 
313
          if L1'length > 0 then
314
            std.textio.read(L1, ch);
315
            if (ch = 'S') or (ch = 's') then
316
              hexread(L1, rectype);
317
              hexread(L1, reclen);
318
              recaddr := (others => '0');
319
              case rectype is
320
                when "0001" =>
321
                  hexread(L1, recaddr(15 downto 0));
322
                when "0010" =>
323
                  hexread(L1, recaddr(23 downto 0));
324
                when "0011" =>
325
                  hexread(L1, recaddr);
326
                  recaddr(31 downto 24) := (others => '0');
327
                when others => next;
328
              end case;
329
              hexread(L1, recdata);
330
              ai := conv_integer(recaddr)/4;
331
              for i in 0 to 3 loop
332
                bank3 (ai+i) := '0' & recdata((i*32) to (i*32+7));
333
                bank2 (ai+i) := '0' & recdata((i*32+8) to (i*32+8+7));
334
                bank1 (ai+i) := '0' & recdata((i*32+16) to (i*32+16+7));
335
                bank0 (ai+i) := '0' & recdata((i*32+24) to (i*32+24+7));
336
              end loop;
337
            end if;
338
          end if;
339
        end if;
340
      end loop;
341
 
342
      FIRST := false;
343
    end if;
344
 
345
        WAIT ON Clk;
346
        IF Clk'EVENT AND Clk = '1' THEN
347
            IF CEN_n = '0' AND Zz = '0' THEN
348
                -- Write Address Register
349
                Addr_write := Addr_read;
350
 
351
                -- Read Address Register
352
                Addr_read := Addr_in ((addr_bits - 1) DOWNTO 2) & bAddr1 & bAddr0;
353
 
354
                -- Address Register
355
                IF AdvLd_n = '0' and ce = '1' THEN
356
                  Addr_in := Addr;
357
                  first_Addr := Addr(1 DOWNTO 0);
358
                  bcnt := Addr(1 DOWNTO 0);
359
              END IF;
360
 
361
 
362
                -- Burst Logic
363
              IF Mode = '0' AND AdvLd_n = '1' THEN
364
                  bcnt := bcnt + 1;
365
              ELSIF Mode = '1' AND AdvLd_n = '1' THEN
366
                        IF (CONV_INTEGER1 (first_Addr) REM 2 = 0) THEN
367
                                bcnt := bcnt + 1;
368
                        ELSIF (CONV_INTEGER1 (first_Addr) REM 2 = 1) THEN
369
                                bcnt := bcnt - 1;
370
                        END IF;
371
              END IF;
372
 
373
 
374
                  bAddr1 := bcnt (1);
375
                  bAddr0 := bcnt (0);
376
 
377
                -- Read Logic
378
                ce_in (0) := ce_in (1);
379
 
380
                IF AdvLd_n = '0' THEN
381
                    ce_in (1) := ce;
382
                END IF;
383
 
384
                rw_in (0) := rw_in (1);
385
                rw_in (1) := rw_in (2);
386
 
387
                IF AdvLd_n = '0' THEN
388
                    rw_in (2) := NOT(ce AND NOT(Rw_n));
389
                END IF;
390
 
391
                -- Write Registry and Data Coherency Control Logic
392
                bwa_in (0) := bwa_in (1);
393
                bwb_in (0) := bwb_in (1);
394
                bwc_in (0) := bwc_in (1);
395
                bwd_in (0) := bwd_in (1);
396
                bwa_in (1) := bwa_in (2);
397
                bwb_in (1) := bwb_in (2);
398
                bwc_in (1) := bwc_in (2);
399
                bwd_in (1) := bwd_in (2);
400
                bwa_in (2) := Bwa_n;
401
                bwb_in (2) := Bwb_n;
402
                bwc_in (2) := Bwc_n;
403
                bwd_in (2) := Bwd_n;
404
 
405
                -- Write Data to Memory
406
                IF rw_in (0) = '0' AND bwa_in (0) = '0' THEN
407
                    bank0 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ( ((data_bits-4) / 4) - 1 DOWNTO  0);
408
                END IF;
409
                IF rw_in (0) = '0' AND bwb_in (0) = '0' THEN
410
                    bank1 (CONV_INTEGER1 (Addr_write)) := '0' & Dq (((data_bits-4) / 2 - 1) DOWNTO  ((data_bits-4) / 4));
411
                END IF;
412
                IF rw_in (0) = '0' AND bwc_in (0) = '0' THEN
413
                    bank2 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ((3 * ((data_bits-4) / 4)) - 1 DOWNTO  ((data_bits-4) / 2));
414
                END IF;
415
                IF rw_in (0) = '0' AND bwd_in (0) = '0' THEN
416
                    bank3 (CONV_INTEGER1 (Addr_write)) := '0' & Dq ((data_bits-4) - 1 DOWNTO  (3 * ((data_bits-4) / 4)));
417
                END IF;
418
            END IF;
419
 
420
                Addr_read_sig   <= Addr_read;
421
 
422
            -- Read Data from Memory Array
423
            IF ce_in (0) = '1' AND rw_in (1) = '1' THEN
424
                dout (((data_bits-4) / 4) - 1 DOWNTO  0) <= bank0 (CONV_INTEGER1 (Addr_read))(7 downto 0);
425
                dout (((data_bits-4) / 2 - 1) DOWNTO  ((data_bits-4) / 4)) <= bank1 (CONV_INTEGER1 (Addr_read))(7 downto 0);
426
                dout ((3 * ((data_bits-4) / 4)) - 1 DOWNTO  ((data_bits-4) / 2)) <= bank2 (CONV_INTEGER1 (Addr_read))(7 downto 0);
427
                dout ((data_bits-4) - 1 DOWNTO  (3 * ((data_bits-4) / 4))) <= bank3 (CONV_INTEGER1 (Addr_read))(7 downto 0);
428
 
429
--                dout ((data_bits / 4) - 1 DOWNTO  0) <= bank0 (CONV_INTEGER1 (Addr_read));
430
--                dout ((data_bits / 2 - 1) DOWNTO  (data_bits / 4)) <= bank1 (CONV_INTEGER1 (Addr_read));
431
--                dout ((3 * (data_bits / 4)) - 1 DOWNTO  (data_bits / 2)) <= bank2 (CONV_INTEGER1 (Addr_read));
432
--                dout (data_bits - 1 DOWNTO  (3 * (data_bits / 4))) <= bank3 (CONV_INTEGER1 (Addr_read));
433
 
434
            ELSE
435
                dout <= (OTHERS => 'Z');
436
            END IF;
437
       END IF;
438
    END PROCESS;
439
 
440
END behave;
441
 
442
 
443
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.