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dimamali |
Leon2 memory controller
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CONFIG_MCTRL_LEON2
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Say Y here to enable the LEON2 memory controller. The controller
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can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
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and SRAM is programmable to 8-, 16- or 32-bits.
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8-bit memory support
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CONFIG_MCTRL_8BIT
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If you say Y here, the PROM/SRAM memory controller will support
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8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
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Say N to save a few hundred gates.
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16-bit memory support
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CONFIG_MCTRL_16BIT
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If you say Y here, the PROM/SRAM memory controller will support
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16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
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Say N to save a few hundred gates.
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Write strobe feedback
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CONFIG_MCTRL_WFB
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If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
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be used to enable the data bus drivers during write cycles. This
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will guarantee that the data is still valid on the rising edge of
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the write strobe. If you say N, the write strobes and the data bus
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drivers will be clocked on the rising edge, potentially creating
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a hold time problem in external memory or I/O. However, in all
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practical cases, there is enough capacitance in the data bus lines
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to keep the value stable for a few (many?) nano-seconds after the
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buffers have been disabled, making it safe to say N and remove a
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combinational path in the netlist that might be difficult to
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analyze.
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Write strobe feedback
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CONFIG_MCTRL_5CS
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If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
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be enabled. If you don't intend to use it, say N and save some gates.
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SDRAM controller enable
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CONFIG_MCTRL_SDRAM
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Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
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intend to use SDRAM, say N and save about 1 kgates.
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SDRAM controller inverted clock
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CONFIG_MCTRL_SDRAM_INVCLK
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If you say Y here, the SDRAM controller output signals will be delayed
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with 1/2 clock in respect to the SDRAM clock. This will allow the used
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of an SDRAM clock which in not strictly in phase with the internal
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clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
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On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
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say Y. On ASIC targets, say N and tell your foundry to balance the
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SDRAM clock output.
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SDRAM separate address buses
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CONFIG_MCTRL_SDRAM_SEPBUS
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Say Y here if your SDRAM is connected through separate address
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and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
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board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
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64-bit data bus
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CONFIG_MCTRL_SDRAM_BUS64
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Say Y here to enable 64-bit SDRAM data bus.
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Page burst enable
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CONFIG_MCTRL_PAGE
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Say Y here to enable SDRAM page burst operation. This will implement
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read operations using page bursts rather than 8-word bursts and save
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about 500 gates (100 LUTs). Note that not all SDRAM supports page
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burst, so use this option with care.
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Programmable page burst enable
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CONFIG_MCTRL_PROGPAGE
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Say Y here to enable programmable SDRAM page burst operation. This
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will allow to dynamically enable/disable page burst by setting
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bit 17 in MCFG2.
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