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dimamali |
----------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2004 GAISLER RESEARCH
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- See the file COPYING for the full details of the license.
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--
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-----------------------------------------------------------------------------
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-- Entity: l2uart
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-- File: l2uart.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Asynchronous UART originally developed for LEON2.
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-- Implements 8-bit data frame with one stop-bit.
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-- Programmable options:
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-- * parity bit (on/off)
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-- * parity polarity (odd/even)
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-- * baud-rate (12-bit programmable divider)
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-- * hardware flow-control (CTS/RTS)
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-- * Loop-back testing
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--
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-- Error-detection in receiver detects parity, framing
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-- break and overrun errors.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.uart.all;
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use grlib.devices.all;
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--pragma translate_off
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use std.textio.all;
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--pragma translate_on
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entity l2uart is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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console : integer := 0;
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pirq : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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uarti : in uart_in_type;
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uarto : out uart_out_type);
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end;
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architecture rtl of l2uart is
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constant REVISION : integer := 1;
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constant pconfig : apb_config_type := (
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1 => apb_iobar(paddr, pmask));
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type rxfsmtype is (idle, startbit, data, cparity, stopbit);
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type txfsmtype is (idle, data, cparity, stopbit);
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type uartregs is record
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rxen : std_ulogic; -- receiver enabled
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txen : std_ulogic; -- transmitter enabled
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rirqen : std_ulogic; -- receiver irq enable
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tirqen : std_ulogic; -- transmitter irq enable
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parsel : std_ulogic; -- parity select
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paren : std_ulogic; -- parity select
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flow : std_ulogic; -- flow control enable
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loopb : std_ulogic; -- loop back mode enable
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dready : std_ulogic; -- data ready
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rsempty : std_ulogic; -- receiver shift register empty (internal)
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tsempty : std_ulogic; -- transmitter shift register empty
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thempty : std_ulogic; -- transmitter hold register empty
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break : std_ulogic; -- break detected
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ovf : std_ulogic; -- receiver overflow
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parerr : std_ulogic; -- parity error
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frame : std_ulogic; -- framing error
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rtsn : std_ulogic; -- request to send
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extclken : std_ulogic; -- use external baud rate clock
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extclk : std_ulogic; -- rising edge detect register
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rhold : std_logic_vector(7 downto 0);
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rshift : std_logic_vector(7 downto 0);
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tshift : std_logic_vector(10 downto 0);
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thold : std_logic_vector(7 downto 0);
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irq : std_ulogic; -- tx/rx interrupt (internal)
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tpar : std_ulogic; -- tx data parity (internal)
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txstate : txfsmtype;
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txclk : std_logic_vector(2 downto 0); -- tx clock divider
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txtick : std_ulogic; -- tx clock (internal)
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rxstate : rxfsmtype;
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rxclk : std_logic_vector(2 downto 0); -- rx clock divider
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rxdb : std_logic_vector(1 downto 0); -- rx delay
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dpar : std_ulogic; -- rx data parity (internal)
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rxtick : std_ulogic; -- rx clock (internal)
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tick : std_ulogic; -- rx clock (internal)
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scaler : std_logic_vector(11 downto 0);
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brate : std_logic_vector(11 downto 0);
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rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
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txd : std_ulogic; -- transmitter data
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end record;
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signal r, rin : uartregs;
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begin
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uartop : process(rst, r, apbi, uarti )
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variable rdata : std_logic_vector(31 downto 0);
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variable scaler : std_logic_vector(11 downto 0);
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variable rxclk, txclk : std_logic_vector(2 downto 0);
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variable rxd, ctsn : std_ulogic;
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variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
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variable v : uartregs;
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--pragma translate_off
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variable L1 : line;
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variable CH : character;
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variable FIRST : boolean := true;
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variable pt : time := 0 ns;
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--pragma translate_on
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begin
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v := r; irq := (others => '0'); irq(pirq) := r.irq;
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v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
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rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
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-- scaler
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scaler := r.scaler - 1;
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if (r.rxen or r.txen) = '1' then
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v.scaler := scaler;
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v.tick := scaler(11) and not r.scaler(11);
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if v.tick = '1' then v.scaler := r.brate; end if;
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end if;
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-- optional external uart clock
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v.extclk := uarti.extclk;
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if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
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-- read/write registers
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case apbi.paddr(3 downto 2) is
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when "00" =>
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rdata(7 downto 0) := r.rhold;
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if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
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v.dready := '0';
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end if;
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when "01" =>
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rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
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r.break & r.thempty & r.tsempty & r.dready;
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--pragma translate_off
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if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
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--pragma translate_on
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when "10" =>
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rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel &
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r.tirqen & r.rirqen & r.txen & r.rxen;
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when others =>
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rdata(11 downto 0) := r.brate;
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end case;
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(3 downto 2) is
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when "01" =>
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v.frame := apbi.pwdata(6);
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v.parerr := apbi.pwdata(5);
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v.ovf := apbi.pwdata(4);
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v.break := apbi.pwdata(3);
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when "10" =>
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v.extclken := apbi.pwdata(8);
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v.loopb := apbi.pwdata(7);
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v.flow := apbi.pwdata(6);
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v.paren := apbi.pwdata(5);
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v.parsel := apbi.pwdata(4);
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v.tirqen := apbi.pwdata(3);
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v.rirqen := apbi.pwdata(2);
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v.txen := apbi.pwdata(1);
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v.rxen := apbi.pwdata(0);
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when "11" =>
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v.brate := apbi.pwdata(11 downto 0);
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v.scaler := apbi.pwdata(11 downto 0);
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when others =>
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end case;
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end if;
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-- tx clock
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txclk := r.txclk + 1;
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if r.tick = '1' then
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v.txclk := txclk;
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v.txtick := r.txclk(2) and not txclk(2);
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end if;
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-- rx clock
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rxclk := r.rxclk + 1;
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if r.tick = '1' then
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v.rxclk := rxclk;
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v.rxtick := r.rxclk(2) and not rxclk(2);
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end if;
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-- filter rx data
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v.rxf := r.rxf(6 downto 0) & uarti.rxd;
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if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
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r.rxf(7)) = r.rxf(6 downto 0))
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then v.rxdb(0) := r.rxf(7); end if;
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-- loop-back mode
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if r.loopb = '1' then
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v.rxdb(0) := r.tshift(0); ctsn := r.dready and not r.rsempty;
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else
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ctsn := uarti.ctsn;
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end if;
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rxd := r.rxdb(0);
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-- transmitter operation
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case r.txstate is
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when idle => -- idle state
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if (r.txtick = '1') then v.tsempty := '1'; end if;
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if ((r.txen and (not r.thempty) and r.txtick) and
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((not ctsn) or not r.flow)) = '1' then
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v.tshift := "10" & r.thold & '0'; v.txstate := data;
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v.tpar := r.parsel; v.irq := r.tirqen; v.thempty := '1';
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v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
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end if;
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when data => -- transmitt data frame
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if r.txtick = '1' then
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v.tpar := r.tpar xor r.tshift(1);
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v.tshift := '1' & r.tshift(10 downto 1);
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if r.tshift(10 downto 1) = "1111111110" then
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if r.paren = '1' then
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v.tshift(0) := r.tpar; v.txstate := cparity;
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else
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v.tshift(0) := '1'; v.txstate := stopbit;
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end if;
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end if;
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end if;
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when cparity => -- transmitt parity bit
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if r.txtick = '1' then
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v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
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end if;
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when stopbit => -- transmitt stop bit
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if r.txtick = '1' then
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v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
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end if;
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end case;
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-- writing of tx data register must be done after tx fsm to get correct
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-- operation of thempty flag
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(3 downto 2) is
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when "00" =>
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v.thold := apbi.pwdata(7 downto 0); v.thempty := '0';
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--pragma translate_off
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if CONSOLE = 1 then
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if first then L1:= new string'(""); first := false; end if; --'
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if apbi.penable'event then --'
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CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
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if CH = CR then
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std.textio.writeline(OUTPUT, L1);
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elsif CH /= LF then
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std.textio.write(L1,CH);
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end if;
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pt := now;
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end if;
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end if;
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--pragma translate_on
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when others => null;
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end case;
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end if;
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-- receiver operation
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284 |
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case r.rxstate is
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when idle => -- wait for start bit
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if ((not r.rsempty) and not r.dready) = '1' then
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v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
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end if;
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if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
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v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
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if v.rsempty = '0' then v.ovf := '1'; end if;
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v.rsempty := '0'; v.rxtick := '0';
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end if;
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when startbit => -- check validity of start bit
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if r.rxtick = '1' then
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if rxd = '0' then
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v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
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v.dpar := r.parsel;
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else
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v.rxstate := idle;
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end if;
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end if;
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when data => -- receive data frame
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if r.rxtick = '1' then
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v.dpar := r.dpar xor rxd;
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v.rshift := rxd & r.rshift(7 downto 1);
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if r.rshift(0) = '0' then
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if r.paren = '1' then v.rxstate := cparity;
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else v.rxstate := stopbit; v.dpar := '0'; end if;
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end if;
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end if;
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when cparity => -- receive parity bit
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if r.rxtick = '1' then
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v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
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end if;
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when stopbit => -- receive stop bit
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318 |
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if r.rxtick = '1' then
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v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
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if rxd = '1' then
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v.parerr := r.dpar; v.rsempty := r.dpar;
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if v.dready = '0' then
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v.rhold := r.rshift; v.rsempty := '1'; v.dready := not r.dpar;
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end if;
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325 |
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else
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326 |
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|
if r.rshift = "00000000" then v.break := '1';
|
327 |
|
|
else v.frame := '1'; end if;
|
328 |
|
|
v.rsempty := '1';
|
329 |
|
|
end if;
|
330 |
|
|
v.rxstate := idle;
|
331 |
|
|
end if;
|
332 |
|
|
|
333 |
|
|
end case;
|
334 |
|
|
|
335 |
|
|
if r.rxtick = '1' then
|
336 |
|
|
v.rtsn := (r.dready and not r.rsempty) or r.loopb;
|
337 |
|
|
end if;
|
338 |
|
|
|
339 |
|
|
v.txd := r.tshift(0) or r.loopb;
|
340 |
|
|
|
341 |
|
|
-- reset operation
|
342 |
|
|
|
343 |
|
|
if rst = '0' then
|
344 |
|
|
v.frame := '0'; v.rsempty := '1';
|
345 |
|
|
v.parerr := '0'; v.ovf := '0'; v.break := '0'; v.thempty := '1';
|
346 |
|
|
v.tsempty := '1'; v.dready := '0'; v.txen := '0'; v.rxen := '0';
|
347 |
|
|
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
|
348 |
|
|
v.extclken := '0'; v.rtsn := '1'; v.flow := '0';
|
349 |
|
|
v.txclk := (others => '0'); v.rxclk := (others => '0');
|
350 |
|
|
end if;
|
351 |
|
|
|
352 |
|
|
-- update registers
|
353 |
|
|
|
354 |
|
|
rin <= v;
|
355 |
|
|
|
356 |
|
|
-- drive outputs
|
357 |
|
|
|
358 |
|
|
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
|
359 |
|
|
apbo.prdata <= rdata; apbo.pirq <= irq;
|
360 |
|
|
apbo.pindex <= pindex;
|
361 |
|
|
|
362 |
|
|
end process;
|
363 |
|
|
|
364 |
|
|
apbo.pconfig <= pconfig;
|
365 |
|
|
|
366 |
|
|
regs : process(clk)
|
367 |
|
|
begin if rising_edge(clk) then r <= rin; end if; end process;
|
368 |
|
|
|
369 |
|
|
-- pragma translate_off
|
370 |
|
|
bootmsg : report_version
|
371 |
|
|
generic map ("l2uart" & tost(pindex) &
|
372 |
|
|
": LEON2 Generic UART rev " & tost(REVISION) & ", irq " & tost(pirq));
|
373 |
|
|
-- pragma translate_on
|
374 |
|
|
|
375 |
|
|
end;
|