1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- This file is a part of the GRLIB VHDL IP LIBRARY
|
3 |
|
|
-- Copyright (C) 2003, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program; if not, write to the Free Software
|
17 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 |
|
|
-----------------------------------------------------------------------------
|
19 |
|
|
-- Entity: ahbtbp
|
20 |
|
|
-- File: ahbtbp.vhd
|
21 |
|
|
-- Author: Nils-Johan Wessman - Gaisler Research
|
22 |
|
|
-- Description: AHB Testbench package
|
23 |
|
|
------------------------------------------------------------------------------
|
24 |
|
|
|
25 |
|
|
library IEEE;
|
26 |
|
|
use IEEE.std_logic_1164.all;
|
27 |
|
|
|
28 |
|
|
library grlib;
|
29 |
|
|
use grlib.amba.all;
|
30 |
|
|
use grlib.stdlib.all;
|
31 |
|
|
use grlib.devices.all;
|
32 |
|
|
|
33 |
|
|
package ahbtbp is
|
34 |
|
|
type ahbtbm_ctrl_type is record
|
35 |
|
|
delay : std_logic_vector(7 downto 0);
|
36 |
|
|
dbgl : integer;
|
37 |
|
|
reset : std_logic;
|
38 |
|
|
end record;
|
39 |
|
|
type ahbtbm_access_type is record
|
40 |
|
|
haddr : std_logic_vector(31 downto 0);
|
41 |
|
|
hdata : std_logic_vector(31 downto 0);
|
42 |
|
|
htrans : std_logic_vector(1 downto 0);
|
43 |
|
|
hburst : std_logic_vector(2 downto 0);
|
44 |
|
|
hsize : std_logic_vector(2 downto 0);
|
45 |
|
|
hwrite : std_logic;
|
46 |
|
|
ctrl : ahbtbm_ctrl_type;
|
47 |
|
|
end record;
|
48 |
|
|
type ahbtbm_status_type is record
|
49 |
|
|
err : std_logic;
|
50 |
|
|
ecount : std_logic_vector(15 downto 0);
|
51 |
|
|
eaddr : std_logic_vector(31 downto 0);
|
52 |
|
|
edatac : std_logic_vector(31 downto 0);
|
53 |
|
|
edatar : std_logic_vector(31 downto 0);
|
54 |
|
|
hresp : std_logic_vector(1 downto 0);
|
55 |
|
|
end record;
|
56 |
|
|
type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type;
|
57 |
|
|
|
58 |
|
|
type ahbtbm_ctrl_in_type is record
|
59 |
|
|
ac : ahbtbm_access_type;
|
60 |
|
|
end record;
|
61 |
|
|
type ahbtbm_ctrl_out_type is record
|
62 |
|
|
rst : std_logic;
|
63 |
|
|
clk : std_logic;
|
64 |
|
|
update : std_logic;
|
65 |
|
|
dvalid : std_logic;
|
66 |
|
|
hrdata : std_logic_vector(31 downto 0);
|
67 |
|
|
status : ahbtbm_status_type;
|
68 |
|
|
end record;
|
69 |
|
|
|
70 |
|
|
type ahbtb_ctrl_type is record
|
71 |
|
|
i : ahbtbm_ctrl_in_type;
|
72 |
|
|
o : ahbtbm_ctrl_out_type;
|
73 |
|
|
end record;
|
74 |
|
|
|
75 |
|
|
constant ac_idle : ahbtbm_access_type :=
|
76 |
|
|
(haddr => x"00000000", hdata => x"00000000", htrans => "00",
|
77 |
|
|
hburst =>"000", hsize => "000", hwrite => '0',
|
78 |
|
|
ctrl => (delay => x"00", dbgl => 100, reset =>'0'));
|
79 |
|
|
constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle);
|
80 |
|
|
constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H',
|
81 |
|
|
update => 'H', dvalid => 'H', hrdata => (others => 'H'),
|
82 |
|
|
status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'),
|
83 |
|
|
edatac => (others => 'H'), edatar => (others => 'H'),
|
84 |
|
|
hresp => (others => 'H')));
|
85 |
|
|
|
86 |
|
|
impure function ptime return string;
|
87 |
|
|
-- pragma translate_off
|
88 |
|
|
|
89 |
|
|
-----------------------------------------------------------------------------
|
90 |
|
|
-- AHB testbench Master
|
91 |
|
|
-----------------------------------------------------------------------------
|
92 |
|
|
component ahbtbm is
|
93 |
|
|
generic (
|
94 |
|
|
hindex : integer := 0;
|
95 |
|
|
hirq : integer := 0;
|
96 |
|
|
venid : integer := 0;
|
97 |
|
|
devid : integer := 0;
|
98 |
|
|
version : integer := 0;
|
99 |
|
|
chprot : integer := 3;
|
100 |
|
|
incaddr : integer := 0);
|
101 |
|
|
port (
|
102 |
|
|
rst : in std_ulogic;
|
103 |
|
|
clk : in std_ulogic;
|
104 |
|
|
ctrli : in ahbtbm_ctrl_in_type;
|
105 |
|
|
ctrlo : out ahbtbm_ctrl_out_type;
|
106 |
|
|
ahbmi : in ahb_mst_in_type;
|
107 |
|
|
ahbmo : out ahb_mst_out_type
|
108 |
|
|
);
|
109 |
|
|
end component;
|
110 |
|
|
|
111 |
|
|
-----------------------------------------------------------------------------
|
112 |
|
|
-- AHB testbench Slave
|
113 |
|
|
-----------------------------------------------------------------------------
|
114 |
|
|
component ahbtbs is
|
115 |
|
|
generic (
|
116 |
|
|
hindex : integer := 0;
|
117 |
|
|
haddr : integer := 0;
|
118 |
|
|
hmask : integer := 16#fff#;
|
119 |
|
|
tech : integer := 0;
|
120 |
|
|
kbytes : integer := 1);
|
121 |
|
|
port (
|
122 |
|
|
rst : in std_ulogic;
|
123 |
|
|
clk : in std_ulogic;
|
124 |
|
|
ahbsi : in ahb_slv_in_type;
|
125 |
|
|
ahbso : out ahb_slv_out_type
|
126 |
|
|
);
|
127 |
|
|
end component;
|
128 |
|
|
|
129 |
|
|
-----------------------------------------------------------------------------
|
130 |
|
|
-- dprint (Debug print)
|
131 |
|
|
-----------------------------------------------------------------------------
|
132 |
|
|
procedure dprint(
|
133 |
|
|
constant doprint : in boolean;
|
134 |
|
|
constant s : in string);
|
135 |
|
|
|
136 |
|
|
-----------------------------------------------------------------------------
|
137 |
|
|
-- AMBATB Init
|
138 |
|
|
-----------------------------------------------------------------------------
|
139 |
|
|
procedure ahbtbminit(
|
140 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
141 |
|
|
|
142 |
|
|
-----------------------------------------------------------------------------
|
143 |
|
|
-- AMBATB DONE
|
144 |
|
|
-----------------------------------------------------------------------------
|
145 |
|
|
procedure ahbtbmdone(
|
146 |
|
|
constant stop: in integer;
|
147 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
148 |
|
|
|
149 |
|
|
-----------------------------------------------------------------------------
|
150 |
|
|
-- AMBATB Idle
|
151 |
|
|
-----------------------------------------------------------------------------
|
152 |
|
|
procedure ahbtbmidle(
|
153 |
|
|
constant sync: in boolean;
|
154 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
155 |
|
|
|
156 |
|
|
-----------------------------------------------------------------------------
|
157 |
|
|
-- AMBA AHB write access
|
158 |
|
|
-----------------------------------------------------------------------------
|
159 |
|
|
procedure ahbwrite(
|
160 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
161 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
162 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
163 |
|
|
constant debug : in integer;
|
164 |
|
|
constant appidle : in boolean;
|
165 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
166 |
|
|
|
167 |
|
|
-----------------------------------------------------------------------------
|
168 |
|
|
-- AMBA AHB write access (htrans)
|
169 |
|
|
-----------------------------------------------------------------------------
|
170 |
|
|
procedure ahbwrite(
|
171 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
172 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
173 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
174 |
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
175 |
|
|
constant hburst : in std_logic;
|
176 |
|
|
constant debug : in integer;
|
177 |
|
|
constant appidle : in boolean;
|
178 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
179 |
|
|
|
180 |
|
|
-----------------------------------------------------------------------------
|
181 |
|
|
-- AMBA AHB write access (Inc Burst)
|
182 |
|
|
-----------------------------------------------------------------------------
|
183 |
|
|
procedure ahbwrite(
|
184 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
185 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
186 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
187 |
|
|
constant count : in integer;
|
188 |
|
|
constant debug : in integer;
|
189 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
190 |
|
|
|
191 |
|
|
-----------------------------------------------------------------------------
|
192 |
|
|
-- AMBA AHB read access
|
193 |
|
|
-----------------------------------------------------------------------------
|
194 |
|
|
procedure ahbread(
|
195 |
|
|
constant address : in std_logic_vector(31 downto 0); -- Address
|
196 |
|
|
constant data : in std_logic_vector(31 downto 0); -- Data
|
197 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
198 |
|
|
constant debug : in integer;
|
199 |
|
|
constant appidle : in boolean;
|
200 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
201 |
|
|
|
202 |
|
|
-----------------------------------------------------------------------------
|
203 |
|
|
-- AMBA AHB read access (htrans)
|
204 |
|
|
-----------------------------------------------------------------------------
|
205 |
|
|
procedure ahbread(
|
206 |
|
|
constant address : in std_logic_vector(31 downto 0); -- Address
|
207 |
|
|
constant data : in std_logic_vector(31 downto 0); -- Data
|
208 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
209 |
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
210 |
|
|
constant hburst : in std_logic;
|
211 |
|
|
constant debug : in integer;
|
212 |
|
|
constant appidle : in boolean;
|
213 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
214 |
|
|
|
215 |
|
|
-----------------------------------------------------------------------------
|
216 |
|
|
-- AMBA AHB read access (Inc Burst)
|
217 |
|
|
-----------------------------------------------------------------------------
|
218 |
|
|
procedure ahbread(
|
219 |
|
|
constant address : in std_logic_vector(31 downto 0); -- Start address
|
220 |
|
|
constant data : in std_logic_vector(31 downto 0); -- Start data
|
221 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
222 |
|
|
constant count : in integer;
|
223 |
|
|
constant debug : in integer;
|
224 |
|
|
signal ctrl : inout ahbtb_ctrl_type);
|
225 |
|
|
|
226 |
|
|
end ahbtbp;
|
227 |
|
|
|
228 |
|
|
package body ahbtbp is
|
229 |
|
|
|
230 |
|
|
impure function ptime return string is
|
231 |
|
|
variable s : string(1 to 20);
|
232 |
|
|
variable length : integer := tost(NOW / 1 ns)'length;
|
233 |
|
|
begin
|
234 |
|
|
s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns ";
|
235 |
|
|
return s(1 to length + 9);
|
236 |
|
|
end function ptime;
|
237 |
|
|
|
238 |
|
|
-----------------------------------------------------------------------------
|
239 |
|
|
-- dprint (Debug print)
|
240 |
|
|
-----------------------------------------------------------------------------
|
241 |
|
|
procedure dprint(
|
242 |
|
|
constant doprint : in boolean;
|
243 |
|
|
constant s : in string) is
|
244 |
|
|
begin
|
245 |
|
|
if doprint = true then
|
246 |
|
|
print(s);
|
247 |
|
|
end if;
|
248 |
|
|
end procedure dprint;
|
249 |
|
|
|
250 |
|
|
|
251 |
|
|
-----------------------------------------------------------------------------
|
252 |
|
|
-- AHBTB init
|
253 |
|
|
-----------------------------------------------------------------------------
|
254 |
|
|
procedure ahbtbminit(
|
255 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
256 |
|
|
begin
|
257 |
|
|
ctrl.o <= ctrlo_nodrive;
|
258 |
|
|
ctrl.i <= ctrli_idle;
|
259 |
|
|
--ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010";
|
260 |
|
|
--ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000";
|
261 |
|
|
--ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0';
|
262 |
|
|
wait until ctrl.o.rst = '1';
|
263 |
|
|
print("**********************************************************");
|
264 |
|
|
print(" AHBTBM Testbench Init");
|
265 |
|
|
print("**********************************************************");
|
266 |
|
|
end procedure ahbtbminit;
|
267 |
|
|
|
268 |
|
|
-----------------------------------------------------------------------------
|
269 |
|
|
-- AMBTB DONE
|
270 |
|
|
-----------------------------------------------------------------------------
|
271 |
|
|
procedure ahbtbmdone(
|
272 |
|
|
constant stop: in integer;
|
273 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
274 |
|
|
begin
|
275 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
276 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
277 |
|
|
ctrl.i <= ctrli_idle;
|
278 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
279 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
280 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
281 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
282 |
|
|
print("**********************************************************");
|
283 |
|
|
print(" AHBTBM Testbench Done");
|
284 |
|
|
print("**********************************************************");
|
285 |
|
|
wait for 100 ns;
|
286 |
|
|
assert stop = 0
|
287 |
|
|
report "ahbtb testbench done!"
|
288 |
|
|
severity FAILURE;
|
289 |
|
|
end procedure ahbtbmdone;
|
290 |
|
|
|
291 |
|
|
-----------------------------------------------------------------------------
|
292 |
|
|
-- AMBTB Idle
|
293 |
|
|
-----------------------------------------------------------------------------
|
294 |
|
|
procedure ahbtbmidle(
|
295 |
|
|
constant sync: in boolean;
|
296 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
297 |
|
|
begin
|
298 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
299 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
300 |
|
|
ctrl.i <= ctrli_idle;
|
301 |
|
|
if sync = true then
|
302 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
303 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
304 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
305 |
|
|
end if;
|
306 |
|
|
end procedure ahbtbmidle;
|
307 |
|
|
|
308 |
|
|
-----------------------------------------------------------------------------
|
309 |
|
|
-- AMBA AHB write access
|
310 |
|
|
-----------------------------------------------------------------------------
|
311 |
|
|
procedure ahbwrite(
|
312 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
313 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
314 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
315 |
|
|
constant debug : in integer;
|
316 |
|
|
constant appidle : in boolean;
|
317 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
318 |
|
|
begin
|
319 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
320 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
321 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
322 |
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
323 |
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
324 |
|
|
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000";
|
325 |
|
|
if appidle = true then
|
326 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
327 |
|
|
ctrl.i <= ctrli_idle;
|
328 |
|
|
end if;
|
329 |
|
|
end procedure ahbwrite;
|
330 |
|
|
|
331 |
|
|
-----------------------------------------------------------------------------
|
332 |
|
|
-- AMBA AHB write access (htrans)
|
333 |
|
|
-----------------------------------------------------------------------------
|
334 |
|
|
procedure ahbwrite(
|
335 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
336 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
337 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
338 |
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
339 |
|
|
constant hburst : in std_logic;
|
340 |
|
|
constant debug : in integer;
|
341 |
|
|
constant appidle : in boolean;
|
342 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
343 |
|
|
begin
|
344 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
345 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
346 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
347 |
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
348 |
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
349 |
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1';
|
350 |
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
351 |
|
|
if appidle = true then
|
352 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
353 |
|
|
ctrl.i <= ctrli_idle;
|
354 |
|
|
end if;
|
355 |
|
|
end procedure ahbwrite;
|
356 |
|
|
|
357 |
|
|
-----------------------------------------------------------------------------
|
358 |
|
|
-- AMBA AHB write access (Inc Burst)
|
359 |
|
|
-----------------------------------------------------------------------------
|
360 |
|
|
procedure ahbwrite(
|
361 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
362 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
363 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
364 |
|
|
constant count : in integer;
|
365 |
|
|
constant debug : in integer;
|
366 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
367 |
|
|
variable vaddr : std_logic_vector(31 downto 0);
|
368 |
|
|
variable vdata : std_logic_vector(31 downto 0);
|
369 |
|
|
variable vhtrans : std_logic_vector(1 downto 0);
|
370 |
|
|
begin
|
371 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
372 |
|
|
vaddr := address; vdata := data; vhtrans := "10";
|
373 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
374 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
375 |
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
376 |
|
|
ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001";
|
377 |
|
|
for i in 0 to count - 1 loop
|
378 |
|
|
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
|
379 |
|
|
ctrl.i.ac.htrans <= vhtrans;
|
380 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
381 |
|
|
vaddr := vaddr + x"4"; vdata := vdata + 1;
|
382 |
|
|
vhtrans := "11";
|
383 |
|
|
end loop;
|
384 |
|
|
ctrl.i <= ctrli_idle;
|
385 |
|
|
end procedure ahbwrite;
|
386 |
|
|
|
387 |
|
|
-----------------------------------------------------------------------------
|
388 |
|
|
-- AMBA AHB read access
|
389 |
|
|
-----------------------------------------------------------------------------
|
390 |
|
|
procedure ahbread(
|
391 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
392 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
393 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
394 |
|
|
constant debug : in integer;
|
395 |
|
|
constant appidle : in boolean;
|
396 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
397 |
|
|
begin
|
398 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
399 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
400 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
401 |
|
|
ctrl.i.ac.hsize <= '0' & size;
|
402 |
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
403 |
|
|
ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000";
|
404 |
|
|
if appidle = true then
|
405 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
406 |
|
|
ctrl.i <= ctrli_idle;
|
407 |
|
|
end if;
|
408 |
|
|
end procedure ahbread;
|
409 |
|
|
|
410 |
|
|
-----------------------------------------------------------------------------
|
411 |
|
|
-- AMBA AHB read access (htrans)
|
412 |
|
|
-----------------------------------------------------------------------------
|
413 |
|
|
procedure ahbread(
|
414 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
415 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
416 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
417 |
|
|
constant htrans : in std_logic_vector(1 downto 0);
|
418 |
|
|
constant hburst : in std_logic;
|
419 |
|
|
constant debug : in integer;
|
420 |
|
|
constant appidle : in boolean;
|
421 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
422 |
|
|
begin
|
423 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
424 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
425 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
426 |
|
|
ctrl.i.ac.hsize <= '0' & size;
|
427 |
|
|
ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data;
|
428 |
|
|
ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0';
|
429 |
|
|
ctrl.i.ac.hburst <= "00" & hburst;
|
430 |
|
|
if appidle = true then
|
431 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
432 |
|
|
ctrl.i <= ctrli_idle;
|
433 |
|
|
end if;
|
434 |
|
|
end procedure ahbread;
|
435 |
|
|
|
436 |
|
|
-----------------------------------------------------------------------------
|
437 |
|
|
-- AMBA AHB read access (Inc Burst)
|
438 |
|
|
-----------------------------------------------------------------------------
|
439 |
|
|
procedure ahbread(
|
440 |
|
|
constant address : in std_logic_vector(31 downto 0);
|
441 |
|
|
constant data : in std_logic_vector(31 downto 0);
|
442 |
|
|
constant size : in std_logic_vector(1 downto 0);
|
443 |
|
|
constant count : in integer;
|
444 |
|
|
constant debug : in integer;
|
445 |
|
|
signal ctrl : inout ahbtb_ctrl_type) is
|
446 |
|
|
variable vaddr : std_logic_vector(31 downto 0);
|
447 |
|
|
variable vdata : std_logic_vector(31 downto 0);
|
448 |
|
|
variable vhtrans : std_logic_vector(1 downto 0);
|
449 |
|
|
begin
|
450 |
|
|
--ctrl.o <= ctrlo_nodrive;
|
451 |
|
|
vaddr := address; vdata := data; vhtrans := "10";
|
452 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
453 |
|
|
ctrl.i.ac.ctrl.dbgl <= debug;
|
454 |
|
|
ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size;
|
455 |
|
|
ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001";
|
456 |
|
|
for i in 0 to count - 1 loop
|
457 |
|
|
ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata;
|
458 |
|
|
ctrl.i.ac.htrans <= vhtrans;
|
459 |
|
|
wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk);
|
460 |
|
|
vaddr := vaddr + x"4"; vdata := vdata + 1;
|
461 |
|
|
vhtrans := "11";
|
462 |
|
|
end loop;
|
463 |
|
|
ctrl.i <= ctrli_idle;
|
464 |
|
|
end procedure ahbread;
|
465 |
|
|
|
466 |
|
|
-- pragma translate_on
|
467 |
|
|
|
468 |
|
|
end ahbtbp;
|
469 |
|
|
|