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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: atactrl
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-- File: atactrl.vhd
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-- Author: Jiri Gaisler, Gaisler Research
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-- Description: ATA controller
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library gaisler;
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use gaisler.ata.all;
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entity atactrl is
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generic (
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tech : integer := 0;
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fdepth : integer := 8;
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mhindex : integer := 0;
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shindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#ff0#;
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pirq : integer := 0;
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mwdma : integer := 0;
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TWIDTH : natural := 8; -- counter width
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 : natural := 6; -- 70ns
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PIO_mode0_T2 : natural := 28; -- 290ns
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PIO_mode0_T4 : natural := 2; -- 30ns
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PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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);
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port (
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rst : in std_ulogic;
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arst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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cfo : out cf_out_type;
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atai : in ata_in_type;
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atao : out ata_out_type
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);
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end;
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architecture rtl of atactrl is
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begin
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dmaen : if mwdma = 1 generate
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x0 : entity work.atactrl_dma generic map (tech, fdepth, mhindex, shindex, haddr, hmask,
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pirq, TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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port map (rst, arst, clk, ahbsi, ahbso, ahbmi, ahbmo, cfo,
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atai.ddi, atai.iordy, atai.intrq, atao.rstn, atao.ddo, atao.oen,
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atao.da, atao.cs0, atao.cs1, atao.dior, atao.diow, atao.dmack, atai.dmarq);
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end generate;
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nodma : if mwdma /= 1 generate
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x0 : entity work.atactrl_nodma generic map (shindex, haddr, hmask,
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pirq, TWIDTH, PIO_mode0_T1, PIO_mode0_T2, PIO_mode0_T4, PIO_mode0_Teoc)
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port map (rst, arst, clk, ahbsi, ahbso, cfo,
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atai.ddi, atai.iordy, atai.intrq, atao.rstn, atao.ddo, atao.oen,
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atao.da, atao.cs0, atao.cs1, atao.dior, atao.diow, atao.dmack);
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ahbmo <= ahbm_none;
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end generate;
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end;
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