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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: atahost_amba_slave
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-- File: atahost_amba_slave.vhd
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-- Author: Nils-Johan Wessman, Gaisler Research
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-- (Modified by E.Jagre Autumn 2006)
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-- Description: ATA controller
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.ata.all;
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use work.ata_inf.all;
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entity atahost_amba_slave is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#ff0#;
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pirq : integer := 0;
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DeviceID : integer := 0;
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RevisionNo : integer := 0;
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 : natural := 6; -- 70ns
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PIO_mode0_T2 : natural := 28; -- 290ns
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PIO_mode0_T4 : natural := 2; -- 30ns
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PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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-- Multiword DMA mode 0 settings (@100MHz clock)
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DMA_mode0_Tm : natural := 4; -- 50ns
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DMA_mode0_Td : natural := 21; -- 215ns
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DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
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);
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port (
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rst : in std_ulogic;
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arst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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cf_power: out std_logic;
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-- ata controller signals
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-- PIO control input
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PIOsel : out std_logic;
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PIOtip, -- PIO transfer in progress
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PIOack : in std_logic; -- PIO acknowledge signal
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PIOq : in std_logic_vector(15 downto 0); -- PIO data input
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PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
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irq : in std_logic; -- interrupt signal input
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PIOa : out std_logic_vector(3 downto 0):="0000";
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PIOd : out std_logic_vector(15 downto 0);
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PIOwe : out std_logic;
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-- DMA control inputs
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-- DMAsel : out std_logic;
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DMAtip, -- DMA transfer in progress
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-- DMAack, -- DMA transfer acknowledge
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DMARxEmpty, -- DMA receive buffer empty
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DMATxFull, -- DMA transmit buffer full
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DMA_dmarq : in std_logic; -- wishbone DMA request
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-- DMAq : in std_logic_vector(31 downto 0);
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-- outputs
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-- control register outputs
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IDEctrl_rst,
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IDEctrl_IDEen,
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IDEctrl_FATR1,
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IDEctrl_FATR0,
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IDEctrl_ppen,
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DMActrl_DMAen,
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DMActrl_dir,
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DMActrl_Bytesw, -- Jagre 2006-12-04, byte swap
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DMActrl_BeLeC0,
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DMActrl_BeLeC1 : out std_logic;
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-- CMD port timing registers
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PIO_cmdport_T1,
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PIO_cmdport_T2,
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PIO_cmdport_T4,
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PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
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PIO_cmdport_IORDYen : out std_logic;
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-- data-port0 timing registers
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PIO_dport0_T1,
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PIO_dport0_T2,
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PIO_dport0_T4,
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PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
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PIO_dport0_IORDYen : out std_logic;
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-- data-port1 timing registers
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PIO_dport1_T1,
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PIO_dport1_T2,
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PIO_dport1_T4,
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PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
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PIO_dport1_IORDYen : out std_logic;
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-- DMA device0 timing registers
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DMA_dev0_Tm,
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DMA_dev0_Td,
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DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
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-- DMA device1 timing registers
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DMA_dev1_Tm,
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DMA_dev1_Td,
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DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
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-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
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fr_BM : in bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
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to_BM : out slv_to_bm_type := SLV_TO_BM_RESET_VECTOR
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-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
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);
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end;
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architecture rtl of atahost_amba_slave is
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constant VERSION : amba_version_type := 0;
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constant hconfig : ahb_config_type := (
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4 => ahb_iobar(haddr, hmask),
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others => zero32);
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type PIOtiming_type is record
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T1,T2,T4,Teoc : std_logic_vector(7 downto 0);
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end record;
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type DMAtiming_type is record
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Tm,Td,Teoc : std_logic_vector(7 downto 0);
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end record;
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-- local registers
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type reg_type is record
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-- AHB signal
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hready : std_ulogic; -- Hready
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hsel : std_ulogic; -- Hsel
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hmbsel : std_logic_vector(0 to 2); -- Mem map select
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haddr : std_logic_vector(31 downto 0); -- Haddr
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hrdata : std_logic_vector(31 downto 0); -- Hreaddata
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hwdata : std_logic_vector(31 downto 0); -- Hwritedata
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hwrite : std_ulogic; -- Hwrite
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htrans : std_logic_vector(1 downto 0); -- Htrans type
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hburst : std_logic_vector(2 downto 0); -- Hburst type
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hresp : std_logic_vector(1 downto 0); -- Hresp type
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size : std_logic_vector(1 downto 0); -- Part of Hsize
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piosel : std_logic;
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irq : std_logic;
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irqv : std_logic_vector(NAHBIRQ-1 downto 0);
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pioack : std_logic;
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atasel : std_logic;
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-- reg signal
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ctrlreg : std_logic_vector(31 downto 0);
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statreg : std_logic_vector(31 downto 0);
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pio_cmd : PIOtiming_type;
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pio_dp0 : PIOtiming_type;
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pio_dp1 : PIOtiming_type;
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dma_dev0 : DMAtiming_type;
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dma_dev1 : DMAtiming_type;
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-- Bus master registers by Erik Jagre 2006-10-03 ------------------start-----
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bmcmd : std_logic_vector(7 downto 0); --Bus master IDE command register
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bmvd0 : std_logic_vector(31 downto 0); --Device specific (reserved)
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bmsta : std_logic_vector(7 downto 0); --Bus master IDE status register
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bmvd1 : std_logic_vector(31 downto 0); --Device specific (reserved)
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prdtb : std_logic_vector(31 downto 0); --Bus master IDE PRD table address
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fr_BM : bm_to_slv_type;
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-- Bus master registers by Erik Jagre 2006-10-03 ------------------end-------
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end record;
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signal r, ri : reg_type;
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begin
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-- ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq, fr_BM) Jagre 2007-02-08
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ctrl : process(rst, ahbsi, r, PIOack, PIOtip, PIOpp_full, irq, PIOq, DMAtip, dma_dmarq, dmatxfull, dmarxempty, fr_BM)
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variable v : reg_type; -- local variables for registers
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variable int : std_logic;
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begin
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-- Variable default settings to avoid latches
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v := r;
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v.hresp := HRESP_OKAY;
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v.irqv := (others => '0');
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int := '1';
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v.irq := irq;
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v.irqv(pirq) := v.irq and not r.irq;
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v.pioack := PIOack;
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-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
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v.fr_BM.err := fr_BM.err;
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v.fr_BM.done := fr_BM.done;
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v.bmvd0:=fr_bm.cur_base;
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v.bmvd1(15 downto 0):=fr_bm.cur_cnt;
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v.bmvd1(31 downto 15):=(others => '0');
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-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
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if (ahbsi.hready = '1') and (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
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v.size := ahbsi.hsize(1 downto 0);
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v.hwrite := ahbsi.hwrite;
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v.htrans := ahbsi.htrans;
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v.hburst := ahbsi.hburst;
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v.hsel := '1';
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v.haddr := ahbsi.haddr;
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v.piosel := ahbsi.haddr(6);
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v.atasel := ahbsi.haddr(6);
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if ahbsi.hwrite = '0' or ahbsi.haddr(6) = '1' then -- Read or ATA
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v.hready := '0';
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else -- Write
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v.hready := '1';
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end if;
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else
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v.hsel := '0';
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if PIOack = '1' then
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v.piosel := '0';
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end if;
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v.hready := r.pioack or not r.atasel;
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if r.pioack = '1' then
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v.atasel := '0';
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end if;
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end if;
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if r.hsel = '1' and r.atasel = '0' and r.hwrite = '1' then -- Write
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case r.haddr(5 downto 2) is
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when "0000" => -- Control register 0x0
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v.ctrlreg := ahbsi.hwdata;
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when "0001" => -- Status register 0x4
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int := ahbsi.hwdata(0); -- irq bit in status reg
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when "0010" => -- PIO Compatible timing register 0x8
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v.pio_cmd.T1 := ahbsi.hwdata(7 downto 0);
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v.pio_cmd.T2 := ahbsi.hwdata(15 downto 8);
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v.pio_cmd.T4 := ahbsi.hwdata(23 downto 16);
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v.pio_cmd.Teoc := ahbsi.hwdata(31 downto 24);
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when "0011" => -- PIO Fast timing register device 0 0xc
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v.pio_dp0.T1 := ahbsi.hwdata(7 downto 0);
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v.pio_dp0.T2 := ahbsi.hwdata(15 downto 8);
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v.pio_dp0.T4 := ahbsi.hwdata(23 downto 16);
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v.pio_dp0.Teoc := ahbsi.hwdata(31 downto 24);
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when "0100" => -- PIO Fast timing register device 1 0x10
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v.pio_dp1.T1 := ahbsi.hwdata(7 downto 0);
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v.pio_dp1.T2 := ahbsi.hwdata(15 downto 8);
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v.pio_dp1.T4 := ahbsi.hwdata(23 downto 16);
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v.pio_dp1.Teoc := ahbsi.hwdata(31 downto 24);
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when "0101" => -- DMA timing register device 0 0x14
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v.dma_dev0.Tm := ahbsi.hwdata(7 downto 0);
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v.dma_dev0.Td := ahbsi.hwdata(15 downto 8);
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v.dma_dev0.Teoc := ahbsi.hwdata(31 downto 24);
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when "0110" => -- DMA timing register device 1 0x18
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279 |
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v.dma_dev1.Tm := ahbsi.hwdata(7 downto 0);
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280 |
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v.dma_dev1.Td := ahbsi.hwdata(15 downto 8);
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281 |
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v.dma_dev1.Teoc := ahbsi.hwdata(31 downto 24);
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282 |
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-- Bus master registers by Erik Jagre 2006-10-03 -----------------start------
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283 |
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when "0111" => -- Bus master IDE command register 0x1C
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284 |
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v.bmcmd(7 downto 0) := ahbsi.hwdata(7 downto 0);
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285 |
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when "1000" => -- Device specific (reserved) 0x20
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286 |
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v.bmvd0(7 downto 0) := ahbsi.hwdata(7 downto 0);
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287 |
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when "1001" => -- Bus master IDE status register 0x24
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288 |
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v.bmsta(6 downto 1) := ahbsi.hwdata(6 downto 1); --bmsta(7) read only
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289 |
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if (ahbsi.hwdata(2)='1') then v.bmsta(2):='0'; end if; --reset IRQ
|
290 |
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if (ahbsi.hwdata(1)='1') then v.bmsta(1):='0'; end if; --reset Error
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291 |
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when "1010" => -- Device specific (reserved) 0x28
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292 |
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v.bmvd1(7 downto 0) := ahbsi.hwdata(7 downto 0);
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293 |
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when "1011" => -- Bus master IDE PRD table address 0x2C
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v.prdtb := ahbsi.hwdata;
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295 |
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-- Bus master registers by Erik Jagre 2006-10-03 -----------------end--------
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296 |
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when others => null;
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297 |
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end case;
|
298 |
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|
299 |
|
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elsif r.hsel = '1' and r.atasel = '1' and r.hwrite = '1' then -- ATA IO device 0x40-
|
300 |
|
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v.hwdata := ahbsi.hwdata;
|
301 |
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end if;
|
302 |
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|
303 |
|
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if r.hsel = '1' and r.atasel = '0' and r.hwrite = '0' then -- Read
|
304 |
|
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case r.haddr(5 downto 2) is
|
305 |
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when "0000" => -- Control register 0x0
|
306 |
|
|
v.hrdata := r.ctrlreg;
|
307 |
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when "0001" => -- Status register 0x4
|
308 |
|
|
v.hrdata := r.statreg;
|
309 |
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when "0010" => -- PIO Compatible timing register 0x8
|
310 |
|
|
v.hrdata := (r.pio_cmd.Teoc & r.pio_cmd.T4 & r.pio_cmd.T2 &
|
311 |
|
|
r.pio_cmd.T1);
|
312 |
|
|
when "0011" => -- PIO Fast timing register device 0 0xc
|
313 |
|
|
v.hrdata := (r.pio_dp0.Teoc & r.pio_dp0.T4 & r.pio_dp0.T2 &
|
314 |
|
|
r.pio_dp0.T1);
|
315 |
|
|
when "0100" => -- PIO Fast timing register device 1 0x10
|
316 |
|
|
v.hrdata := (r.pio_dp1.Teoc & r.pio_dp1.T4 & r.pio_dp1.T2 &
|
317 |
|
|
r.pio_dp1.T1);
|
318 |
|
|
when "0101" => -- DMA timing register device 0 0x14
|
319 |
|
|
v.hrdata := (r.dma_dev0.Teoc & x"00" & r.dma_dev0.Td &
|
320 |
|
|
r.dma_dev0.Tm);
|
321 |
|
|
when "0110" => -- DMA timing register device 1 0x18
|
322 |
|
|
v.hrdata := (r.dma_dev1.Teoc & x"00" & r.dma_dev1.Td &
|
323 |
|
|
r.dma_dev1.Tm);
|
324 |
|
|
-- Bus master registers by Erik Jagre 2006-10-03 -----------------start---
|
325 |
|
|
when "0111" => -- Bus master IDE command register 0x1C
|
326 |
|
|
v.hrdata := (others => '0'); --return 0 on reads
|
327 |
|
|
v.hrdata(3) := r.bmcmd(3); --except for bit 3
|
328 |
|
|
when "1000" => -- Device specific (reserved) 0x20
|
329 |
|
|
v.hrdata(31 downto 0) := r.bmvd0; --Erik Jagre 2006-11-13
|
330 |
|
|
--v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
|
331 |
|
|
--v.hrdata(7 downto 0) := r.bmvd0;
|
332 |
|
|
when "1001" => -- Bus master IDE status register 0x24
|
333 |
|
|
v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
|
334 |
|
|
v.hrdata(7 downto 0) := r.bmsta;
|
335 |
|
|
v.hrdata(7) := '1'; --simplex only
|
336 |
|
|
v.hrdata(4 downto 3) := (others => '0'); --return 0 on reads
|
337 |
|
|
when "1010" => -- Device specific (reserved) 0x28
|
338 |
|
|
v.hrdata(31 downto 0) := r.bmvd1; --Erik Jagre 2006-11-13
|
339 |
|
|
--v.hrdata(31 downto 8) := (others => '0'); --return 0 on reads
|
340 |
|
|
--v.hrdata(7 downto 0) := r.bmvd1;
|
341 |
|
|
when "1011" => -- Bus master IDE PRD table address 0x2C
|
342 |
|
|
v.hrdata := r.prdtb;
|
343 |
|
|
-- Bus master registers by Erik Jagre 2006-10-03 ------------------end----
|
344 |
|
|
when others =>
|
345 |
|
|
v.hrdata := x"aaaaaaaa";
|
346 |
|
|
end case;
|
347 |
|
|
elsif r.atasel = '1' then -- ATA IO device 0x40-
|
348 |
|
|
v.hrdata := (x"0000" & PIOq);
|
349 |
|
|
end if;
|
350 |
|
|
|
351 |
|
|
-- Status register
|
352 |
|
|
v.statreg(31 downto 0) := (others => '0'); -- clear all bits (read unused bits as '0')
|
353 |
|
|
v.statreg(31 downto 28) := std_logic_vector(to_unsigned(DeviceId,4)); -- set Device ID
|
354 |
|
|
v.statreg(27 downto 24) := std_logic_vector(to_unsigned(RevisionNo,4)); -- set revision number
|
355 |
|
|
v.statreg(16) := irq; --Erik Jagre 20006-11-13
|
356 |
|
|
v.statreg(15) := DMAtip;
|
357 |
|
|
v.statreg(10) := DMARxEmpty;
|
358 |
|
|
v.statreg(9) := DMATxFull;
|
359 |
|
|
v.statreg(8) := DMA_dmarq;
|
360 |
|
|
v.statreg(7) := PIOtip;
|
361 |
|
|
v.statreg(6) := PIOpp_full;
|
362 |
|
|
v.statreg(0) := (r.statreg(0) or (v.irq and not r.irq)) and int;
|
363 |
|
|
|
364 |
|
|
-- Bus master control by Erik Jagre 2006-10-03 -----------------start------
|
365 |
|
|
if (v.fr_BM.err='1' and r.fr_BM.err='0') then
|
366 |
|
|
v.bmsta(1):='1'; --set err on rising flank
|
367 |
|
|
end if;
|
368 |
|
|
|
369 |
|
|
if (v.irq='1' and r.irq='0') then
|
370 |
|
|
v.bmsta(2):='1'; --set irq on rising flank
|
371 |
|
|
end if;
|
372 |
|
|
|
373 |
|
|
if ((v.fr_BM.done='1' and r.fr_BM.done='0') or --BM done
|
374 |
|
|
(v.bmcmd(0)='0' and r.bmcmd(0)='1') or --Reset by software
|
375 |
|
|
(v.fr_BM.err='1' and r.fr_BM.err='0')) then --Error from BM
|
376 |
|
|
v.bmsta(0):='0'; --clear active
|
377 |
|
|
elsif (v.bmcmd(0)='1' and r.bmcmd(0)='0') then
|
378 |
|
|
v.bmsta(0):='1'; --set active on rising start flank
|
379 |
|
|
end if;
|
380 |
|
|
-- Bus master control by Erik Jagre 2006-10-03 ------------------end-------
|
381 |
|
|
|
382 |
|
|
-- reset
|
383 |
|
|
if rst = '0' then
|
384 |
|
|
v.ctrlreg := (0 => '1', others => '0');
|
385 |
|
|
v.statreg(0) := '0';
|
386 |
|
|
|
387 |
|
|
-- Bus master control by Erik Jagre 2006-10-04 -----------------start---
|
388 |
|
|
v.bmcmd := (others => '0');
|
389 |
|
|
v.bmvd0 := (others => '0');
|
390 |
|
|
v.bmsta := (7 => '1', others => '0');
|
391 |
|
|
v.bmvd1 := (others => '0');
|
392 |
|
|
v.prdtb := (others => '0');
|
393 |
|
|
|
394 |
|
|
-- Bus master control by Erik Jagre 2006-10-04 ------------------end----
|
395 |
|
|
|
396 |
|
|
v.haddr := (others => '0');
|
397 |
|
|
v.hwrite := '0';
|
398 |
|
|
v.hready := '1';
|
399 |
|
|
v.pioack := '0';
|
400 |
|
|
v.atasel := '0';
|
401 |
|
|
v.piosel := '0';
|
402 |
|
|
|
403 |
|
|
v.pio_cmd.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
|
404 |
|
|
v.pio_cmd.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
|
405 |
|
|
v.pio_cmd.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
|
406 |
|
|
v.pio_cmd.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
|
407 |
|
|
|
408 |
|
|
v.pio_dp0.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
|
409 |
|
|
v.pio_dp0.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
|
410 |
|
|
v.pio_dp0.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
|
411 |
|
|
v.pio_dp0.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
|
412 |
|
|
|
413 |
|
|
v.pio_dp1.T1 := conv_std_logic_vector(PIO_mode0_T1,8);
|
414 |
|
|
v.pio_dp1.T2 := conv_std_logic_vector(PIO_mode0_T2,8);
|
415 |
|
|
v.pio_dp1.T4 := conv_std_logic_vector(PIO_mode0_T4,8);
|
416 |
|
|
v.pio_dp1.Teoc := conv_std_logic_vector(PIO_mode0_Teoc,8);
|
417 |
|
|
|
418 |
|
|
v.dma_dev0.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
|
419 |
|
|
v.dma_dev0.Td := conv_std_logic_vector(DMA_mode0_Td,8);
|
420 |
|
|
v.dma_dev0.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
|
421 |
|
|
|
422 |
|
|
v.dma_dev1.Tm := conv_std_logic_vector(DMA_mode0_Tm,8);
|
423 |
|
|
v.dma_dev1.Td := conv_std_logic_vector(DMA_mode0_Td,8);
|
424 |
|
|
v.dma_dev1.Teoc := conv_std_logic_vector(DMA_mode0_Teoc,8);
|
425 |
|
|
end if;
|
426 |
|
|
|
427 |
|
|
-- assign control bits
|
428 |
|
|
cf_power <= r.ctrlreg(31);
|
429 |
|
|
DMActrl_DMAen <= r.bmcmd(0); --r.ctrlreg(15); --Erik Jagre 2006-10-24
|
430 |
|
|
DMActrl_dir <= not r.bmcmd(3); --r.ctrlreg(13); --Jagre 2006-12-04
|
431 |
|
|
DMActrl_Bytesw <= r.ctrlreg(11); --Jagre 2006-12-04, byteswap ATA data
|
432 |
|
|
DMActrl_BeLeC1 <= r.ctrlreg(9);
|
433 |
|
|
DMActrl_BeLeC0 <= r.ctrlreg(8);
|
434 |
|
|
IDEctrl_IDEen <= r.ctrlreg(7);
|
435 |
|
|
IDEctrl_FATR1 <= r.ctrlreg(6);
|
436 |
|
|
IDEctrl_FATR0 <= r.ctrlreg(5);
|
437 |
|
|
IDEctrl_ppen <= r.ctrlreg(4);
|
438 |
|
|
PIO_dport1_IORDYen <= r.ctrlreg(3);
|
439 |
|
|
PIO_dport0_IORDYen <= r.ctrlreg(2);
|
440 |
|
|
PIO_cmdport_IORDYen <= r.ctrlreg(1);
|
441 |
|
|
IDEctrl_rst <= r.ctrlreg(0);
|
442 |
|
|
|
443 |
|
|
-- CMD port timing
|
444 |
|
|
PIO_cmdport_T1 <= r.pio_cmd.T1; PIO_cmdport_T2 <= r.pio_cmd.T2;
|
445 |
|
|
PIO_cmdport_T4 <= r.pio_cmd.T4; PIO_cmdport_Teoc <= r.pio_cmd.Teoc;
|
446 |
|
|
|
447 |
|
|
-- data-port0 timing
|
448 |
|
|
PIO_dport0_T1 <= r.pio_dp0.T1; PIO_dport0_T2 <= r.pio_dp0.T2;
|
449 |
|
|
PIO_dport0_T4 <= r.pio_dp0.T4; PIO_dport0_Teoc <= r.pio_dp0.Teoc;
|
450 |
|
|
|
451 |
|
|
-- data-port1 timing
|
452 |
|
|
PIO_dport1_T1 <= r.pio_dp1.T1; PIO_dport1_T2 <= r.pio_dp1.T2;
|
453 |
|
|
PIO_dport1_T4 <= r.pio_dp1.T4; PIO_dport1_Teoc <= r.pio_dp1.Teoc;
|
454 |
|
|
|
455 |
|
|
-- DMA device0 timing
|
456 |
|
|
DMA_dev0_Tm <= r.dma_dev0.Tm; DMA_dev0_Td <= r.dma_dev0.Td;
|
457 |
|
|
DMA_dev0_Teoc <= r.dma_dev0.Teoc;
|
458 |
|
|
|
459 |
|
|
-- DMA device1 timing
|
460 |
|
|
DMA_dev1_Tm <= r.dma_dev0.Tm; DMA_dev1_Td <= r.dma_dev0.Td;
|
461 |
|
|
DMA_dev1_Teoc <= r.dma_dev0.Teoc;
|
462 |
|
|
|
463 |
|
|
-- Bus master control by Erik Jagre 2006-10-04 -----------------start---
|
464 |
|
|
--assign BM signal
|
465 |
|
|
-- to_BM.en<=r.bmcmd(0);Jagre 2007-1-15
|
466 |
|
|
to_BM.en<=r.bmsta(0);
|
467 |
|
|
to_BM.dir<=r.bmcmd(3);
|
468 |
|
|
to_BM.prdtb<=r.prdtb;
|
469 |
|
|
to_BM.prd_belec<=r.ctrlreg(10);
|
470 |
|
|
-- Bus master control by Erik Jagre 2006-10-04 ------------------end----
|
471 |
|
|
|
472 |
|
|
ri <= v;
|
473 |
|
|
|
474 |
|
|
PIOa <= r.haddr(5 downto 2);
|
475 |
|
|
PIOd <= r.hwdata(15 downto 0);
|
476 |
|
|
PIOsel <= r.piosel;
|
477 |
|
|
PIOwe <= r.hwrite;
|
478 |
|
|
-- DMAsel <= '0'; -- temp ***
|
479 |
|
|
|
480 |
|
|
ahbso.hready <= r.hready;
|
481 |
|
|
ahbso.hresp <= r.hresp;
|
482 |
|
|
ahbso.hrdata <= r.hrdata;
|
483 |
|
|
ahbso.hconfig <= hconfig;
|
484 |
|
|
ahbso.hcache <= '0';
|
485 |
|
|
ahbso.hirq <= r.irqv;
|
486 |
|
|
ahbso.hindex <= hindex;
|
487 |
|
|
|
488 |
|
|
end process;
|
489 |
|
|
|
490 |
|
|
regs : process(clk,rst)
|
491 |
|
|
begin
|
492 |
|
|
|
493 |
|
|
if rising_edge(clk) then
|
494 |
|
|
r <= ri;
|
495 |
|
|
end if;
|
496 |
|
|
|
497 |
|
|
if rst = '0' then
|
498 |
|
|
end if;
|
499 |
|
|
end process;
|
500 |
|
|
|
501 |
|
|
end;
|
502 |
|
|
|