Subversion Repositories mips_enhanced

SDRAM controller enable

CONFIG_DDR2SP

  Say Y here to enabled a 16-bit DDR266 SDRAM controller.

Power-on init

CONFIG_DDR2SP_INIT

  Say Y here to enable the automatic DDR initialization sequence.

  If disabled, the sequencemust be performed in software before

  the DDR can be used. If unsure, say Y.

Memory frequency

CONFIG_DDR2SP_FREQ

  Enter the frequency of the DDR clock (in MHz). The value is

  typically between 130 - 200, depending on system configuration.

  Some template design (such as the leon3-avnet-eval-lx25)

  calculate this value automatically and this value is not used.

Refresh to Activate

CONFIG_DDR2SP_TRFC

  Enter the Refresh to Activate timing (tRFC) in ns. The value is

  typically between 75 - 130, depending on memory chip implementation.

DDR2 Data width

CONFIG_DDR2SP_DATAWIDTH

  Select the width of the DDR2 data bus. 64-bit or 32-bit or

  16-bit can be selected. Only used in some template designs.

Column bits

CONFIG_DDR2SP_COL

  Select the number of colomn address bits of the DDR memory.

  Typical values are 8 - 11. Only needed when automatic DDR

  initialisation is choosen. The column size can always be

  programmed by software as well.

Chip select size

CONFIG_DDR2SP_MBYTE

  Select the memory size (Mbytes) that each chip select should decode.

  Only needed when automatic DDR initialisation is choosen. The chip

  select size can always be programmed by software as well.

Read data delay

CONFIG_DDR2SP_DELAY0 CONFIG_DDR2SP_DELAY1 CONFIG_DDR2SP_DELAY2 CONFIG_DDR2SP_DELAY3 CONFIG_DDR2SP_DELAY4 CONFIG_DDR2SP_DELAY5 CONFIG_DDR2SP_DELAY6 CONFIG_DDR2SP_DELAY7

  On Xilinx targets (virtex4 and virtex5), input delays are added to

  all data bits to align read data to the internal DDR clock signal.

  The delay can be set to a value of 0 to 63 tap-delays. Each tap-

  delay equals to ~78ps delay, with an reference clock at 200 MHz.

  This delay value is only a reset valus, it can be changed dynamically

  via a configuration register.