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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ddrsp
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-- File: ddrsp.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: 16-bit DDR266 SDRAM memory controller.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use grlib.devices.all;
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use gaisler.memctrl.all;
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entity ddrsp is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#f00#;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#fff#;
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MHz : integer := 100;
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col : integer := 9;
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Mbit : integer := 256;
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fast : integer := 0;
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pwron : integer := 0;
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oepol : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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sdi : in sdctrl_in_type;
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sdo : out sdctrl_out_type
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);
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end;
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architecture rtl of ddrsp is
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constant REVISION : integer := 0;
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constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
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constant CMD_REF : std_logic_vector(2 downto 0) := "100";
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constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
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constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
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constant hconfig : ahb_config_type := (
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4 => ahb_membar(haddr, '1', '1', hmask),
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5 => ahb_iobar(ioaddr, iomask),
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others => zero32);
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type mcycletype is (midle, active, ext, leadout);
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type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
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wr1, wr2, wr3, wr4a, wr4, wr5, sidle);
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type icycletype is (iidle, pre, ref1, ref2, emode, lmode, finish);
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-- sdram configuration register
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type sdram_cfg_type is record
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command : std_logic_vector(2 downto 0);
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csize : std_logic_vector(1 downto 0);
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bsize : std_logic_vector(2 downto 0);
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casdel : std_ulogic; -- tCD : 2/3 clock cycles
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trfc : std_logic_vector(2 downto 0);
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trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
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refresh : std_logic_vector(11 downto 0);
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renable : std_ulogic;
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dllrst : std_ulogic;
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refon : std_ulogic;
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cke : std_ulogic;
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end record;
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-- local registers
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type reg_type is record
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hready : std_ulogic;
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hsel : std_ulogic;
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bdrive : std_ulogic;
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qdrive : std_ulogic;
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nbdrive : std_ulogic;
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burst : std_ulogic;
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hio : std_ulogic;
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startsd : std_ulogic;
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mstate : mcycletype;
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sdstate : sdcycletype;
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cmstate : mcycletype;
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istate : icycletype;
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haddr : std_logic_vector(31 downto 0);
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hrdata : std_logic_vector(31 downto 0);
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hwdata : std_logic_vector(31 downto 0);
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hwrite : std_ulogic;
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htrans : std_logic_vector(1 downto 0);
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hresp : std_logic_vector(1 downto 0);
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size : std_logic_vector(1 downto 0);
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cfg : sdram_cfg_type;
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trfc : std_logic_vector(2 downto 0);
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refresh : std_logic_vector(11 downto 0);
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sdcsn : std_logic_vector(1 downto 0);
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sdwen : std_ulogic;
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rasn : std_ulogic;
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casn : std_ulogic;
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dqm : std_logic_vector(3 downto 0);
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address : std_logic_vector(16 downto 2); -- memory address
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end record;
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signal r, ri : reg_type;
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signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
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attribute syn_preserve : boolean;
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attribute syn_preserve of rbdrive : signal is true;
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begin
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ctrl : process(rst, ahbsi, r, sdi, rbdrive)
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variable v : reg_type; -- local variables for registers
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variable startsd : std_ulogic;
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variable dataout : std_logic_vector(31 downto 0); -- data from memory
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variable regsd : std_logic_vector(31 downto 0); -- data from registers
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variable dqm : std_logic_vector(3 downto 0);
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variable raddr : std_logic_vector(12 downto 0);
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variable adec : std_ulogic;
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variable rams : std_logic_vector(1 downto 0);
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variable ba : std_logic_vector(1 downto 0);
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variable haddr : std_logic_vector(31 downto 0);
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variable dout : std_logic_vector(31 downto 0);
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variable hsize : std_logic_vector(1 downto 0);
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variable hwrite : std_ulogic;
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variable htrans : std_logic_vector(1 downto 0);
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variable hready : std_ulogic;
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variable vbdrive : std_logic_vector(31 downto 0);
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variable bdrive : std_ulogic;
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begin
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-- Variable default settings to avoid latches
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v := r; startsd := '0'; v.hresp := HRESP_OKAY; vbdrive := rbdrive;
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v.hrdata(31 downto 0) := sdi.data(31 downto 0);
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v.hwdata := ahbsi.hwdata; v.qdrive :='0';
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if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
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v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
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v.htrans := ahbsi.htrans;
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if ahbsi.htrans(1) = '1' then
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v.hio := ahbsi.hmbsel(1);
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v.hsel := '1'; v.hready := v.hio;
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end if;
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v.haddr := ahbsi.haddr;
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end if;
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if (r.hsel = '1') and (ahbsi.hready = '0') then
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haddr := r.haddr; hsize := r.size;
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htrans := r.htrans; hwrite := r.hwrite;
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else
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haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
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htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
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end if;
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if fast = 1 then haddr := r.haddr; end if;
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if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
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-- generate DQM from address and write size
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case r.size is
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when "00" =>
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case r.haddr(1 downto 0) is
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when "00" => dqm := "0111";
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when "01" => dqm := "1011";
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when "10" => dqm := "1101";
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when others => dqm := "1110";
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end case;
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when "01" =>
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if r.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
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when others => dqm := "0000";
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end case;
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-- main FSM
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case r.mstate is
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when midle =>
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if ((v.hsel and htrans(1) and not v.hio) = '1') then
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if (r.sdstate = sidle) and (r.cfg.command = "000") and
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(r.cmstate = midle) and (v.hio = '0')
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then
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if fast = 0 then startsd := '1'; else v.startsd := '1'; end if;
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v.mstate := active;
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end if;
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end if;
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when others => null;
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end case;
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startsd := startsd or r.startsd;
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-- generate row and column address size
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case r.cfg.csize is
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when "00" => raddr := haddr(21 downto 9);
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when "01" => raddr := haddr(22 downto 10);
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when "10" => raddr := haddr(23 downto 11);
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when others =>
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if r.cfg.bsize = "110" then raddr := haddr(25 downto 13);
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else raddr := haddr(24 downto 12); end if;
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end case;
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-- generate bank address
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ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
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genmux(r.cfg.bsize, haddr(27 downto 20));
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-- generate chip select
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adec := genmux(r.cfg.bsize, haddr(29 downto 22));
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rams := adec & not adec;
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-- sdram access FSM
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if r.trfc /= "000" then v.trfc := r.trfc - 1; end if;
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case r.sdstate is
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when sidle =>
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if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
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and (r.istate = finish)
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then
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v.address(16 downto 2) := ba & raddr;
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v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
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v.startsd := '0';
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end if;
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when act1 =>
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v.rasn := '1'; v.trfc := r.cfg.trfc;
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if r.cfg.casdel = '1' then v.sdstate := act2; else
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v.sdstate := act3;
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v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
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end if;
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when act2 =>
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v.sdstate := act3;
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v.hready := r.hwrite and ahbsi.htrans(0) and ahbsi.htrans(1);
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when act3 =>
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v.casn := '0';
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v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '0';
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v.dqm := dqm; v.burst := r.hready;
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if r.hwrite = '1' then
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v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '0'; v.qdrive := '1';
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266 |
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if ahbsi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
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267 |
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else v.sdstate := rd1; end if;
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268 |
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when wr1 =>
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269 |
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v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
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270 |
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v.address(14 downto 2) := r.haddr(12 downto 11) & '0' & r.haddr(10 downto 2) & '0';
|
271 |
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if (((r.burst and r.hready) = '1') and (r.htrans = "11")) then
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272 |
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v.hready := ahbsi.htrans(0) and ahbsi.htrans(1) and r.hready;
|
273 |
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if (r.hready = '1') and (r.address(4 downto 3) = "11") then
|
274 |
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v.sdwen := '0'; v.casn := '0';
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275 |
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end if;
|
276 |
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else
|
277 |
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v.sdstate := wr2;
|
278 |
|
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v.dqm := (others => '1'); --v.bdrive := '1';
|
279 |
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end if;
|
280 |
|
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when wr2 =>
|
281 |
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v.sdstate := wr3; v.qdrive := '1';
|
282 |
|
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when wr3 =>
|
283 |
|
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v.sdstate := wr4a; v.qdrive := '1';
|
284 |
|
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when wr4a =>
|
285 |
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v.bdrive := '1';
|
286 |
|
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v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
|
287 |
|
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when wr4 =>
|
288 |
|
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v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
|
289 |
|
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v.sdstate := wr5;
|
290 |
|
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when wr5 =>
|
291 |
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v.sdstate := sidle;
|
292 |
|
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when rd1 =>
|
293 |
|
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v.casn := '1'; v.sdstate := rd7;
|
294 |
|
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when rd7 =>
|
295 |
|
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v.sdstate := rd2;
|
296 |
|
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when rd2 =>
|
297 |
|
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v.sdstate := rd3;
|
298 |
|
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if ahbsi.htrans /= "11" then v.rasn := '0'; v.sdwen := '0'; end if;
|
299 |
|
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if v.sdwen = '0' then v.dqm := (others => '1'); end if;
|
300 |
|
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when rd3 =>
|
301 |
|
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v.sdstate := rd4; v.hready := '1'; v.casn := '1';
|
302 |
|
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if r.sdwen = '0' then
|
303 |
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v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
|
304 |
|
|
elsif r.haddr(4 downto 2) = "000" then
|
305 |
|
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v.casn := '0'; v.burst := '1'; v.address(5) := '1';
|
306 |
|
|
end if;
|
307 |
|
|
when rd4 =>
|
308 |
|
|
v.hready := '1'; v.casn := '1';
|
309 |
|
|
if (ahbsi.htrans = "11") and (r.sdcsn /= "11") and
|
310 |
|
|
(r.haddr(3 downto 2) = "11") and (r.burst = '1')
|
311 |
|
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then
|
312 |
|
|
v.burst := '0';
|
313 |
|
|
elsif (ahbsi.htrans /= "11") or (r.sdcsn = "11") or
|
314 |
|
|
(r.haddr(3 downto 2) = "11")
|
315 |
|
|
then
|
316 |
|
|
v.hready := '0'; v.dqm := (others => '1'); v.burst := '0';
|
317 |
|
|
if (r.sdcsn /= "11") then
|
318 |
|
|
if (ahbsi.htrans = "11") and (r.cfg.command(2) = '0') then
|
319 |
|
|
v.sdstate := act3;
|
320 |
|
|
else v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; end if;
|
321 |
|
|
else
|
322 |
|
|
if r.cfg.trp = '1' then v.sdstate := rd6;
|
323 |
|
|
else v.sdstate := sidle; end if;
|
324 |
|
|
end if;
|
325 |
|
|
end if;
|
326 |
|
|
when rd5 =>
|
327 |
|
|
if r.cfg.trp = '1' then
|
328 |
|
|
v.sdstate := rd6;
|
329 |
|
|
else v.sdstate := sidle; end if;
|
330 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
|
331 |
|
|
when rd6 =>
|
332 |
|
|
v.sdstate := sidle; v.dqm := (others => '1');
|
333 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
|
334 |
|
|
when others =>
|
335 |
|
|
v.sdstate := sidle;
|
336 |
|
|
end case;
|
337 |
|
|
|
338 |
|
|
-- sdram commands
|
339 |
|
|
|
340 |
|
|
case r.cmstate is
|
341 |
|
|
when midle =>
|
342 |
|
|
if r.sdstate = sidle then
|
343 |
|
|
case r.cfg.command is
|
344 |
|
|
when CMD_PRE => -- precharge
|
345 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
|
346 |
|
|
v.address(12) := '1'; v.cmstate := active;
|
347 |
|
|
when CMD_REF => -- auto-refresh
|
348 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
349 |
|
|
v.cmstate := active;
|
350 |
|
|
when CMD_EMR => -- load-ext-mode-reg
|
351 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
352 |
|
|
v.sdwen := '0'; v.cmstate := active;
|
353 |
|
|
v.address(16 downto 2) := "010000000000000";
|
354 |
|
|
when CMD_LMR => -- load-mode-reg
|
355 |
|
|
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
|
356 |
|
|
v.sdwen := '0'; v.cmstate := active;
|
357 |
|
|
-- v.address(16 downto 2) := "000000" & r.cfg.dllrst & "0" & "01" & r.cfg.casdel & "0011";
|
358 |
|
|
v.address(16 downto 2) := "000000" & r.cfg.dllrst & "0" & "01" & "00011";
|
359 |
|
|
when others => null;
|
360 |
|
|
end case;
|
361 |
|
|
end if;
|
362 |
|
|
when active =>
|
363 |
|
|
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
|
364 |
|
|
v.sdwen := '1'; v.cfg.command := "000";
|
365 |
|
|
v.cmstate := leadout; v.trfc := r.cfg.trfc;
|
366 |
|
|
when others =>
|
367 |
|
|
if r.trfc = "000" then v.cmstate := midle; end if;
|
368 |
|
|
|
369 |
|
|
end case;
|
370 |
|
|
|
371 |
|
|
-- sdram init
|
372 |
|
|
|
373 |
|
|
case r.istate is
|
374 |
|
|
when iidle =>
|
375 |
|
|
if r.cfg.renable = '1' then
|
376 |
|
|
v.cfg.command := CMD_PRE; v.cfg.cke := '1'; v.cfg.dllrst := '1';
|
377 |
|
|
if r.cfg.cke = '1' then v.istate := pre; end if;
|
378 |
|
|
end if;
|
379 |
|
|
when pre =>
|
380 |
|
|
if r.cfg.command = "000" then
|
381 |
|
|
v.cfg.command := "11" & r.cfg.dllrst;
|
382 |
|
|
if r.cfg.dllrst = '1' then v.istate := emode; else v.istate := lmode; end if;
|
383 |
|
|
end if;
|
384 |
|
|
when emode =>
|
385 |
|
|
if r.cfg.command = "000" then
|
386 |
|
|
v.istate := lmode; v.cfg.command := CMD_LMR;
|
387 |
|
|
end if;
|
388 |
|
|
when lmode =>
|
389 |
|
|
if r.cfg.command = "000" then
|
390 |
|
|
if r.cfg.dllrst = '1' then
|
391 |
|
|
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
|
392 |
|
|
v.cfg.command := CMD_REF; v.istate := ref1;
|
393 |
|
|
end if;
|
394 |
|
|
else
|
395 |
|
|
v.istate := finish; v.cfg.command := CMD_LMR;
|
396 |
|
|
v.cfg.refon := '1'; v.cfg.renable := '0';
|
397 |
|
|
end if;
|
398 |
|
|
end if;
|
399 |
|
|
when ref1 =>
|
400 |
|
|
if r.cfg.command = "000" then
|
401 |
|
|
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
|
402 |
|
|
end if;
|
403 |
|
|
when ref2 =>
|
404 |
|
|
if r.cfg.command = "000" then
|
405 |
|
|
v.cfg.command := CMD_PRE; v.istate := pre;
|
406 |
|
|
end if;
|
407 |
|
|
when others =>
|
408 |
|
|
if r.cfg.renable = '1' then
|
409 |
|
|
v.istate := iidle; v.cfg.dllrst := '1';
|
410 |
|
|
end if;
|
411 |
|
|
end case;
|
412 |
|
|
|
413 |
|
|
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
|
414 |
|
|
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
|
415 |
|
|
end if;
|
416 |
|
|
|
417 |
|
|
if (r.hsel and r.hio and not r.hready) = '1' then v.hready := '1'; end if;
|
418 |
|
|
|
419 |
|
|
-- second part of main fsm
|
420 |
|
|
|
421 |
|
|
case r.mstate is
|
422 |
|
|
when active =>
|
423 |
|
|
if v.hready = '1' then
|
424 |
|
|
v.mstate := midle;
|
425 |
|
|
end if;
|
426 |
|
|
when others => null;
|
427 |
|
|
end case;
|
428 |
|
|
|
429 |
|
|
-- sdram refresh counter
|
430 |
|
|
|
431 |
|
|
if ((r.cfg.refon = '1') and (r.istate = finish)) or
|
432 |
|
|
(r.cfg.dllrst = '1')
|
433 |
|
|
then
|
434 |
|
|
v.refresh := r.refresh - 1;
|
435 |
|
|
if (v.refresh(11) and not r.refresh(11)) = '1' then
|
436 |
|
|
v.refresh := r.cfg.refresh;
|
437 |
|
|
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
|
438 |
|
|
end if;
|
439 |
|
|
end if;
|
440 |
|
|
|
441 |
|
|
-- AHB register access
|
442 |
|
|
|
443 |
|
|
if (r.hsel and r.hio and r.hwrite and r.htrans(1)) = '1' then
|
444 |
|
|
v.cfg.refresh := ahbsi.hwdata(11 downto 0);
|
445 |
|
|
v.cfg.cke := ahbsi.hwdata(15);
|
446 |
|
|
v.cfg.renable := ahbsi.hwdata(16);
|
447 |
|
|
v.cfg.dllrst := ahbsi.hwdata(17);
|
448 |
|
|
v.cfg.command := ahbsi.hwdata(20 downto 18);
|
449 |
|
|
v.cfg.csize := ahbsi.hwdata(22 downto 21);
|
450 |
|
|
v.cfg.bsize := ahbsi.hwdata(25 downto 23);
|
451 |
|
|
v.cfg.casdel := ahbsi.hwdata(26);
|
452 |
|
|
v.cfg.trfc := ahbsi.hwdata(29 downto 27);
|
453 |
|
|
v.cfg.trp := ahbsi.hwdata(30);
|
454 |
|
|
v.cfg.refon := ahbsi.hwdata(31);
|
455 |
|
|
v.refresh := (others => '0');
|
456 |
|
|
end if;
|
457 |
|
|
|
458 |
|
|
regsd := (others => '0');
|
459 |
|
|
regsd(31 downto 15) := r.cfg.refon & r.cfg.trp & r.cfg.trfc &
|
460 |
|
|
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command &
|
461 |
|
|
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
|
462 |
|
|
regsd(11 downto 0) := r.cfg.refresh;
|
463 |
|
|
|
464 |
|
|
if (r.hsel and r.hio) = '1' then dout := regsd;
|
465 |
|
|
else dout := r.hrdata(31 downto 0); end if;
|
466 |
|
|
|
467 |
|
|
v.nbdrive := not v.bdrive;
|
468 |
|
|
|
469 |
|
|
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
|
470 |
|
|
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
|
471 |
|
|
|
472 |
|
|
-- reset
|
473 |
|
|
|
474 |
|
|
if rst = '0' then
|
475 |
|
|
v.sdstate := sidle;
|
476 |
|
|
v.mstate := midle;
|
477 |
|
|
v.istate := finish;
|
478 |
|
|
v.cmstate := midle;
|
479 |
|
|
v.hsel := '0';
|
480 |
|
|
v.cfg.command := "000";
|
481 |
|
|
v.cfg.csize := conv_std_logic_vector(col-8, 2);
|
482 |
|
|
v.cfg.bsize := conv_std_logic_vector(log2(Mbit/32), 3);
|
483 |
|
|
if MHz > 100 then v.cfg.casdel := '1'; else v.cfg.casdel := '0'; end if;
|
484 |
|
|
v.cfg.refon := '0';
|
485 |
|
|
v.cfg.trfc := conv_std_logic_vector(7*MHz/100-2, 3);
|
486 |
|
|
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
|
487 |
|
|
v.refresh := (others => '0');
|
488 |
|
|
if pwron = 1 then v.cfg.renable := '1';
|
489 |
|
|
else v.cfg.renable := '0'; end if;
|
490 |
|
|
if MHz > 100 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
|
491 |
|
|
v.dqm := (others => '1');
|
492 |
|
|
v.sdwen := '1';
|
493 |
|
|
v.rasn := '1';
|
494 |
|
|
v.casn := '1';
|
495 |
|
|
v.hready := '1';
|
496 |
|
|
v.startsd := '0';
|
497 |
|
|
v.cfg.dllrst := '0';
|
498 |
|
|
v.cfg.cke := '0';
|
499 |
|
|
end if;
|
500 |
|
|
|
501 |
|
|
ri <= v;
|
502 |
|
|
ribdrive <= vbdrive;
|
503 |
|
|
|
504 |
|
|
ahbso.hready <= r.hready;
|
505 |
|
|
ahbso.hresp <= r.hresp;
|
506 |
|
|
ahbso.hrdata <= dout;
|
507 |
|
|
ahbso.hcache <= not r.hio;
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
end process;
|
511 |
|
|
|
512 |
|
|
sdo.sdcke <= (others => r.cfg.cke);
|
513 |
|
|
ahbso.hconfig <= hconfig;
|
514 |
|
|
ahbso.hirq <= (others => '0');
|
515 |
|
|
ahbso.hindex <= hindex;
|
516 |
|
|
|
517 |
|
|
regs : process(clk, rst) begin
|
518 |
|
|
if rising_edge(clk) then
|
519 |
|
|
r <= ri; rbdrive <= ribdrive;
|
520 |
|
|
end if;
|
521 |
|
|
if (rst = '0') then
|
522 |
|
|
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
|
523 |
|
|
r.cfg.cke <= '1';
|
524 |
|
|
if oepol = 0 then rbdrive <= (others => '1');
|
525 |
|
|
else rbdrive <= (others => '0'); end if;
|
526 |
|
|
end if;
|
527 |
|
|
end process;
|
528 |
|
|
|
529 |
|
|
sdo.address <= ri.address;
|
530 |
|
|
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
|
531 |
|
|
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
|
532 |
|
|
sdo.vbdrive <= rbdrive;
|
533 |
|
|
sdo.sdcsn <= ri.sdcsn;
|
534 |
|
|
sdo.sdwen <= ri.sdwen;
|
535 |
|
|
sdo.dqm <= "111111111111" & r.dqm;
|
536 |
|
|
sdo.rasn <= ri.rasn;
|
537 |
|
|
sdo.casn <= ri.casn;
|
538 |
|
|
sdo.data(31 downto 0) <= r.hwdata;
|
539 |
|
|
|
540 |
|
|
-- pragma translate_off
|
541 |
|
|
bootmsg : report_version
|
542 |
|
|
generic map ("sdctrl" & tost(hindex) &
|
543 |
|
|
": DDR266 controller rev " & tost(REVISION));
|
544 |
|
|
-- pragma translate_on
|
545 |
|
|
|
546 |
|
|
end;
|
547 |
|
|
|