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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: hs
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-- File: hs.vhd
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-- Author: David Lindh - Gaisler Research
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-- Description: High speed DDR memory interface
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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use grlib.amba.all;
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library gaisler;
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use gaisler.misc.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.allmem.all;
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library gaisler;
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use gaisler.ddrrec.all;
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entity hs is
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generic(
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tech : in integer;
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dqsize : in integer;
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dmsize : in integer;
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strobesize: in integer;
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clkperiod : in integer);
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port (
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rst : in std_ulogic;
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clk0 : in std_ulogic;
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clk90 : in std_ulogic;
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clk180 : in std_ulogic;
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clk270 : in std_ulogic;
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hclk : in std_ulogic;
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hssi : in hs_in_type;
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hsso : out hs_out_type);
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end entity hs;
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architecture rtl of hs is
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type wait_times_row_type is array(7 downto 0) of integer range 0 to 31;
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type wait_times_matrix_type is array(7 downto 0) of wait_times_row_type;
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constant DELAY_15NS : integer := (((15*1000)-1) / (clkperiod*1000))+1;
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constant DELAY_20NS : integer := (((20*1000)-1) / (clkperiod*1000))+1;
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constant DELAY_50NS : integer := (((50*1000)-1) / (clkperiod*1000))+1;
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constant DELAY_75NS : integer := (((75*1000)-1) / (clkperiod*1000))+1;
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constant DELAY_80NS : integer := (((80*1000)-1) / (clkperiod*1000))+1;
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constant DELAY_120NS : integer := (((120*1000)-1) / (clkperiod*1000))+1;
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constant wait_times : wait_times_matrix_type :=
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-- NOP,BST,READ,WRITE,ACT,PRE,RFSH,LMR
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((0, 0, 0, 0, 0, 0, 0, 0),
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(0, 0, 0, 0, 0, 0, 0, 0),
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(0, 0, 0, 2, DELAY_20NS, 10, 10, 10),
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(0, 0, 3, 0, DELAY_20NS, 10, 10, 10),
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(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, DELAY_15NS, DELAY_20NS, DELAY_120NS, 2),
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(0, 0, 0, 1+DELAY_15NS, DELAY_50NS, DELAY_20NS, DELAY_120NS, 2),
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(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2),
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(0, 0, DELAY_20NS, 1+DELAY_15NS+DELAY_20NS, 10, DELAY_20NS, DELAY_120NS, 2));
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--signal cmdr : cmd_reg_type; signal cmdri: cmd_reg_type;
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signal rwr : rw_reg_type; signal rwri : rw_reg_type;
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signal data_out : std_logic_vector((dqsize-1) downto 0);
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signal data_in : std_logic_vector((dqsize-1) downto 0);
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signal strobe_out : std_logic_vector((strobesize-1) downto 0);
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signal mask_out : std_logic_vector((dmsize-1) downto 0);
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signal dq1_i : std_logic_vector((dqsize-1) downto 0);
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signal dq1del_i : std_logic_vector((dqsize-1) downto 0);
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signal dq2_i : std_logic_vector((dqsize-1) downto 0);
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signal dq1_o : std_logic_vector((dqsize-1) downto 0);
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signal dq2_o : std_logic_vector((dqsize-1) downto 0);
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signal dm1_o : std_logic_vector((dmsize-1) downto 0);
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signal dm2_o : std_logic_vector((dmsize-1) downto 0);
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signal dqs1_o, dqs2_o, w_ce, r_ce, vcc, gnd : std_ulogic;
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-- DQS delay control signal
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signal uddcntl : std_ulogic;
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signal lock : std_ulogic;
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signal dqsdel : std_ulogic;
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signal read : std_ulogic;
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signal dqso : std_logic_vector((strobesize-1) downto 0);
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signal ddrclkpol : std_logic_vector((strobesize-1) downto 0);
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signal invrst : std_logic;
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signal clk_90 :std_ulogic;
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begin
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-------------------------------------------------------------------------------
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rwcomb : process(rst, hssi, rwr, dq1_i, dq1del_i, dq2_i)
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variable v : rw_reg_type;
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begin
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v:= rwr;
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v.set_cmd := CMD_NOP;
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v.set_adr := (others => '0');
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v.set_cs := "11";
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v.begin_read := '0';
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v.begin_write := '0';
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-------------------------------------------------------------------------------
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-- Buffer for incoming command
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-------------------------------------------------------------------------------
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case v.cbufstate is
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when no_cmd =>
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v.hs_busy := '0';
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if hssi.cmd_valid = '1' then
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v.next_bl := hssi.bl; v.next_buf := hssi.buf; v.next_cas := hssi.cas;
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v.next_adr := hssi.adr; v.next_cs := hssi.cs; v.next_cmd := hssi.cmd;
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v.next_ml := hssi.ml; v.next_ahb := hssi.ahb;
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v.cbufstate := new_cmd;
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end if;
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when new_cmd =>
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v.hs_busy := '1';
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end case;
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-------------------------------------------------------------------------------
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-- Send commands
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-------------------------------------------------------------------------------
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case v.cmdstate is
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when idle =>
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v.holdcnt := 0;
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if rwr.cbufstate = new_cmd then
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v.rw_cmd := rwr.next_cmd;
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v.rw_bl := rwr.next_bl;
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v.rw_cas := 2 + conv_integer(rwr.next_cas(0))+ conv_integer(rwr.next_cas(1));
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v.set_cmd := rwr.next_cmd;
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v.set_adr := rwr.next_adr;
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v.set_cs := rwr.next_cs;
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v.set_cke := '1';
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v.cbufstate := no_cmd;
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v.cmdstate := hold;
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-- Read command, delay start of Read machine
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if rwr.next_cmd = CMD_READ then
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if rwr.next_cas = "00" then -- cas 2
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v.readwait(5) := '1';
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v.bufwait(5):= rwr.next_buf;
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v.ahbwait(5) := rwr.next_ahb;
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v.blwait(5) := rwr.next_bl;
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v.caswait(5) := rwr.next_cas(0);
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else -- cas 2.5 or 3
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v.readwait(6) := '1';
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v.bufwait(6):= rwr.next_buf;
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v.ahbwait(6) := rwr.next_ahb;
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v.blwait(6) := rwr.next_bl;
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v.caswait(6) := rwr.next_cas(0);
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end if;
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-- Calculate delay until write can begin
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v.r2wholdcnt := rwr.rw_cas + rwr.rw_bl/2 +2;
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-- Write command, immediately start Write machine
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elsif rwr.next_cmd = CMD_WRITE then
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v.writewait(1) := '1';
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v.bufwait(1):= rwr.next_buf;
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v.ahbwait(1) := rwr.next_ahb;
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v.blwait(1) := rwr.next_bl;
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v.mlwait(1) := rwr.next_ml;
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-- Active command, begin count towards ealiest precharge
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elsif rwr.next_cmd = CMD_ACTIVE then
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v.act2precnt := DELAY_50NS-1;
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end if;
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end if;
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-- Wait until next cmd is valid to send
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when hold =>
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v.set_cmd := CMD_NOP;
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v.set_adr := (others => '0');
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v.set_cs := "11";
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-- Some waittimes which isn't constant
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if v.rw_cmd = CMD_READ and rwr.next_cmd = CMD_WRITE then
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v.wait_time := v.rw_cas + v.rw_bl/2;
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elsif v.rw_cmd = CMD_READ or v.rw_cmd = CMD_WRITE then
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v.wait_time := v.rw_bl/2;
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else
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v.wait_time := 0;
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end if;
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-- Calculate total wait time
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if rwr.cbufstate = new_cmd then
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if ((v.holdcnt+2 >= wait_times(conv_integer(rwr.next_cmd))(conv_integer(v.rw_cmd))+ v.wait_time)
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and (v.r2wholdcnt = 0 or rwr.next_cmd /= CMD_WRITE)
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and (v.act2precnt = 0 or rwr.next_cmd /= CMD_PRE)) then
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v.cmdstate := idle;
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end if;
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elsif v.holdcnt >= 4+DELAY_120NS then
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v.cmdstate := idle;
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end if;
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v.holdcnt := v.holdcnt +1;
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end case;
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-- Separate count for time beteen a read and write and between active and precharge
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if v.r2wholdcnt /= 0 then v.r2wholdcnt := v.r2wholdcnt -1; end if;
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if v.act2precnt /= 0 then v.act2precnt := v.act2precnt -1; end if;
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-------------------------------------------------------------------------------
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230 |
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-- Delay cmd data for Read machine during CAS period
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231 |
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-------------------------------------------------------------------------------
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232 |
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if v.readwait(0) = '1' or v.writewait(0) = '1' then
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v.begin_read := v.readwait(0);
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v.begin_write := v.writewait(0);
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v.use_ahb := v.ahbwait(0);
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v.use_buf := v.bufwait(0);
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v.use_bl := v.blwait(0);
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239 |
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if v.writewait(0) = '1' then
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v.use_ml := v.mlwait(0);
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else
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242 |
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v.use_cas := v.caswait(0);
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end if;
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244 |
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end if;
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245 |
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246 |
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v.readwait := '0' & v.readwait(6 downto 1);
|
247 |
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v.writewait := '0' & v.writewait(1);
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248 |
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v.bufwait(5 downto 0) := v.bufwait(6 downto 1);
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249 |
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v.ahbwait := 0 & v.ahbwait(6 downto 1);
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250 |
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v.blwait := 8 & v.blwait(6 downto 1);
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251 |
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v.mlwait := 1 & v.mlwait(1);
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252 |
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v.caswait := '0' & v.caswait(6 downto 1);
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253 |
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254 |
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255 |
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256 |
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-------------------------------------------------------------------------------
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257 |
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-- Send/recieve data
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258 |
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-------------------------------------------------------------------------------
|
259 |
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260 |
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-- Read and Write routines
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261 |
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case v.rwstate is
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262 |
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when idle =>
|
263 |
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v.sync_adr(0) := (v.cur_buf(0)+1) & "00";
|
264 |
|
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v.sync_adr(1) := (v.cur_buf(1)+1) & "00";
|
265 |
|
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v.cmdDone := v.cur_buf;
|
266 |
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v.sync_write:= "00";
|
267 |
|
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v.dq_dqs_oe := '1';
|
268 |
|
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v.dqs1_o := '0';
|
269 |
|
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v.w_ce := '0';
|
270 |
|
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v.r_ce := '1';
|
271 |
|
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v.cnt := 0;
|
272 |
|
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|
273 |
|
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if v.begin_write = '1' then
|
274 |
|
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v.cur_buf(v.use_ahb) := v.use_buf;
|
275 |
|
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v.cur_ahb := v.use_ahb;
|
276 |
|
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v.dq_dqs_oe := '0';
|
277 |
|
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v.w_ce := '1';
|
278 |
|
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v.cnt := v.cnt +2;
|
279 |
|
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if v.use_bl = 2 then
|
280 |
|
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v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
|
281 |
|
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else
|
282 |
|
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v.sync_adr(v.use_ahb) := v.use_buf & "01";
|
283 |
|
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end if;
|
284 |
|
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v.rwstate := w;
|
285 |
|
|
|
286 |
|
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elsif v.begin_read = '1' then
|
287 |
|
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v.cur_buf(v.use_ahb) := v.use_buf;
|
288 |
|
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v.cur_ahb := v.use_ahb;
|
289 |
|
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v.sync_adr(v.use_ahb) := v.use_buf & "00";
|
290 |
|
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v.sync_write(v.use_ahb) := '1';
|
291 |
|
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v.cnt := v.cnt +2;
|
292 |
|
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v.cmdDone(v.use_ahb) := v.use_buf;
|
293 |
|
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if v.use_cas = '0' then -- Cas 2 or 3
|
294 |
|
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v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
|
295 |
|
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else -- Cas 2.5
|
296 |
|
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v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
|
297 |
|
|
end if;
|
298 |
|
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v.rwstate := r;
|
299 |
|
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end if;
|
300 |
|
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|
301 |
|
|
-- Write
|
302 |
|
|
when w =>
|
303 |
|
|
v.dqs1_o := '1';
|
304 |
|
|
v.dq_dqs_oe := '0';
|
305 |
|
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|
306 |
|
|
if v.cnt = v.use_bl then
|
307 |
|
|
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
|
308 |
|
|
if v.begin_write = '0' then -- No new write is following
|
309 |
|
|
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
|
310 |
|
|
v.cnt := 0;
|
311 |
|
|
v.rwstate := idle;
|
312 |
|
|
else -- New write is following
|
313 |
|
|
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
|
314 |
|
|
if v.use_bl = 2 then
|
315 |
|
|
v.sync_adr(v.use_ahb) := (v.use_buf +1) & "00";
|
316 |
|
|
else
|
317 |
|
|
v.sync_adr(v.use_ahb) := v.use_buf & "01";
|
318 |
|
|
end if;
|
319 |
|
|
v.cur_buf(v.use_ahb) := v.use_buf;
|
320 |
|
|
v.cur_ahb := v.use_ahb;
|
321 |
|
|
v.cnt := 2;
|
322 |
|
|
end if;
|
323 |
|
|
else
|
324 |
|
|
v.cnt := v.cnt +2;
|
325 |
|
|
if v.cnt = v.use_bl then
|
326 |
|
|
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
|
327 |
|
|
else
|
328 |
|
|
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb)+1;
|
329 |
|
|
end if;
|
330 |
|
|
end if;
|
331 |
|
|
|
332 |
|
|
-- Read
|
333 |
|
|
when r =>
|
334 |
|
|
v.cmdDone(v.cur_ahb) := v.cur_buf(v.cur_ahb);
|
335 |
|
|
if v.use_cas = '0' then -- Cas 2 or 3
|
336 |
|
|
v.sync_wdata((2*dqsize)-1 downto 0) := dq1_i & dq2_i;
|
337 |
|
|
else -- Cas 2.5
|
338 |
|
|
v.sync_wdata((2*dqsize)-1 downto 0) := dq2_i & dq1del_i;
|
339 |
|
|
end if;
|
340 |
|
|
|
341 |
|
|
if v.cnt = v.use_bl then
|
342 |
|
|
if v.begin_read = '0' then
|
343 |
|
|
v.sync_write := "00";
|
344 |
|
|
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
|
345 |
|
|
v.cnt := 0;
|
346 |
|
|
v.rwstate := idle;
|
347 |
|
|
else
|
348 |
|
|
v.sync_adr(v.cur_ahb) := (v.cur_buf(v.cur_ahb)+1) & "00";
|
349 |
|
|
v.cnt := 2;
|
350 |
|
|
v.cur_ahb := v.use_ahb;
|
351 |
|
|
v.cur_buf(v.use_ahb) := v.use_buf;
|
352 |
|
|
v.sync_adr(v.use_ahb) := v.use_buf & "00";
|
353 |
|
|
if v.use_ahb = 0 then
|
354 |
|
|
v.sync_write := "01";
|
355 |
|
|
else
|
356 |
|
|
v.sync_write := "10";
|
357 |
|
|
end if;
|
358 |
|
|
end if;
|
359 |
|
|
else
|
360 |
|
|
v.cnt := v.cnt +2;
|
361 |
|
|
v.sync_adr(v.cur_ahb) := v.sync_adr(v.cur_ahb) +1;
|
362 |
|
|
end if;
|
363 |
|
|
|
364 |
|
|
end case;
|
365 |
|
|
|
366 |
|
|
-- Calculate and set data mask
|
367 |
|
|
if v.use_ml+1 < v.cnt then
|
368 |
|
|
v.dm1_o := (others => '1');
|
369 |
|
|
v.dm2_o := (others => '1');
|
370 |
|
|
elsif v.use_ml+1 = v.cnt then
|
371 |
|
|
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
|
372 |
|
|
v.dm2_o := (others => '1');
|
373 |
|
|
else
|
374 |
|
|
v.dm1_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+dmsize)-1 downto (2*dqsize));
|
375 |
|
|
v.dm2_o(dmsize-1 downto 0) := hssi.dsramso(v.use_ahb).dataout2((2*dqsize+2*dmsize)-1 downto (2*dqsize+dmsize));
|
376 |
|
|
end if;
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
-------------------------------------------------------------------------------
|
381 |
|
|
-- Register and reset
|
382 |
|
|
|
383 |
|
|
if rst = '0' then
|
384 |
|
|
v.cbufstate := no_cmd;
|
385 |
|
|
v.cmdstate := idle;
|
386 |
|
|
v.rwstate := idle;
|
387 |
|
|
v.cur_buf := (others => (others => '1'));
|
388 |
|
|
v.cur_ahb := 0;
|
389 |
|
|
v.use_bl := 4;
|
390 |
|
|
v.use_ml := 2;
|
391 |
|
|
v.use_buf := (others => '1');
|
392 |
|
|
v.use_cas := '0';
|
393 |
|
|
v.rw_cmd := CMD_NOP;
|
394 |
|
|
v.rw_bl := 4;
|
395 |
|
|
v.rw_cas := 2;
|
396 |
|
|
v.next_bl := 4;
|
397 |
|
|
v.next_ml := 2;
|
398 |
|
|
v.next_buf := (others => '1');
|
399 |
|
|
v.next_cas := "00";
|
400 |
|
|
v.next_adr := (others => '0');
|
401 |
|
|
v.next_cs := "11";
|
402 |
|
|
v.next_cmd := CMD_NOP;
|
403 |
|
|
v.set_cmd := CMD_NOP;
|
404 |
|
|
v.set_adr := (others => '0');
|
405 |
|
|
v.set_cs := "00";
|
406 |
|
|
v.set_cke := '0';
|
407 |
|
|
v.hs_busy := '0';
|
408 |
|
|
v.cmdDone := (others => (others => '1'));
|
409 |
|
|
v.begin_read := '0';
|
410 |
|
|
v.begin_write := '0';
|
411 |
|
|
v.dq_dqs_oe := '1';
|
412 |
|
|
v.w_ce := '0';
|
413 |
|
|
v.r_ce := '0';
|
414 |
|
|
v.cnt := 0;
|
415 |
|
|
v.holdcnt := 0;
|
416 |
|
|
v.r2wholdcnt:= 0;
|
417 |
|
|
v.act2precnt:= 0;
|
418 |
|
|
v.wait_time := 10;
|
419 |
|
|
v.readwait := (others => '0');
|
420 |
|
|
v.writewait := (others => '0');
|
421 |
|
|
v.dm1_o := (others => '1');
|
422 |
|
|
v.dm2_o := (others => '1');
|
423 |
|
|
v.dqs1_o := '0';
|
424 |
|
|
v.sync_adr := (others => (others => '0'));
|
425 |
|
|
v.sync_write := "00";
|
426 |
|
|
v.sync_wdata := (others => '0');
|
427 |
|
|
end if;
|
428 |
|
|
|
429 |
|
|
rwri <= v;
|
430 |
|
|
|
431 |
|
|
-- Combinatiorial outputs
|
432 |
|
|
hsso.hs_busy <= v.hs_busy;
|
433 |
|
|
dqs1_o <= v.dqs1_o;
|
434 |
|
|
dqs2_o <= '0';
|
435 |
|
|
hsso.dsramsi(0).address2 <= v.sync_adr(0);
|
436 |
|
|
hsso.dsramsi(0).write2 <= v.sync_write(0);
|
437 |
|
|
hsso.dsramsi(0).datain2 <= v.sync_wdata;
|
438 |
|
|
hsso.dsramsi(1).address2 <= v.sync_adr(1);
|
439 |
|
|
hsso.dsramsi(1).write2 <= v.sync_write(1);
|
440 |
|
|
hsso.dsramsi(1).datain2 <= v.sync_wdata;
|
441 |
|
|
end process;
|
442 |
|
|
|
443 |
|
|
-------------------------------------------------------------------------------
|
444 |
|
|
-- Clocked processes
|
445 |
|
|
|
446 |
|
|
-- CLK0, Main register
|
447 |
|
|
rwclk : process(clk0)
|
448 |
|
|
begin
|
449 |
|
|
if rising_edge(clk0) then
|
450 |
|
|
rwr <= rwri;
|
451 |
|
|
|
452 |
|
|
-- Registered outputs
|
453 |
|
|
r_ce <= rwri.r_ce;
|
454 |
|
|
w_ce <= rwri.w_ce;
|
455 |
|
|
hsso.cmdDone <= rwri.cmdDone;
|
456 |
|
|
dm1_o <= rwri.dm1_o((dmsize-1) downto 0);
|
457 |
|
|
dm2_o <= rwri.dm2_o((dmsize-1) downto 0);
|
458 |
|
|
|
459 |
|
|
-- Registers
|
460 |
|
|
dq1del_i <= dq1_i;
|
461 |
|
|
dq1_o <= hssi.dsramso(rwri.use_ahb).dataout2(dqsize-1 downto 0);
|
462 |
|
|
dq2_o <= hssi.dsramso(rwri.use_ahb).dataout2((2*dqsize)-1 downto dqsize);
|
463 |
|
|
|
464 |
|
|
end if;
|
465 |
|
|
end process;
|
466 |
|
|
|
467 |
|
|
---- CLK270, Drives output enable signal
|
468 |
|
|
--oeclk : process(rst, clk270)
|
469 |
|
|
-- begin
|
470 |
|
|
-- if rst = '0' then
|
471 |
|
|
-- hsso.ddsi.dq_dqs_oe <= '1';
|
472 |
|
|
-- elsif rising_edge(clk270) then
|
473 |
|
|
-- hsso.ddsi.dq_dqs_oe <= rwri.dq_dqs_oe;
|
474 |
|
|
-- end if;
|
475 |
|
|
-- end process;
|
476 |
|
|
|
477 |
|
|
|
478 |
|
|
-- CLK0, Drives control signals
|
479 |
|
|
cmdclk : process(clk0)
|
480 |
|
|
begin
|
481 |
|
|
if rising_edge(clk0) then
|
482 |
|
|
hsso.ddsi.control <= rwri.set_cmd;
|
483 |
|
|
hsso.ddsi.adr <= rwri.set_adr((adrbits-3) downto 0);
|
484 |
|
|
hsso.ddsi.ba <= rwri.set_adr((adrbits-1) downto (adrbits-2));
|
485 |
|
|
hsso.ddsi.cs <= rwri.set_cs;
|
486 |
|
|
hsso.ddsi.cke <= rwri.set_cke;
|
487 |
|
|
end if;
|
488 |
|
|
end process;
|
489 |
|
|
|
490 |
|
|
vcc <= '1';
|
491 |
|
|
gnd <= '0';
|
492 |
|
|
data_in <= hssi.ddso.dq((dqsize-1) downto 0);
|
493 |
|
|
hsso.ddsi.dq((dqsize-1) downto 0) <= data_out;
|
494 |
|
|
hsso.ddsi.dqs((strobesize-1) downto 0) <= strobe_out;
|
495 |
|
|
hsso.ddsi.dm((dmsize-1) downto 0) <= mask_out;
|
496 |
|
|
|
497 |
|
|
dqot : if dqsize < maxdqsize generate
|
498 |
|
|
hsso.ddsi.dq((maxdqsize-1) downto dqsize) <= (others => '-');
|
499 |
|
|
end generate;
|
500 |
|
|
dqsot : if strobesize < maxstrobesize generate
|
501 |
|
|
hsso.ddsi.dqs((maxstrobesize-1) downto strobesize) <= (others => '-');
|
502 |
|
|
end generate;
|
503 |
|
|
dmot : if dmsize <= maxdmsize generate
|
504 |
|
|
hsso.ddsi.dm((maxdmsize-1) downto dmsize) <= (others => '-');
|
505 |
|
|
end generate;
|
506 |
|
|
|
507 |
|
|
-------------------------------------------------------------------------------
|
508 |
|
|
-- DDR IO registers
|
509 |
|
|
-------------------------------------------------------------------------------
|
510 |
|
|
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
-- Input and Output DQ
|
514 |
|
|
|
515 |
|
|
dqio : for i in 0 to (dqsize-1) generate
|
516 |
|
|
in1 : ddr_ireg generic map( tech => tech)
|
517 |
|
|
port map(
|
518 |
|
|
Q1 => dq1_i(i),
|
519 |
|
|
Q2 => dq2_i(i),
|
520 |
|
|
C1 => clk0,
|
521 |
|
|
C2 => clk180,
|
522 |
|
|
CE => vcc, --r_ce,
|
523 |
|
|
D => data_in(i),
|
524 |
|
|
R => gnd,
|
525 |
|
|
S => gnd);
|
526 |
|
|
|
527 |
|
|
out1 : ddr_oreg
|
528 |
|
|
generic map( tech => tech)
|
529 |
|
|
port map(
|
530 |
|
|
Q => data_out(i),
|
531 |
|
|
C1 => clk180,
|
532 |
|
|
C2 => clk0,
|
533 |
|
|
CE => vcc, --w_ce,
|
534 |
|
|
D1 => dq1_o(i),
|
535 |
|
|
D2 => dq2_o(i),
|
536 |
|
|
R => gnd,
|
537 |
|
|
S => gnd);
|
538 |
|
|
|
539 |
|
|
dq_tri : ddr_oreg generic map(
|
540 |
|
|
tech => tech)
|
541 |
|
|
port map(
|
542 |
|
|
Q => hsso.ddsi.dq_oe(i),
|
543 |
|
|
C1 => clk180,
|
544 |
|
|
C2 => clk0,
|
545 |
|
|
CE => vcc, --w_ce,
|
546 |
|
|
D1 => rwri.dq_dqs_oe,
|
547 |
|
|
D2 => rwri.dq_dqs_oe,
|
548 |
|
|
R => gnd,
|
549 |
|
|
S => gnd);
|
550 |
|
|
|
551 |
|
|
end generate;
|
552 |
|
|
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
-- output DQS
|
556 |
|
|
|
557 |
|
|
dqsio : for i in 0 to (strobesize-1) generate
|
558 |
|
|
dqso : ddr_oreg
|
559 |
|
|
generic map(
|
560 |
|
|
tech => tech)
|
561 |
|
|
port map(
|
562 |
|
|
Q => strobe_out(i),
|
563 |
|
|
C1 => clk270,
|
564 |
|
|
C2 => clk90,
|
565 |
|
|
CE => vcc,
|
566 |
|
|
D1 => dqs1_o,
|
567 |
|
|
D2 => dqs2_o,
|
568 |
|
|
R => gnd,
|
569 |
|
|
S => gnd);
|
570 |
|
|
|
571 |
|
|
dqso_tri : ddr_oreg
|
572 |
|
|
generic map(
|
573 |
|
|
tech => tech)
|
574 |
|
|
port map(
|
575 |
|
|
Q => hsso.ddsi.dqs_oe(i),
|
576 |
|
|
C1 => clk270,
|
577 |
|
|
C2 => clk90,
|
578 |
|
|
CE => vcc, --w_ce,
|
579 |
|
|
D1 => rwri.dq_dqs_oe,
|
580 |
|
|
D2 => rwri.dq_dqs_oe,
|
581 |
|
|
R => gnd,
|
582 |
|
|
S => gnd);
|
583 |
|
|
end generate;
|
584 |
|
|
|
585 |
|
|
|
586 |
|
|
|
587 |
|
|
-- Output DM
|
588 |
|
|
|
589 |
|
|
dmo : for i in 0 to (dmsize-1) generate
|
590 |
|
|
U4 : ddr_oreg
|
591 |
|
|
generic map(
|
592 |
|
|
tech => tech)
|
593 |
|
|
port map(
|
594 |
|
|
Q => mask_out(i),
|
595 |
|
|
C1 => clk180,
|
596 |
|
|
C2 => clk0,
|
597 |
|
|
CE => vcc, --w_ce, --write_ce
|
598 |
|
|
D1 => dm1_o(i),
|
599 |
|
|
D2 => dm2_o(i),
|
600 |
|
|
R => gnd,
|
601 |
|
|
S => gnd);
|
602 |
|
|
end generate;
|
603 |
|
|
|
604 |
|
|
end rtl;
|