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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: acache
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-- File: acache.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Interface module between I/D cache controllers and Amba AHB
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.libiu.all;
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use gaisler.libcache.all;
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use gaisler.leon3.all;
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entity acache is
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generic (
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hindex : integer range 0 to NAHBMST-1 := 0;
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ilinesize : integer range 4 to 8 := 4;
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cached : integer := 0;
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clk2x : integer := 0;
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scantest : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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mcii : in memory_ic_in_type;
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mcio : out memory_ic_out_type;
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mcdi : in memory_dc_in_type;
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mcdo : out memory_dc_out_type;
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ahbi : in ahb_mst_in_type;
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ahbo : out ahb_mst_out_type;
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ahbso : in ahb_slv_out_vector;
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hclken : in std_ulogic
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);
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end;
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architecture rtl of acache is
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-- cache control register type
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type reg_type is record
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bg : std_ulogic; -- bus grant
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bo : std_ulogic; -- bus owner
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ba : std_ulogic; -- bus active
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lb : std_ulogic; -- last burst cycle
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retry : std_ulogic; -- retry/split pending
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werr : std_ulogic; -- write error
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hlocken : std_ulogic; -- ready to perform locked transaction
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lock : std_ulogic; -- keep bus locked during SWAP sequence
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hcache : std_ulogic;
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nbo : std_ulogic;
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nba : std_ulogic;
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end record;
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type reg2_type is record
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reqmsk : std_logic_vector(1 downto 0);
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hclken2 : std_ulogic;
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end record;
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constant hconfig : ahb_config_type := (
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others => zero32);
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constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
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function dec_fixed(scache : std_ulogic;
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haddr : std_logic_vector(3 downto 0); cached : integer) return std_ulogic is
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begin
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if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
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else return(scache); end if;
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end;
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signal r, rin : reg_type;
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signal r2, r2in : reg2_type;
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begin
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comb : process(ahbi, r, rst, mcii, mcdi, hclken, ahbso, r2)
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variable v : reg_type;
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variable v2 : reg2_type;
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variable haddr : std_logic_vector(31 downto 0); -- address bus
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variable htrans : std_logic_vector(1 downto 0); -- transfer type
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variable hwrite : std_ulogic; -- read/write
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variable hlock : std_ulogic; -- bus lock
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variable hsize : std_logic_vector(2 downto 0); -- transfer size
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variable hburst : std_logic_vector(2 downto 0); -- burst type
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variable hwdata : std_logic_vector(31 downto 0); -- write data
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variable hbusreq : std_ulogic; -- bus request
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variable iready, dready : std_ulogic;
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variable igrant, dgrant : std_ulogic;
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variable iretry, dretry : std_ulogic;
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variable ihcache, dhcache, dec_hcache : std_ulogic;
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variable imexc, dmexc, nbo, ireq, dreq : std_ulogic;
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variable su, nb : std_ulogic;
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variable scanen : std_ulogic;
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begin
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-- initialisation
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htrans := HTRANS_IDLE;
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v := r; iready := '0'; v.werr := '0'; v2 := r2;
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dready := '0'; igrant := '0'; dgrant := '0';
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imexc := '0'; dmexc := '0'; hlock := '0'; iretry := '0'; dretry := '0';
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ihcache := '0'; dhcache := '0'; su := '0'; --hcache := ahbi.hcache;
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if ahbi.hready = '1' then v.lb := '0'; end if;
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if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
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-- generate AHB signals
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ireq := mcii.req; dreq := mcdi.req;
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if (clk2x /= 0) then ireq := ireq and r2.reqmsk(1); dreq := dreq and r2.reqmsk(0); end if;
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hbusreq := ireq or dreq;
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-- if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
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hwdata := mcdi.data;
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-- nbo := (dreq and not (r.ba and mcii.req and not r.bo));
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nbo := ((not ireq) or (r.ba and mcdi.req and r.bo));
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-- dont change bus master if we have started driving htrans
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if r.nba = '1' then
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nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
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end if;
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if (r.hlocken or r.retry) = '1' then
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nbo := r.nbo;
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end if;
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if (nbo and mcdi.lock and not r.hlocken) = '1' then htrans := HTRANS_IDLE; end if;
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dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
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if nbo = '0' then
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if mcii.req = '1' then htrans := HTRANS_NONSEQ; end if;
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haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
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su := mcii.su;
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if (ireq and r.ba and not r.bo and not r.retry) = '1' then
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htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
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if (((ilinesize = 4) and haddr(3 downto 2) = "10")
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or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
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then v.lb := '1'; end if;
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end if;
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if mcii.burst = '1' then
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hburst := HBURST_INCR;
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else hburst := HBURST_SINGLE; end if;
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if (ireq and r.bg and ahbi.hready and not r.retry) = '1'
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then igrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
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else
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if mcdi.req = '1' then htrans := HTRANS_NONSEQ; end if;
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haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
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hlock := mcdi.lock;
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if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if;
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if mcdi.burst = '1' then hburst := HBURST_INCR;
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else hburst := HBURST_SINGLE; end if;
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if (dreq and r.ba and r.bo and not r.retry) = '1' then
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htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
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hburst := HBURST_INCR;
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end if;
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if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
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then dgrant := not mcdi.lock or r.hlocken; v.hcache := dec_hcache; end if;
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end if;
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if (hclken = '1') or (clk2x = 0) then
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if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
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then v.retry := not ahbi.hready; else v.retry := '0'; end if;
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end if;
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if r.retry = '1' then htrans := HTRANS_IDLE; end if;
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if r.bo = '0' then
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if r.ba = '1' then
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ihcache := r.hcache;
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if ahbi.hready = '1' then
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case ahbi.hresp is
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when HRESP_OKAY => iready := '1';
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when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
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when others => iready := '1'; imexc := '1';
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end case;
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end if;
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end if;
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else
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if r.ba = '1' then
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dhcache := r.hcache;
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if ahbi.hready = '1' then
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case ahbi.hresp is
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when HRESP_OKAY => dready := '1'; v.lock := mcdi.lock and mcdi.read;
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when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
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when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
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end case;
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end if;
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end if;
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end if;
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if r.lock = '1' then hlock := mcdi.lock; end if;
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if (r.lock and nbo) = '1' then v.lock := '0'; end if;
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-- decode cacheability
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if (nbo = '1') and ((hsize = "011") or ((dec_hcache and mcdi.read and mcdi.cache) = '1')) then
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hsize := "010"; haddr(1 downto 0) := "00";
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end if;
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if ahbi.hready = '1' then
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v.bo := nbo; v.bg := ahbi.hgrant(hindex);
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if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
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v.ba := r.bg;
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else v.ba := '0'; end if;
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v.hlocken := hlock and ahbi.hgrant(hindex);
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if (clk2x /= 0) then v.hlocken := v.hlocken and r2.reqmsk(0); end if;
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end if;
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if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
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v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
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if (clk2x /= 0) then
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v2.hclken2 := hclken;
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if (hclken = '1') then
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v2.reqmsk := mcii.req & mcdi.req;
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if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "11"; end if;
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end if;
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end if;
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-- reset operation
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if rst = '0' then
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v.bg := '0'; v.bo := '0'; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
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v.lock := '0'; v.hlocken := '0'; v2.reqmsk := "00"; v.nba := '0'; v.nbo := '0';
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end if;
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-- drive ports
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ahbo.haddr <= haddr ;
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ahbo.htrans <= htrans;
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ahbo.hbusreq <= hbusreq and not r.lb and not (((r.bo and r.ba) or nb) and r.bg and nbo);
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ahbo.hwdata <= hwdata;
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ahbo.hlock <= hlock and mcdi.read;
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ahbo.hwrite <= hwrite;
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ahbo.hsize <= hsize;
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ahbo.hburst <= hburst;
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ahbo.hprot <= "11" & su & nbo;
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ahbo.hindex <= hindex;
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mcio.grant <= igrant;
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mcio.ready <= iready;
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mcio.mexc <= imexc;
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mcio.retry <= iretry;
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mcio.cache <= ihcache;
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mcdo.grant <= dgrant;
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mcdo.ready <= dready;
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mcdo.mexc <= dmexc;
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mcdo.retry <= dretry;
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mcdo.werr <= r.werr;
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mcdo.cache <= dhcache;
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mcdo.ba <= r.ba;
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mcdo.bg <= r.bg;
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mcio.scanen <= scanen;
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mcdo.scanen <= scanen;
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mcdo.testen <= ahbi.testen;
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mcdo.par <= (others => '0');
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mcio.par <= (others => '0');
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rin <= v; r2in <= v2;
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end process;
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281 |
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mcio.data <= ahbi.hrdata; mcdo.data <= ahbi.hrdata;
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ahbo.hirq <= (others => '0');
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ahbo.hconfig <= hconfig;
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reg : process(clk)
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begin
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if rising_edge(clk) then r <= rin; end if;
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end process;
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reg2gen : if (clk2x /= 0) generate
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reg2 : process(clk)
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begin
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if rising_edge(clk) then r2 <= r2in; end if;
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end process;
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end generate;
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296 |
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297 |
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noreg2gen : if (clk2x = 0) generate
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298 |
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r2.reqmsk <= "00";
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end generate;
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300 |
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end;
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302 |
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