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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: grfpwx
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-- File: grfpwx.vhd
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-- Author: Edvin Catovic - Gaisler Research
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-- Description: GRFPU/GRFPC wrapper and FP register file
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library gaisler;
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use gaisler.leon3.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.netcomp.all;
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entity grfpwx is
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generic (fabtech : integer := 0;
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memtech : integer := 0;
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mul : integer range 0 to 2 := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer range 0 to 2 := 0;
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disas : integer range 0 to 2 := 0;
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netlist : integer := 0;
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index : integer := 0);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi : in fpc_in_type;
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cpo : out fpc_out_type
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);
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end;
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architecture rtl of grfpwx is
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component grfpw
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generic (fabtech : integer := 0;
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memtech : integer := 0;
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mul : integer range 0 to 2 := 0;
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pclow : integer range 0 to 2 := 2;
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dsu : integer range 0 to 1 := 0;
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disas : integer range 0 to 2 := 0;
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index : integer range 0 to 2 := 0
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);
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port (
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rst : in std_ulogic; -- Reset
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clk : in std_ulogic;
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holdn : in std_ulogic; -- pipeline hold
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cpi_flush : in std_ulogic; -- pipeline flush
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cpi_exack : in std_ulogic; -- FP exception acknowledge
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cpi_a_rs1 : in std_logic_vector(4 downto 0);
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cpi_d_pc : in std_logic_vector(31 downto 0);
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cpi_d_inst : in std_logic_vector(31 downto 0);
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cpi_d_cnt : in std_logic_vector(1 downto 0);
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cpi_d_trap : in std_ulogic;
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cpi_d_annul : in std_ulogic;
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cpi_d_pv : in std_ulogic;
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cpi_a_pc : in std_logic_vector(31 downto 0);
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cpi_a_inst : in std_logic_vector(31 downto 0);
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cpi_a_cnt : in std_logic_vector(1 downto 0);
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cpi_a_trap : in std_ulogic;
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cpi_a_annul : in std_ulogic;
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cpi_a_pv : in std_ulogic;
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cpi_e_pc : in std_logic_vector(31 downto 0);
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cpi_e_inst : in std_logic_vector(31 downto 0);
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cpi_e_cnt : in std_logic_vector(1 downto 0);
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cpi_e_trap : in std_ulogic;
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cpi_e_annul : in std_ulogic;
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cpi_e_pv : in std_ulogic;
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cpi_m_pc : in std_logic_vector(31 downto 0);
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cpi_m_inst : in std_logic_vector(31 downto 0);
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cpi_m_cnt : in std_logic_vector(1 downto 0);
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cpi_m_trap : in std_ulogic;
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cpi_m_annul : in std_ulogic;
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cpi_m_pv : in std_ulogic;
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cpi_x_pc : in std_logic_vector(31 downto 0);
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cpi_x_inst : in std_logic_vector(31 downto 0);
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cpi_x_cnt : in std_logic_vector(1 downto 0);
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cpi_x_trap : in std_ulogic;
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cpi_x_annul : in std_ulogic;
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cpi_x_pv : in std_ulogic;
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cpi_lddata : in std_logic_vector(31 downto 0); -- load data
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cpi_dbg_enable : in std_ulogic;
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cpi_dbg_write : in std_ulogic;
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cpi_dbg_fsr : in std_ulogic; -- FSR access
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cpi_dbg_addr : in std_logic_vector(4 downto 0);
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cpi_dbg_data : in std_logic_vector(31 downto 0);
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cpo_data : out std_logic_vector(31 downto 0); -- store data
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cpo_exc : out std_logic; -- FP exception
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cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
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cpo_ccv : out std_ulogic; -- FP condition codes valid
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cpo_ldlock : out std_logic; -- FP pipeline hold
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cpo_holdn : out std_ulogic;
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cpo_dbg_data : out std_logic_vector(31 downto 0);
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rfi1_rd1addr : out std_logic_vector(3 downto 0);
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rfi1_rd2addr : out std_logic_vector(3 downto 0);
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rfi1_wraddr : out std_logic_vector(3 downto 0);
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rfi1_wrdata : out std_logic_vector(31 downto 0);
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rfi1_ren1 : out std_ulogic;
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rfi1_ren2 : out std_ulogic;
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rfi1_wren : out std_ulogic;
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rfi2_rd1addr : out std_logic_vector(3 downto 0);
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rfi2_rd2addr : out std_logic_vector(3 downto 0);
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rfi2_wraddr : out std_logic_vector(3 downto 0);
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rfi2_wrdata : out std_logic_vector(31 downto 0);
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rfi2_ren1 : out std_ulogic;
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rfi2_ren2 : out std_ulogic;
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rfi2_wren : out std_ulogic;
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rfo1_data1 : in std_logic_vector(31 downto 0);
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rfo1_data2 : in std_logic_vector(31 downto 0);
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rfo2_data1 : in std_logic_vector(31 downto 0);
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rfo2_data2 : in std_logic_vector(31 downto 0)
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);
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end component;
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signal rfi1, rfi2 : fp_rf_in_type;
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signal rfo1, rfo2 : fp_rf_out_type;
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begin
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x0 : if netlist = 0 generate
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grfpw0 : grfpw generic map (fabtech, memtech, mul, pclow, dsu, disas, index)
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port map (
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rst ,
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clk ,
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holdn ,
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cpi.flush ,
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cpi.exack ,
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cpi.a_rs1 ,
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cpi.d.pc ,
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cpi.d.inst ,
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cpi.d.cnt ,
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cpi.d.trap ,
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cpi.d.annul ,
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cpi.d.pv ,
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cpi.a.pc ,
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cpi.a.inst ,
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cpi.a.cnt ,
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cpi.a.trap ,
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cpi.a.annul ,
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cpi.a.pv ,
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cpi.e.pc ,
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cpi.e.inst ,
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cpi.e.cnt ,
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cpi.e.trap ,
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cpi.e.annul ,
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cpi.e.pv ,
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cpi.m.pc ,
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cpi.m.inst ,
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cpi.m.cnt ,
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cpi.m.trap ,
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cpi.m.annul ,
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cpi.m.pv ,
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cpi.x.pc ,
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cpi.x.inst ,
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cpi.x.cnt ,
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cpi.x.trap ,
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cpi.x.annul ,
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cpi.x.pv ,
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cpi.lddata ,
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cpi.dbg.enable ,
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cpi.dbg.write ,
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cpi.dbg.fsr ,
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cpi.dbg.addr ,
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cpi.dbg.data ,
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cpo.data ,
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cpo.exc ,
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cpo.cc ,
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cpo.ccv ,
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cpo.ldlock ,
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cpo.holdn ,
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cpo.dbg.data ,
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rfi1.rd1addr ,
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rfi1.rd2addr ,
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rfi1.wraddr ,
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rfi1.wrdata ,
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rfi1.ren1 ,
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rfi1.ren2 ,
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rfi1.wren ,
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rfi2.rd1addr ,
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rfi2.rd2addr ,
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rfi2.wraddr ,
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rfi2.wrdata ,
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rfi2.ren1 ,
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rfi2.ren2 ,
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rfi2.wren ,
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rfo1.data1 ,
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rfo1.data2 ,
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rfo2.data1 ,
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rfo2.data2
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);
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end generate;
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x1 : if netlist = 1 generate
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grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
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port map (
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rst ,
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clk ,
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holdn ,
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cpi.flush ,
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cpi.exack ,
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cpi.a_rs1 ,
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cpi.d.pc ,
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cpi.d.inst ,
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cpi.d.cnt ,
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cpi.d.trap ,
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cpi.d.annul ,
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cpi.d.pv ,
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cpi.a.pc ,
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cpi.a.inst ,
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cpi.a.cnt ,
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cpi.a.trap ,
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cpi.a.annul ,
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cpi.a.pv ,
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cpi.e.pc ,
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cpi.e.inst ,
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cpi.e.cnt ,
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cpi.e.trap ,
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cpi.e.annul ,
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cpi.e.pv ,
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cpi.m.pc ,
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cpi.m.inst ,
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cpi.m.cnt ,
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cpi.m.trap ,
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cpi.m.annul ,
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cpi.m.pv ,
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cpi.x.pc ,
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cpi.x.inst ,
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cpi.x.cnt ,
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cpi.x.trap ,
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cpi.x.annul ,
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cpi.x.pv ,
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cpi.lddata ,
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cpi.dbg.enable ,
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cpi.dbg.write ,
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cpi.dbg.fsr ,
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cpi.dbg.addr ,
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cpi.dbg.data ,
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cpo.data ,
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cpo.exc ,
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cpo.cc ,
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cpo.ccv ,
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cpo.ldlock ,
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cpo.holdn ,
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cpo.dbg.data ,
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rfi1.rd1addr ,
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rfi1.rd2addr ,
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rfi1.wraddr ,
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rfi1.wrdata ,
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rfi1.ren1 ,
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rfi1.ren2 ,
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rfi1.wren ,
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rfi2.rd1addr ,
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rfi2.rd2addr ,
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rfi2.wraddr ,
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rfi2.wrdata ,
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rfi2.ren1 ,
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rfi2.ren2 ,
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rfi2.wren ,
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rfo1.data1 ,
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rfo1.data2 ,
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rfo2.data1 ,
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rfo2.data2
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);
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end generate;
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rf1 : regfile_3p generic map (memtech, 4, 32, 1, 16)
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port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
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| 301 |
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rfi1.rd2addr, rfi1.ren2, rfo1.data2);
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| 302 |
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rf2 : regfile_3p generic map (memtech, 4, 32, 1, 16)
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| 304 |
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port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
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rfi2.rd2addr, rfi2.ren2, rfo2.data2);
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end;
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