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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [leon3/] [grlfpwx.vhd] - Blame information for rev 2

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------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003, Gaisler Research
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-----------------------------------------------------------------------------
-- Entity:      grlfpwx
-- File:        grlfpwx.vhd
-- Author:      Edvin Catovic - Gaisler Research
-- Description: GRFPU LITE / GRFPC wrapper and FP register file
------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
 
entity grlfpwx is
  generic (tech     : integer := 0;
           pclow    : integer range 0 to 2 := 2;
           dsu      : integer range 0 to 1 := 0;
           disas    : integer range 0 to 2 := 0;
           pipe     : integer              := 0;
           netlist  : integer              := 0);
  port (
    rst    : in  std_ulogic;                    -- Reset
    clk    : in  std_ulogic;
    holdn  : in  std_ulogic;                    -- pipeline hold
    cpi    : in  fpc_in_type;
    cpo    : out fpc_out_type
    );
end;
 
architecture rtl of grlfpwx is
 
  signal rfi1, rfi2  : fp_rf_in_type;
  signal rfo1, rfo2  : fp_rf_out_type;
 
  component grlfpw
  generic (tech     : integer := 0;
           pclow    : integer range 0 to 2 := 2;
           dsu      : integer range 0 to 1 := 1;
           disas    : integer range 0 to 2 := 0;
           pipe     : integer range 0 to 2 := 0
           );
  port (
    rst    : in  std_ulogic;                    -- Reset
    clk    : in  std_ulogic;
    holdn  : in  std_ulogic;                    -- pipeline hold
    cpi_flush   : in std_ulogic;                          -- pipeline flush
    cpi_exack           : in std_ulogic;                          -- FP exception acknowledge
    cpi_a_rs1   : in std_logic_vector(4 downto 0);
    cpi_d_pc    : in std_logic_vector(31 downto 0);
    cpi_d_inst  : in std_logic_vector(31 downto 0);
    cpi_d_cnt   : in std_logic_vector(1 downto 0);
    cpi_d_trap  : in std_ulogic;
    cpi_d_annul : in std_ulogic;
    cpi_d_pv    : in std_ulogic;
    cpi_a_pc    : in std_logic_vector(31 downto 0);
    cpi_a_inst  : in std_logic_vector(31 downto 0);
    cpi_a_cnt   : in std_logic_vector(1 downto 0);
    cpi_a_trap  : in std_ulogic;
    cpi_a_annul : in std_ulogic;
    cpi_a_pv    : in std_ulogic;
    cpi_e_pc    : in std_logic_vector(31 downto 0);
    cpi_e_inst  : in std_logic_vector(31 downto 0);
    cpi_e_cnt   : in std_logic_vector(1 downto 0);
    cpi_e_trap  : in std_ulogic;
    cpi_e_annul : in std_ulogic;
    cpi_e_pv    : in std_ulogic;
    cpi_m_pc    : in std_logic_vector(31 downto 0);
    cpi_m_inst  : in std_logic_vector(31 downto 0);
    cpi_m_cnt   : in std_logic_vector(1 downto 0);
    cpi_m_trap  : in std_ulogic;
    cpi_m_annul : in std_ulogic;
    cpi_m_pv    : in std_ulogic;
    cpi_x_pc    : in std_logic_vector(31 downto 0);
    cpi_x_inst  : in std_logic_vector(31 downto 0);
    cpi_x_cnt   : in std_logic_vector(1 downto 0);
    cpi_x_trap  : in std_ulogic;
    cpi_x_annul : in std_ulogic;
    cpi_x_pv    : in std_ulogic;
    cpi_lddata        : in std_logic_vector(31 downto 0);     -- load data
    cpi_dbg_enable : in std_ulogic;
    cpi_dbg_write  : in std_ulogic;
    cpi_dbg_fsr    : in std_ulogic;                            -- FSR access
    cpi_dbg_addr   : in std_logic_vector(4 downto 0);
    cpi_dbg_data   : in std_logic_vector(31 downto 0);
 
    cpo_data          : out std_logic_vector(31 downto 0); -- store data
    cpo_exc             : out std_logic;                         -- FP exception
    cpo_cc           : out std_logic_vector(1 downto 0);  -- FP condition codes
    cpo_ccv            : out std_ulogic;                         -- FP condition codes valid
    cpo_ldlock       : out std_logic;                    -- FP pipeline hold
    cpo_holdn         : out std_ulogic;
    cpo_dbg_data     : out std_logic_vector(31 downto 0);
 
    rfi1_rd1addr        : out std_logic_vector(3 downto 0);
    rfi1_rd2addr        : out std_logic_vector(3 downto 0);
    rfi1_wraddr         : out std_logic_vector(3 downto 0);
    rfi1_wrdata         : out std_logic_vector(31 downto 0);
    rfi1_ren1        : out std_ulogic;
    rfi1_ren2        : out std_ulogic;
    rfi1_wren        : out std_ulogic;
 
    rfi2_rd1addr        : out std_logic_vector(3 downto 0);
    rfi2_rd2addr        : out std_logic_vector(3 downto 0);
    rfi2_wraddr         : out std_logic_vector(3 downto 0);
    rfi2_wrdata         : out std_logic_vector(31 downto 0);
    rfi2_ren1        : out std_ulogic;
    rfi2_ren2        : out std_ulogic;
    rfi2_wren        : out std_ulogic;
 
    rfo1_data1          : in std_logic_vector(31 downto 0);
    rfo1_data2          : in std_logic_vector(31 downto 0);
    rfo2_data1          : in std_logic_vector(31 downto 0);
    rfo2_data2          : in std_logic_vector(31 downto 0)
    );
  end component;
 
begin
 
  x0 : if netlist = 0 generate
   grlfpw0 : grlfpw generic map (tech, pclow, dsu, disas, pipe)
   port map (
    rst          ,
    clk          ,
    holdn        ,
    cpi.flush    ,
    cpi.exack    ,
    cpi.a_rs1    ,
    cpi.d.pc     ,
    cpi.d.inst   ,
    cpi.d.cnt    ,
    cpi.d.trap   ,
    cpi.d.annul  ,
    cpi.d.pv     ,
    cpi.a.pc     ,
    cpi.a.inst   ,
    cpi.a.cnt    ,
    cpi.a.trap   ,
    cpi.a.annul  ,
    cpi.a.pv     ,
    cpi.e.pc     ,
    cpi.e.inst   ,
    cpi.e.cnt    ,
    cpi.e.trap   ,
    cpi.e.annul  ,
    cpi.e.pv     ,
    cpi.m.pc     ,
    cpi.m.inst   ,
    cpi.m.cnt    ,
    cpi.m.trap   ,
    cpi.m.annul  ,
    cpi.m.pv     ,
    cpi.x.pc     ,
    cpi.x.inst   ,
    cpi.x.cnt    ,
    cpi.x.trap   ,
    cpi.x.annul  ,
    cpi.x.pv     ,
    cpi.lddata   ,
    cpi.dbg.enable  ,
    cpi.dbg.write   ,
    cpi.dbg.fsr     ,
    cpi.dbg.addr    ,
    cpi.dbg.data    ,
 
    cpo.data        ,
    cpo.exc         ,
    cpo.cc          ,
    cpo.ccv         ,
    cpo.ldlock      ,
    cpo.holdn       ,
    cpo.dbg.data    ,
 
    rfi1.rd1addr    ,
    rfi1.rd2addr     ,
    rfi1.wraddr      ,
    rfi1.wrdata      ,
    rfi1.ren1        ,
    rfi1.ren2        ,
    rfi1.wren        ,
 
    rfi2.rd1addr     ,
    rfi2.rd2addr     ,
    rfi2.wraddr       ,
    rfi2.wrdata       ,
    rfi2.ren1         ,
    rfi2.ren2         ,
    rfi2.wren         ,
 
    rfo1.data1        ,
    rfo1.data2        ,
    rfo2.data1        ,
    rfo2.data2
    );
  end generate;
 
  x1 : if netlist = 1 generate
   grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)
   port map (
    rst          ,
    clk          ,
    holdn        ,
    cpi.flush    ,
    cpi.exack    ,
    cpi.a_rs1    ,
    cpi.d.pc     ,
    cpi.d.inst   ,
    cpi.d.cnt    ,
    cpi.d.trap   ,
    cpi.d.annul  ,
    cpi.d.pv     ,
    cpi.a.pc     ,
    cpi.a.inst   ,
    cpi.a.cnt    ,
    cpi.a.trap   ,
    cpi.a.annul  ,
    cpi.a.pv     ,
    cpi.e.pc     ,
    cpi.e.inst   ,
    cpi.e.cnt    ,
    cpi.e.trap   ,
    cpi.e.annul  ,
    cpi.e.pv     ,
    cpi.m.pc     ,
    cpi.m.inst   ,
    cpi.m.cnt    ,
    cpi.m.trap   ,
    cpi.m.annul  ,
    cpi.m.pv     ,
    cpi.x.pc     ,
    cpi.x.inst   ,
    cpi.x.cnt    ,
    cpi.x.trap   ,
    cpi.x.annul  ,
    cpi.x.pv     ,
    cpi.lddata   ,
    cpi.dbg.enable  ,
    cpi.dbg.write   ,
    cpi.dbg.fsr     ,
    cpi.dbg.addr    ,
    cpi.dbg.data    ,
 
    cpo.data        ,
    cpo.exc         ,
    cpo.cc          ,
    cpo.ccv         ,
    cpo.ldlock      ,
    cpo.holdn       ,
    cpo.dbg.data    ,
 
    rfi1.rd1addr    ,
    rfi1.rd2addr     ,
    rfi1.wraddr      ,
    rfi1.wrdata      ,
    rfi1.ren1        ,
    rfi1.ren2        ,
    rfi1.wren        ,
 
    rfi2.rd1addr     ,
    rfi2.rd2addr     ,
    rfi2.wraddr       ,
    rfi2.wrdata       ,
    rfi2.ren1         ,
    rfi2.ren2         ,
    rfi2.wren         ,
 
    rfo1.data1        ,
    rfo1.data2        ,
    rfo2.data1        ,
    rfo2.data2
    );
  end generate;
 
 
   rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)
     port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,
               rfi1.rd2addr, rfi1.ren2, rfo1.data2);
 
   rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)
     port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,
               rfi2.rd2addr, rfi2.ren2, rfo2.data2);
 
end;

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Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [leon3/] [grlfpwx.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`------------------------------------------------------------------------------`
2			`-- This file is a part of the GRLIB VHDL IP LIBRARY`
3			`-- Copyright (C) 2003, Gaisler Research`
4			`--`
5			`-- This program is free software; you can redistribute it and/or modify`
6			`-- it under the terms of the GNU General Public License as published by`
7			`-- the Free Software Foundation; either version 2 of the License, or`
8			`-- (at your option) any later version.`
9			`--`
10			`-- This program is distributed in the hope that it will be useful,`
11			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
13			`-- GNU General Public License for more details.`
14			`--`
15			`-- You should have received a copy of the GNU General Public License`
16			`-- along with this program; if not, write to the Free Software`
17			`-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
18			`-----------------------------------------------------------------------------`
19			`-- Entity: grlfpwx`
20			`-- File: grlfpwx.vhd`
21			`-- Author: Edvin Catovic - Gaisler Research`
22			`-- Description: GRFPU LITE / GRFPC wrapper and FP register file`
23			`------------------------------------------------------------------------------`
24
25			`library IEEE;`
26			`use IEEE.std_logic_1164.all;`
27			`library gaisler;`
28			`use gaisler.leon3.all;`
29			`library techmap;`
30			`use techmap.gencomp.all;`
31			`use techmap.netcomp.all;`
32
33			`entity grlfpwx is`
34			`generic (tech : integer := 0;`
35			`pclow : integer range 0 to 2 := 2;`
36			`dsu : integer range 0 to 1 := 0;`
37			`disas : integer range 0 to 2 := 0;`
38			`pipe : integer := 0;`
39			`netlist : integer := 0);`
40			`port (`
41			`rst : in std_ulogic; -- Reset`
42			`clk : in std_ulogic;`
43			`holdn : in std_ulogic; -- pipeline hold`
44			`cpi : in fpc_in_type;`
45			`cpo : out fpc_out_type`
46			`);`
47			`end;`
48
49			`architecture rtl of grlfpwx is`
50
51			`signal rfi1, rfi2 : fp_rf_in_type;`
52			`signal rfo1, rfo2 : fp_rf_out_type;`
53
54			`component grlfpw`
55			`generic (tech : integer := 0;`
56			`pclow : integer range 0 to 2 := 2;`
57			`dsu : integer range 0 to 1 := 1;`
58			`disas : integer range 0 to 2 := 0;`
59			`pipe : integer range 0 to 2 := 0`
60			`);`
61			`port (`
62			`rst : in std_ulogic; -- Reset`
63			`clk : in std_ulogic;`
64			`holdn : in std_ulogic; -- pipeline hold`
65			`cpi_flush : in std_ulogic; -- pipeline flush`
66			`cpi_exack : in std_ulogic; -- FP exception acknowledge`
67			`cpi_a_rs1 : in std_logic_vector(4 downto 0);`
68			`cpi_d_pc : in std_logic_vector(31 downto 0);`
69			`cpi_d_inst : in std_logic_vector(31 downto 0);`
70			`cpi_d_cnt : in std_logic_vector(1 downto 0);`
71			`cpi_d_trap : in std_ulogic;`
72			`cpi_d_annul : in std_ulogic;`
73			`cpi_d_pv : in std_ulogic;`
74			`cpi_a_pc : in std_logic_vector(31 downto 0);`
75			`cpi_a_inst : in std_logic_vector(31 downto 0);`
76			`cpi_a_cnt : in std_logic_vector(1 downto 0);`
77			`cpi_a_trap : in std_ulogic;`
78			`cpi_a_annul : in std_ulogic;`
79			`cpi_a_pv : in std_ulogic;`
80			`cpi_e_pc : in std_logic_vector(31 downto 0);`
81			`cpi_e_inst : in std_logic_vector(31 downto 0);`
82			`cpi_e_cnt : in std_logic_vector(1 downto 0);`
83			`cpi_e_trap : in std_ulogic;`
84			`cpi_e_annul : in std_ulogic;`
85			`cpi_e_pv : in std_ulogic;`
86			`cpi_m_pc : in std_logic_vector(31 downto 0);`
87			`cpi_m_inst : in std_logic_vector(31 downto 0);`
88			`cpi_m_cnt : in std_logic_vector(1 downto 0);`
89			`cpi_m_trap : in std_ulogic;`
90			`cpi_m_annul : in std_ulogic;`
91			`cpi_m_pv : in std_ulogic;`
92			`cpi_x_pc : in std_logic_vector(31 downto 0);`
93			`cpi_x_inst : in std_logic_vector(31 downto 0);`
94			`cpi_x_cnt : in std_logic_vector(1 downto 0);`
95			`cpi_x_trap : in std_ulogic;`
96			`cpi_x_annul : in std_ulogic;`
97			`cpi_x_pv : in std_ulogic;`
98			`cpi_lddata : in std_logic_vector(31 downto 0); -- load data`
99			`cpi_dbg_enable : in std_ulogic;`
100			`cpi_dbg_write : in std_ulogic;`
101			`cpi_dbg_fsr : in std_ulogic; -- FSR access`
102			`cpi_dbg_addr : in std_logic_vector(4 downto 0);`
103			`cpi_dbg_data : in std_logic_vector(31 downto 0);`
104
105			`cpo_data : out std_logic_vector(31 downto 0); -- store data`
106			`cpo_exc : out std_logic; -- FP exception`
107			`cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes`
108			`cpo_ccv : out std_ulogic; -- FP condition codes valid`
109			`cpo_ldlock : out std_logic; -- FP pipeline hold`
110			`cpo_holdn : out std_ulogic;`
111			`cpo_dbg_data : out std_logic_vector(31 downto 0);`
112
113			`rfi1_rd1addr : out std_logic_vector(3 downto 0);`
114			`rfi1_rd2addr : out std_logic_vector(3 downto 0);`
115			`rfi1_wraddr : out std_logic_vector(3 downto 0);`
116			`rfi1_wrdata : out std_logic_vector(31 downto 0);`
117			`rfi1_ren1 : out std_ulogic;`
118			`rfi1_ren2 : out std_ulogic;`
119			`rfi1_wren : out std_ulogic;`
120
121			`rfi2_rd1addr : out std_logic_vector(3 downto 0);`
122			`rfi2_rd2addr : out std_logic_vector(3 downto 0);`
123			`rfi2_wraddr : out std_logic_vector(3 downto 0);`
124			`rfi2_wrdata : out std_logic_vector(31 downto 0);`
125			`rfi2_ren1 : out std_ulogic;`
126			`rfi2_ren2 : out std_ulogic;`
127			`rfi2_wren : out std_ulogic;`
128
129			`rfo1_data1 : in std_logic_vector(31 downto 0);`
130			`rfo1_data2 : in std_logic_vector(31 downto 0);`
131			`rfo2_data1 : in std_logic_vector(31 downto 0);`
132			`rfo2_data2 : in std_logic_vector(31 downto 0)`
133			`);`
134			`end component;`
135
136			`begin`
137
138			`x0 : if netlist = 0 generate`
139			`grlfpw0 : grlfpw generic map (tech, pclow, dsu, disas, pipe)`
140			`port map (`
141			`rst ,`
142			`clk ,`
143			`holdn ,`
144			`cpi.flush ,`
145			`cpi.exack ,`
146			`cpi.a_rs1 ,`
147			`cpi.d.pc ,`
148			`cpi.d.inst ,`
149			`cpi.d.cnt ,`
150			`cpi.d.trap ,`
151			`cpi.d.annul ,`
152			`cpi.d.pv ,`
153			`cpi.a.pc ,`
154			`cpi.a.inst ,`
155			`cpi.a.cnt ,`
156			`cpi.a.trap ,`
157			`cpi.a.annul ,`
158			`cpi.a.pv ,`
159			`cpi.e.pc ,`
160			`cpi.e.inst ,`
161			`cpi.e.cnt ,`
162			`cpi.e.trap ,`
163			`cpi.e.annul ,`
164			`cpi.e.pv ,`
165			`cpi.m.pc ,`
166			`cpi.m.inst ,`
167			`cpi.m.cnt ,`
168			`cpi.m.trap ,`
169			`cpi.m.annul ,`
170			`cpi.m.pv ,`
171			`cpi.x.pc ,`
172			`cpi.x.inst ,`
173			`cpi.x.cnt ,`
174			`cpi.x.trap ,`
175			`cpi.x.annul ,`
176			`cpi.x.pv ,`
177			`cpi.lddata ,`
178			`cpi.dbg.enable ,`
179			`cpi.dbg.write ,`
180			`cpi.dbg.fsr ,`
181			`cpi.dbg.addr ,`
182			`cpi.dbg.data ,`
183
184			`cpo.data ,`
185			`cpo.exc ,`
186			`cpo.cc ,`
187			`cpo.ccv ,`
188			`cpo.ldlock ,`
189			`cpo.holdn ,`
190			`cpo.dbg.data ,`
191
192			`rfi1.rd1addr ,`
193			`rfi1.rd2addr ,`
194			`rfi1.wraddr ,`
195			`rfi1.wrdata ,`
196			`rfi1.ren1 ,`
197			`rfi1.ren2 ,`
198			`rfi1.wren ,`
199
200			`rfi2.rd1addr ,`
201			`rfi2.rd2addr ,`
202			`rfi2.wraddr ,`
203			`rfi2.wrdata ,`
204			`rfi2.ren1 ,`
205			`rfi2.ren2 ,`
206			`rfi2.wren ,`
207
208			`rfo1.data1 ,`
209			`rfo1.data2 ,`
210			`rfo2.data1 ,`
211			`rfo2.data2`
212			`);`
213			`end generate;`
214
215			`x1 : if netlist = 1 generate`
216			`grlfpw0 : grlfpw_net generic map (tech, pclow, dsu, disas, pipe)`
217			`port map (`
218			`rst ,`
219			`clk ,`
220			`holdn ,`
221			`cpi.flush ,`
222			`cpi.exack ,`
223			`cpi.a_rs1 ,`
224			`cpi.d.pc ,`
225			`cpi.d.inst ,`
226			`cpi.d.cnt ,`
227			`cpi.d.trap ,`
228			`cpi.d.annul ,`
229			`cpi.d.pv ,`
230			`cpi.a.pc ,`
231			`cpi.a.inst ,`
232			`cpi.a.cnt ,`
233			`cpi.a.trap ,`
234			`cpi.a.annul ,`
235			`cpi.a.pv ,`
236			`cpi.e.pc ,`
237			`cpi.e.inst ,`
238			`cpi.e.cnt ,`
239			`cpi.e.trap ,`
240			`cpi.e.annul ,`
241			`cpi.e.pv ,`
242			`cpi.m.pc ,`
243			`cpi.m.inst ,`
244			`cpi.m.cnt ,`
245			`cpi.m.trap ,`
246			`cpi.m.annul ,`
247			`cpi.m.pv ,`
248			`cpi.x.pc ,`
249			`cpi.x.inst ,`
250			`cpi.x.cnt ,`
251			`cpi.x.trap ,`
252			`cpi.x.annul ,`
253			`cpi.x.pv ,`
254			`cpi.lddata ,`
255			`cpi.dbg.enable ,`
256			`cpi.dbg.write ,`
257			`cpi.dbg.fsr ,`
258			`cpi.dbg.addr ,`
259			`cpi.dbg.data ,`
260
261			`cpo.data ,`
262			`cpo.exc ,`
263			`cpo.cc ,`
264			`cpo.ccv ,`
265			`cpo.ldlock ,`
266			`cpo.holdn ,`
267			`cpo.dbg.data ,`
268
269			`rfi1.rd1addr ,`
270			`rfi1.rd2addr ,`
271			`rfi1.wraddr ,`
272			`rfi1.wrdata ,`
273			`rfi1.ren1 ,`
274			`rfi1.ren2 ,`
275			`rfi1.wren ,`
276
277			`rfi2.rd1addr ,`
278			`rfi2.rd2addr ,`
279			`rfi2.wraddr ,`
280			`rfi2.wrdata ,`
281			`rfi2.ren1 ,`
282			`rfi2.ren2 ,`
283			`rfi2.wren ,`
284
285			`rfo1.data1 ,`
286			`rfo1.data2 ,`
287			`rfo2.data1 ,`
288			`rfo2.data2`
289			`);`
290			`end generate;`
291
292
293			`rf1 : regfile_3p generic map (tech, 4, 32, 1, 16)`
294			`port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr, rfi1.ren1, rfo1.data1,`
295			`rfi1.rd2addr, rfi1.ren2, rfo1.data2);`
296
297			`rf2 : regfile_3p generic map (tech, 4, 32, 1, 16)`
298			`port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr, rfi2.ren1, rfo2.data1,`
299			`rfi2.rd2addr, rfi2.ren2, rfo2.data2);`
300
301			`end;`