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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: mmutlbcam
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-- File: mmutlbcam.vhd
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-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
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-- Description: MMU TLB logic
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.libiu.all;
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use gaisler.libcache.all;
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use gaisler.leon3.all;
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use gaisler.mmuconfig.all;
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use gaisler.mmuiface.all;
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entity mmutlbcam is
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generic (
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tlb_type : integer range 0 to 3 := 1
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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tlbcami : in mmutlbcam_in_type;
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tlbcamo : out mmutlbcam_out_type
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);
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end mmutlbcam;
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architecture rtl of mmutlbcam is
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constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
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type tlbcam_rtype is record
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btag : tlbcam_reg;
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end record;
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signal r,c : tlbcam_rtype;
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begin
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p0: process (rst, r, tlbcami)
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variable v : tlbcam_rtype;
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variable hm, hf : std_logic;
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variable h_i1, h_i2, h_i3, h_c : std_logic;
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variable h_l2, h_l3 : std_logic;
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variable h_su_cnt : std_logic;
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variable blvl : std_logic_vector(1 downto 0);
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variable bet : std_logic_vector(1 downto 0);
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variable bsu : std_logic;
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variable blvl_decode : std_logic_vector(3 downto 0);
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variable bet_decode : std_logic_vector(3 downto 0);
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variable ref, modified : std_logic;
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variable tlbcamo_pteout : std_logic_vector(31 downto 0);
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variable tlbcamo_LVL : std_logic_vector(1 downto 0);
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variable tlbcamo_NEEDSYNC : std_logic;
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variable tlbcamo_WBNEEDSYNC : std_logic;
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begin
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v := r;
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--#init
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h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
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hm := '0';
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hf := r.btag.VALID;
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blvl := r.btag.LVL;
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bet := r.btag.ET;
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bsu := r.btag.SU;
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bet_decode := decode(bet);
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blvl_decode := decode(blvl);
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ref := r.btag.R;
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modified := r.btag.M;
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tlbcamo_pteout := (others => '0');
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tlbcamo_lvl := (others => '0');
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-- prepare tag comparision
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if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
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if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
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if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
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if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
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-- #level 2 hit (segment)
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h_l2 := h_i1 and h_i2 ;
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-- #level 3 hit (page)
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h_l3 := h_i1 and h_i2 and h_i3;
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-- # context + su
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h_su_cnt := h_c or bsu;
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--# translation (match) op
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case blvl is
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when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
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when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
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when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
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when LVL_CTX => hm := h_c and r.btag.VALID;
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when others => hm := 'X';
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end case;
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--# translation: update ref/mod bit
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tlbcamo_NEEDSYNC := '0';
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if (tlbcami.trans_op and hm ) = '1' then
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v.btag.R := '1';
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v.btag.M := r.btag.M or tlbcami.tagin.M;
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tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
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end if;
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tlbcamo_WBNEEDSYNC := '0';
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if ( hm ) = '1' then
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tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
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end if;
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--# flush operation
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-- tlbcam only stores PTEs, tlb does not store PTDs
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case tlbcami.tagin.TYP is
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when FPTY_PAGE => -- page
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hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
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when FPTY_SEGMENT => -- segment
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hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
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when FPTY_REGION => -- region
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hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
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when FPTY_CTX => -- context
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hf := hf and (h_c and (not bsu));
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when FPTY_N => -- entire
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when others =>
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hf := '0';
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end case;
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--# flush: invalidate on flush hit
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--if (tlbcami.flush_op and hf ) = '1' then
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if (tlbcami.flush_op ) = '1' then
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v.btag.VALID := '0';
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end if;
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--# write op
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if ( tlbcami.write_op = '1' ) then
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v.btag := tlbcami.tagwrite;
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end if;
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--# reset
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if (rst = '0' or tlbcami.mmuen = '0') then
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v.btag.VALID := '0';
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end if;
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tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
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tlbcamo_pteout(PTE_C) := r.btag.C;
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tlbcamo_pteout(PTE_M) := r.btag.M;
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tlbcamo_pteout(PTE_R) := r.btag.R;
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tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
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tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
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tlbcamo_LVL(1 downto 0) := r.btag.LVL;
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--# drive signals
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tlbcamo.pteout <= tlbcamo_pteout;
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tlbcamo.LVL <= tlbcamo_LVL;
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--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
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tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
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tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
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tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
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tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
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tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
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tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
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c <= v;
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end process p0;
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p1: process (clk, c)
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begin if rising_edge(clk) then r <= c; end if;
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end process p1;
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end rtl;
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