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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
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Author |
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dimamali |
mainmenu_option next_comment
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comment '8/32-bit PROM/SRAM controller '
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bool 'Enable 8/32-bit PROM/SRAM controller ' CONFIG_SRCTRL
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if [ "$CONFIG_SRCTRL" = "y" ]; then
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bool '8-bit PROM interface ' CONFIG_SRCTRL_8BIT
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int 'PROM waitstates' CONFIG_SRCTRL_PROMWS 3
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int 'RAM waitstates' CONFIG_SRCTRL_RAMWS 0
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int 'IO waitstates' CONFIG_SRCTRL_IOWS 0
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bool 'Use read-modify-write for sub-word writes ' CONFIG_SRCTRL_RMW
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choice 'SRAM banks' \
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"1 CONFIG_SRCTRL_SRBANKS1 \
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2 CONFIG_SRCTRL_SRBANKS2 \
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3 CONFIG_SRCTRL_SRBANKS3 \
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4 CONFIG_SRCTRL_SRBANKS4 \
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5 CONFIG_SRCTRL_SRBANKS5" 1
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choice 'SRAM bank size (kb) (0 for programmable)' \
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"8 CONFIG_SRCTRL_BANKSZ0 \
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16 CONFIG_SRCTRL_BANKSZ1 \
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32 CONFIG_SRCTRL_BANKSZ2 \
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64 CONFIG_SRCTRL_BANKSZ3 \
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128 CONFIG_SRCTRL_BANKSZ4 \
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256 CONFIG_SRCTRL_BANKSZ5 \
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512 CONFIG_SRCTRL_BANKSZ6 \
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1024 CONFIG_SRCTRL_BANKSZ7 \
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2048 CONFIG_SRCTRL_BANKSZ8 \
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4096 CONFIG_SRCTRL_BANKSZ9 \
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8192 CONFIG_SRCTRL_BANKSZ10 \
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16384 CONFIG_SRCTRL_BANKSZ11 \
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32768 CONFIG_SRCTRL_BANKSZ12 \
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65536 CONFIG_SRCTRL_BANKSZ13" 0
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int 'PROM bank select address bit (0 - 28)' CONFIG_SRCTRL_ROMASEL 19
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fi
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endmenu
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