OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [memctrl/] [ssrctrl.in.help] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
SDRAM controller enable
2
CONFIG_SSCTRL
3
  Say Y here to enabled a 32-bit synchronous SRAM (SSRAM) controller.
4
  The controller is designed for piplined ZBT SSRAM.
5
 
6
CONFIG_SSCTRL_PROM16
7
  Say Y here to enabled a 16-bit PROM support. The PROM should be
8
  connected to D[31:16] of the data bus.
9
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.