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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ahbram
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-- File: ahbram.vhd
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-- Author: Jiri Gaisler - Gaisler Reserch
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-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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entity ahbram is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#fff#;
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tech : integer := DEFMEMTECH;
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kbytes : integer := 1);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end;
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architecture rtl of ahbram is
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constant abits : integer := log2(kbytes) + 8;
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constant hconfig : ahb_config_type := (
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4 => ahb_membar(haddr, '1', '1', hmask),
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others => zero32);
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type reg_type is record
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hwrite : std_ulogic;
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hready : std_ulogic;
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hsel : std_ulogic;
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addr : std_logic_vector(abits+1 downto 0);
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size : std_logic_vector(1 downto 0);
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end record;
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signal r, c : reg_type;
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signal ramsel : std_ulogic;
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signal write : std_logic_vector(3 downto 0);
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signal ramaddr : std_logic_vector(abits-1 downto 0);
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signal ramdata : std_logic_vector(31 downto 0);
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begin
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comb : process (ahbsi, r, rst, ramdata)
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variable bs : std_logic_vector(3 downto 0);
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variable v : reg_type;
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variable haddr : std_logic_vector(abits-1 downto 0);
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begin
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v := r; v.hready := '1'; bs := (others => '0');
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if (r.hwrite or not r.hready) = '1' then haddr := r.addr(abits+1 downto 2);
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else
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haddr := ahbsi.haddr(abits+1 downto 2); bs := (others => '0');
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end if;
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if ahbsi.hready = '1' then
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v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
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v.hwrite := ahbsi.hwrite and v.hsel;
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v.addr := ahbsi.haddr(abits+1 downto 0);
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v.size := ahbsi.hsize(1 downto 0);
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end if;
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if r.hwrite = '1' then
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case r.size(1 downto 0) is
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when "00" => bs (conv_integer(r.addr(1 downto 0))) := '1';
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when "01" => bs := r.addr(1) & r.addr(1) & not (r.addr(1) & r.addr(1));
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when others => bs := (others => '1');
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end case;
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v.hready := not (v.hsel and not ahbsi.hwrite);
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v.hwrite := v.hwrite and v.hready;
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end if;
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if rst = '0' then v.hwrite := '0'; v.hready := '1'; end if;
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write <= bs; ramsel <= v.hsel or r.hwrite; ahbso.hready <= r.hready;
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ramaddr <= haddr; c <= v; ahbso.hrdata <= ramdata;
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end process;
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ahbso.hresp <= "00";
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ahbso.hsplit <= (others => '0');
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ahbso.hirq <= (others => '0');
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ahbso.hcache <= '1';
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ahbso.hconfig <= hconfig;
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ahbso.hindex <= hindex;
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ra : for i in 0 to 3 generate
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aram : syncram generic map (tech, abits, 8) port map (
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clk, ramaddr, ahbsi.hwdata(i*8+7 downto i*8),
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ramdata(i*8+7 downto i*8), ramsel, write(3-i));
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end generate;
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reg : process (clk)
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begin
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if rising_edge(clk ) then r <= c; end if;
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end process;
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-- pragma translate_off
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bootmsg : report_version
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generic map ("ahbram" & tost(hindex) &
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": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
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-- pragma translate_on
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end;
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