Subversion Repositories mips_enhanced

On-chip rom

CONFIG_AHBROM_ENABLE

  Say Y here to add a block on on-chip rom to the AHB bus. The ram

  provides 0-waitstates read access,  burst support, and 8-, 16-

  and 32-bit data size. The rom will be syntheised into block rams

  on Xilinx and Altera FPGA devices, and into gates on ASIC

  technologies. GRLIB includes a utility to automatically create

  the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB

  documentation for details.

On-chip rom address

CONFIG_AHBROM_START

  Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy

  a 1 Mbyte slot at the selected address. Default is 000, corresponding

  to AHB address 0x00000000. When address 0x0 is selected, the rom area

  of any other memory controller is set to 0x10000000 to avoid conflicts.

Enable pipeline register for on-chip rom

CONFIG_AHBROM_PIPE

  Say Y here to add a data pipeline register to the on-chip rom.

  This should be done when the rom is implemenented in (ASIC) gates,

  or in logic cells on FPGAs. Do not use this option when the rom is

  implemented in block rams. If enabled, the rom will operate with

  one waitstate.