OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [misc/] [ahbstat.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
------------------------------------------------------------------------------
2
--  This file is a part of the GRLIB VHDL IP LIBRARY
3
--  Copyright (C) 2003, Gaisler Research
4
--
5
--  This program is free software; you can redistribute it and/or modify
6
--  it under the terms of the GNU General Public License as published by
7
--  the Free Software Foundation; either version 2 of the License, or
8
--  (at your option) any later version.
9
--
10
--  This program is distributed in the hope that it will be useful,
11
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
--  GNU General Public License for more details.
14
--
15
--  You should have received a copy of the GNU General Public License
16
--  along with this program; if not, write to the Free Software
17
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
18
-------------------------------------------------------------------------------
19
 
20
library ieee;
21
library grlib;
22
library gaisler;
23
 
24
use ieee.std_logic_1164.all;
25
use grlib.amba.all;
26
use grlib.stdlib.all;
27
use grlib.devices.all;
28
use gaisler.misc.all;
29
 
30
entity ahbstat is
31
  generic(
32
    pindex : integer := 0;
33
    paddr  : integer := 0;
34
    pmask  : integer := 16#FFF#;
35
    pirq   : integer := 0;
36
    nftslv : integer range 1 to NAHBSLV - 1 := 3);
37
  port(
38
    rst   : in std_ulogic;
39
    clk   : in std_ulogic;
40
    ahbmi : in ahb_mst_in_type;
41
    ahbsi : in ahb_slv_in_type;
42
    stati : in ahbstat_in_type;
43
    apbi  : in apb_slv_in_type;
44
    apbo  : out apb_slv_out_type
45
  );
46
end entity;
47
 
48
architecture rtl of ahbstat is
49
  type reg_type is record
50
    addr    : std_logic_vector(31 downto 0); --failing address
51
    hsize   : std_logic_vector(2 downto 0);  --ahb signals for failing op.
52
    hmaster : std_logic_vector(3 downto 0);
53
    hwrite  : std_ulogic;
54
    hresp   : std_logic_vector(1 downto 0);
55
    newerr  : std_ulogic; --new error detected
56
    cerror  : std_ulogic; --correctable error detected
57
    pirq    : std_ulogic;
58
  end record;
59
 
60
  signal r, rin : reg_type;
61
 
62
  constant VERSION : integer := 0;
63
 
64
  constant pconfig : apb_config_type := (
65
 
66
  1 => apb_iobar(paddr, pmask));
67
 
68
begin
69
 
70
  comb : process(rst, ahbmi, ahbsi, stati, apbi, r) is
71
  variable v       : reg_type;
72
  variable prdata  : std_logic_vector(31 downto 0);
73
  variable vpirq   : std_logic_vector(NAHBIRQ - 1 downto 0);
74
  variable ce      : std_ulogic; --correctable error
75
  begin
76
    v := r; vpirq := (others => '0'); prdata := (others => '0'); v.pirq := '0';
77
 
78
    ce := orv(stati.cerror(0 to nftslv-1));
79
 
80
    case apbi.paddr(2) is
81
    when '0' => --status values
82
      prdata(2 downto 0) := r.hsize;
83
      prdata(6 downto 3) := r.hmaster;
84
      prdata(7) := r.hwrite;
85
      prdata(8) := r.newerr;
86
      prdata(9) := r.cerror;
87
    when others => --failing address
88
      prdata := r.addr;
89
    end case;
90
    --writes. data is written in setup cycle so that r.newerr is updated
91
    --when hready = '1'
92
    if (apbi.psel(pindex) and not apbi.penable and apbi.pwrite) = '1' then
93
      case apbi.paddr(2) is
94
      when '0' =>
95
        v.newerr := apbi.pwdata(8);
96
        v.cerror := apbi.pwdata(9);
97
      when others => null;
98
      end case;
99
    end if;
100
 
101
    v.hresp := ahbmi.hresp;
102
 
103
    if (ahbsi.hready = '1') and  (r.newerr = '0') then
104
      if (r.hresp = HRESP_ERROR) or (ce = '1') then v.newerr := '1';
105
        v.cerror := ce;
106
      else
107
        v.addr := ahbsi.haddr;
108
        v.hsize := ahbsi.hsize;
109
        v.hmaster := ahbsi.hmaster;
110
        v.hwrite := ahbsi.hwrite;
111
      end if;
112
    end if;
113
 
114
    --irq generation
115
    v.pirq := v.newerr and not r.newerr;
116
    vpirq(pirq) := r.pirq;
117
 
118
    --reset
119
    if rst = '0' then
120
      v.newerr := '0'; v.cerror := '0';
121
    end if;
122
 
123
    rin <= v;
124
    apbo.prdata <= prdata;
125
    apbo.pirq <= vpirq;
126
  end process;
127
 
128
  apbo.pconfig <= pconfig;
129
  apbo.pindex <= pindex;
130
 
131
  regs : process(clk) is
132
  begin
133
    if rising_edge(clk) then r <= rin; end if;
134
  end process;
135
 
136
-- boot message
137
 
138
-- pragma translate_off
139
    bootmsg : report_version
140
    generic map ("ahbstat" & tost(pindex) &
141
        ": AHB status unit rev " & tost(VERSION) &
142
        ", irq " & tost(pirq));
143
-- pragma translate_on
144
 
145
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.