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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: gpio
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-- File: gpio.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Scalable general-purpose I/O port
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.misc.all;
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--pragma translate_off
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use std.textio.all;
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--pragma translate_on
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entity grgpio is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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imask : integer := 16#0000#;
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nbits : integer := 16; -- GPIO bits
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oepol : integer := 0; -- Output enable polarity
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syncrst : integer := 0; -- Only synchronous reset
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bypass : integer := 16#0000#;
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scantest : integer := 0;
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bpdir : integer := 16#0000#
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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gpioi : in gpio_in_type;
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gpioo : out gpio_out_type
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);
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end;
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architecture rtl of grgpio is
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constant REVISION : integer := 0;
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constant PIMASK : std_logic_vector(31 downto 0) := '0' & conv_std_logic_vector(imask, 31);
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constant BPMASK : std_logic_vector(31 downto 0) := conv_std_logic_vector(bypass, 32);
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constant BPDIRM : std_logic_vector(31 downto 0) := conv_std_logic_vector(bpdir, 32);
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constant pconfig : apb_config_type := (
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1 => apb_iobar(paddr, pmask));
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type registers is record
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din1 : std_logic_vector(nbits-1 downto 0);
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din2 : std_logic_vector(nbits-1 downto 0);
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dout : std_logic_vector(nbits-1 downto 0);
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imask : std_logic_vector(nbits-1 downto 0);
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level : std_logic_vector(nbits-1 downto 0);
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edge : std_logic_vector(nbits-1 downto 0);
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ilat : std_logic_vector(nbits-1 downto 0);
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dir : std_logic_vector(nbits-1 downto 0);
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bypass : std_logic_vector(nbits-1 downto 0);
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end record;
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signal r, rin : registers;
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signal arst : std_ulogic;
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begin
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arst <= apbi.testrst when (scantest = 1) and (apbi.testen = '1') else rst;
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comb : process(rst, r, apbi, gpioi)
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variable readdata, tmp2, dout, dir, pval, din : std_logic_vector(31 downto 0);
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variable v : registers;
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variable xirq : std_logic_vector(NAHBIRQ-1 downto 0);
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begin
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din := (others => '0');
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din(nbits-1 downto 0) := gpioi.din(nbits-1 downto 0);
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v := r; v.din2 := r.din1; v.din1 := din(nbits-1 downto 0);
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v.ilat := r.din2; dout := (others => '0'); dir := (others => '0');
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dir(nbits-1 downto 0) := r.dir(nbits-1 downto 0);
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if (syncrst = 1) and (rst = '0') then
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if oepol = 0 then dir(nbits-1 downto 0) := (others => '1');
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else dir(nbits-1 downto 0) := (others => '0'); end if;
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end if;
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dout(nbits-1 downto 0) := r.dout(nbits-1 downto 0);
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-- read registers
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readdata := (others => '0');
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case apbi.paddr(4 downto 2) is
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when "000" => readdata(nbits-1 downto 0) := r.din2;
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when "001" => readdata(nbits-1 downto 0) := r.dout;
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when "010" =>
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if oepol = 0 then readdata(nbits-1 downto 0) := not r.dir;
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else readdata(nbits-1 downto 0) := r.dir; end if;
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when "011" =>
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if (imask /= 0) then
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readdata(nbits-1 downto 0) :=
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r.imask(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "100" =>
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if (imask /= 0) then
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readdata(nbits-1 downto 0) :=
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r.level(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "101" =>
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if (imask /= 0) then
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readdata(nbits-1 downto 0) :=
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r.edge(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "110" =>
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if (bypass /= 0) then
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readdata(nbits-1 downto 0) :=
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r.bypass(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
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end if;
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when others =>
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end case;
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-- write registers
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(4 downto 2) is
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when "000" => null;
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when "001" => v.dout := apbi.pwdata(nbits-1 downto 0);
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when "010" =>
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if oepol = 0 then v.dir := not apbi.pwdata(nbits-1 downto 0);
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else v.dir := apbi.pwdata(nbits-1 downto 0); end if;
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when "011" =>
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if (imask /= 0) then
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v.imask := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "100" =>
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if (imask /= 0) then
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v.level := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "101" =>
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if (imask /= 0) then
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v.edge := apbi.pwdata(nbits-1 downto 0) and PIMASK(nbits-1 downto 0);
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end if;
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when "110" =>
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if (bypass /= 0) then
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v.bypass := apbi.pwdata(nbits-1 downto 0) and BPMASK(nbits-1 downto 0);
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end if;
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when others =>
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end case;
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end if;
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-- interrupt filtering and routing
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xirq := (others => '0'); tmp2 := (others => '0');
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if (imask /= 0) then
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tmp2(nbits-1 downto 0) := r.din2;
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for i in 0 to nbits-1 loop
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if (PIMASK(i) and r.imask(i)) = '1' then
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if r.edge(i) = '1' then
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if r.level(i) = '1' then tmp2(i) := r.din2(i) and not r.ilat(i);
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else tmp2(i) := not r.din2(i) and r.ilat(i); end if;
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else tmp2(i) := r.din2(i) xor not r.level(i); end if;
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else
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tmp2(i) := '0';
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end if;
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end loop;
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for i in 0 to nbits-1 loop
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if i > NAHBIRQ-1 then
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exit;
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end if;
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xirq(i) := tmp2(i);
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end loop;
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end if;
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-- drive filtered inputs on the output record
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pval := (others => '0');
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pval(nbits-1 downto 0) := r.din2;
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-- Drive output with gpioi.sig_in for bypassed registers
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if bypass /= 0 then
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for i in 0 to nbits-1 loop
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if r.bypass(i) = '1' then
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dout(i) := gpioi.sig_in(i);
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end if;
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end loop;
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end if;
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-- Drive output with gpioi.sig_in for bypassed registers
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if bpdir /= 0 then
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for i in 0 to nbits-1 loop
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if (BPDIRM(i) and gpioi.sig_en(i)) = '1' then
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dout(i) := gpioi.sig_in(i);
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if oepol = 0 then dir(i) := '0'; else dir(i) := '1'; end if;
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end if;
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end loop;
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end if;
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-- reset operation
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if rst = '0' then
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v.imask := (others => '0'); v.bypass := (others => '0');
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if oepol = 1 then v.dir := (others => '0');
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else v.dir := (others => '1'); end if;
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v.dout := (others => '0');
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end if;
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rin <= v;
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apbo.prdata <= readdata; -- drive apb read bus
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apbo.pirq <= xirq;
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gpioo.dout <= dout;
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gpioo.oen <= dir;
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gpioo.val <= pval;
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-- non filtered input
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gpioo.sig_out <= din;
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end process;
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apbo.pindex <= pindex;
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apbo.pconfig <= pconfig;
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-- registers
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regs : process(clk, arst)
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begin
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if rising_edge(clk) then r <= rin; end if;
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if (syncrst = 0 ) and (arst = '0') then
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if oepol = 1 then r.dir <= (others => '0');
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else r.dir <= (others => '1'); end if;
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end if;
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end process;
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-- boot message
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-- pragma translate_off
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bootmsg : report_version
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generic map ("grgpio" & tost(pindex) &
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": " & tost(nbits) & "-bit GPIO Unit rev " & tost(REVISION));
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-- pragma translate_on
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end;
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