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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Entity: i2cmst
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-- File: i2cmst.vhd
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-- Author: Jan Andersson - Gaisler Research
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-- jan@gaisler.com
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--
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-- Description:
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--
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-- APB interface to OpenCores I2C-master. This is an GRLIB AMBA wrapper
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-- that instantiates the byte- and bit-controller of the OpenCores I2C
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-- master (OC core developed by Richard Herveille, richard@asics.ws).
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-- The OC byte- and bit-controller are located under lib/opencores/i2c
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--
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-- The original master had a WISHBONE interface with registers
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-- aligned at byte boundaries. This wrapper has a slighly different
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-- alignment of the registers:
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--
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-- +------------+--------------------------------------+
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-- | Offset | Bits in word |
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-- | |---------+---------+---------+--------+
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-- | | 31 - 24 | 23 - 16 | 15 - 8 | 7 - 0 |
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-- +------------+---------+---------+---------+--------+
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-- | 0x00 | 0x00 | 0x00 | PRERhi | PRERlo |
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-- | 0x04 | 0x00 | 0x00 | 0x00 | CTR |
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-- | 0x08 | 0x00 | 0x00 | 0x00 | TXR |
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-- | 0x08 | 0x00 | 0x00 | 0x00 | RXR |
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-- | 0x0C | 0x00 | 0x00 | 0x00 | CR |
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-- | 0x0C | 0x00 | 0x00 | 0x00 | SR |
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-- +------------+---------+---------+---------+--------+
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library grlib;
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use grlib.amba.all;
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use grlib.devices.all;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.misc.all;
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library opencores;
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use opencores.i2coc.all;
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entity i2cmst is
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generic (
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-- APB generics
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pindex : integer := 0; -- slave bus index
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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pirq : integer := 0; -- interrupt index
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oepol : integer range 0 to 1 := 0); -- output enable polarity
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port (
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rstn : in std_ulogic;
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clk : in std_ulogic;
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-- APB signals
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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-- I2C signals
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i2ci : in i2c_in_type;
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i2co : out i2c_out_type
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);
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end entity i2cmst;
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architecture rtl of i2cmst is
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-----------------------------------------------------------------------------
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-- Constants
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-----------------------------------------------------------------------------
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constant PCONFIG : apb_config_type := (
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1 => apb_iobar(paddr, pmask));
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constant PRER_addr : std_logic_vector(7 downto 2) := "000000";
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constant CTR_addr : std_logic_vector(7 downto 2) := "000001";
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constant TXR_addr : std_logic_vector(7 downto 2) := "000010";
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constant RXR_addr : std_logic_vector(7 downto 2) := "000010";
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constant CR_addr : std_logic_vector(7 downto 2) := "000011";
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constant SR_addr : std_logic_vector(7 downto 2) := "000011";
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-----------------------------------------------------------------------------
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-- Types
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-----------------------------------------------------------------------------
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-- Register interface
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type ctrl_reg_type is record -- Control register
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en : std_ulogic;
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ien : std_ulogic;
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end record;
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type cmd_reg_type is record -- Command register
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sta : std_ulogic;
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sto : std_ulogic;
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rd : std_ulogic;
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wr : std_ulogic;
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ack : std_ulogic;
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end record;
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type sts_reg_type is record -- Status register
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rxack : std_ulogic;
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busy : std_ulogic;
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al : std_ulogic;
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tip : std_ulogic;
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ifl : std_ulogic;
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end record;
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-- Core registers
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type i2c_reg_type is record
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-- i2c registers
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prer : std_logic_vector(15 downto 0); -- clock prescale register
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ctrl : ctrl_reg_type; -- control register
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txr : std_logic_vector(7 downto 0); -- transmit register
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cmd : cmd_reg_type; -- command register
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sts : sts_reg_type; -- status register
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--
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irq : std_ulogic;
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end record;
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-- Signals to and from byte controller block
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signal rxr : std_logic_vector(7 downto 0); -- Receive register
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signal done : std_logic; -- Signals completion of command
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signal rxack : std_logic; -- Received acknowledge
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signal busy : std_logic; -- I2C core busy
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signal al : std_logic; -- Aribitration lost
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signal irst : std_ulogic; -- Internal, negated reset signal
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signal iscloen : std_ulogic; -- Internal SCL output enable
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signal isdaoen : std_ulogic; -- Internal SDA output enable
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-- Register interface
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signal r, rin : i2c_reg_type;
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signal vcc : std_logic;
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begin
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-- Byte Controller from OpenCores I2C master,
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-- by Richard Herveille (richard@asics.ws). The asynchronous
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-- reset is tied to '1'. Only the synchronous reset is used.
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vcc <= '1';
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byte_ctrl: i2c_master_byte_ctrl
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port map (clk, irst, vcc, r.ctrl.en, r.prer, r.cmd.sta,
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r.cmd.sto, r.cmd.rd, r.cmd.wr, r.cmd.ack, r.txr, done,
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rxack, busy, al, rxr, i2ci.scl, i2co.scl, iscloen,
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i2ci.sda, i2co.sda, isdaoen);
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-- OC I2C logic has active high reset.
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irst <= not rstn;
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-- Fix output enable polarity
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soepol0: if oepol = 0 generate
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i2co.scloen <= iscloen;
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i2co.sdaoen <= isdaoen;
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end generate soepol0;
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soepol1: if oepol /= 0 generate
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i2co.scloen <= not iscloen;
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i2co.sdaoen <= not isdaoen;
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end generate soepol1;
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comb: process (r, rstn, rxr, rxack, busy, al, done, apbi)
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variable v : i2c_reg_type;
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variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
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variable apbaddr : std_logic_vector(7 downto 2);
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variable apbout : std_logic_vector(31 downto 0);
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begin -- process comb
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v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
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apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
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-- Command done or arbitration lost, clear command register
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if (done or al) = '1' then
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v.cmd := ('0', '0', '0', '0', '0');
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end if;
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-- Update status register
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v.sts := (rxack => rxack,
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busy => busy,
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al => al or (r.sts.al and not r.cmd.sta),
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tip => r.cmd.rd or r.cmd.wr,
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ifl => done or al or r.sts.ifl);
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v.irq := (done or al) and r.ctrl.ien;
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-- read registers
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if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
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case apbaddr is
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when PRER_addr =>
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apbout(15 downto 0) := r.prer;
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when CTR_addr =>
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apbout(7 downto 6) := r.ctrl.en & r.ctrl.ien;
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when RXR_addr =>
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apbout(7 downto 0) := rxr;
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when SR_Addr =>
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apbout(7 downto 5) := r.sts.rxack & r.sts.busy & r.sts.al;
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apbout(1 downto 0) := r.sts.tip & r.sts.ifl;
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when others => null;
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end case;
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end if;
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-- write registers
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbaddr is
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when PRER_addr => v.prer := apbi.pwdata(15 downto 0);
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when CTR_addr => v.ctrl.en := apbi.pwdata(7);
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v.ctrl.ien := apbi.pwdata(6);
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when TXR_addr => v.txr := apbi.pwdata(7 downto 0);
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when CR_addr =>
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-- Check that core is enabled and that WR and RD has been cleared
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-- before accepting new command.
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if (r.ctrl.en and not (r.cmd.wr or r.cmd.rd)) = '1' then
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v.cmd.sta := apbi.pwdata(7);
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v.cmd.sto := apbi.pwdata(6);
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v.cmd.rd := apbi.pwdata(5);
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v.cmd.wr := apbi.pwdata(4);
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v.cmd.ack := apbi.pwdata(3);
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end if;
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-- Bit 0 of CR is interrupt acknowledge. The core will only pulse one
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-- interrupt per irq event. Software does not have to clear the
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-- interrupt flag...
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if apbi.pwdata(0) = '1' then
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v.sts.ifl := '0';
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end if;
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when others => null;
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end case;
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end if;
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if rstn = '0' then
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v.prer := (others => '1');
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v.ctrl := ('0', '0');
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v.txr := (others => '0');
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v.cmd := ('0','0','0','0', '0');
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v.sts := ('0','0','0','0', '0');
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end if;
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-- Update registers
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rin <= v;
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-- Update outputs
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apbo.prdata <= apbout;
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apbo.pirq <= irq;
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apbo.pconfig <= PCONFIG;
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apbo.pindex <= pindex;
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end process comb;
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reg: process (clk)
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begin -- process reg
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process reg;
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-- Boot message
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-- pragma translate_off
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bootmsg : report_version
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generic map (
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"i2cmst" & tost(pindex) & ": AMBA Wrapper for OC I2C-master rev " &
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tost(0) & ", irq " & tost(pirq));
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-- pragma translate_on
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end architecture rtl;
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