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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: pcitb_target
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-- File: pcitb_target.vhd
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-- Author: Alf Vaerneus, Gaisler Research
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-- Description: PCI Target emulator.
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------------------------------------------------------------------------------
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-- pragma translate_off
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.pcitb.all;
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use gaisler.pcilib.all;
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use gaisler.ambatest.all;
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library std;
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use std.textio.all;
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entity pcitb_target is
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generic (
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slot : integer := 0;
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abits : integer := 10;
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bars : integer := 1;
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resptime : integer := 2;
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latency : integer := 0;
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rbuf : integer := 8;
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stopwd : boolean := true;
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tval : time := 7 ns;
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conf : config_header_type := config_init;
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dbglevel : integer := 1);
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port (
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-- PCI signals
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pciin : in pci_type;
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pciout : out pci_type;
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-- TB signals
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tbi : in tb_in_type;
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tbo : out tb_out_type
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);
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end pcitb_target;
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architecture tb of pcitb_target is
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constant T_O : integer := 9;
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constant word : std_logic_vector(2 downto 0) := "100";
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type mem_type is array(0 to ((2**abits)-1)) of std_logic_vector(31 downto 0);
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type state_type is(idle,respwait,write,read,latw);
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type reg_type is record
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state : state_type;
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pci : pci_type;
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pcien : std_logic;
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aden : std_logic;
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paren : std_logic;
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erren : std_logic;
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write : std_logic;
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waitcycles : integer;
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latcnt : integer;
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curword : integer;
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first : boolean;
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di : std_logic_vector(31 downto 0);
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ad : std_logic_vector(31 downto 0);
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comm : std_logic_vector(3 downto 0);
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config : config_header_type;
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cbe : std_logic_vector(3 downto 0); -- *** sub-word write
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end record;
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signal r,rin : reg_type;
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signal do : std_logic_vector(31 downto 0);
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procedure writeconf(ad : in std_logic_vector(5 downto 0);
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data : in std_logic_vector(31 downto 0);
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vconfig : out config_header_type) is
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begin
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case conv_integer(ad) is
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-- when 0 => vconfig.devid := data(31 downto 16); vconfig.vendid <= data(15 downto 0);
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when 1 => vconfig.status := data(31 downto 16); vconfig.command := data(15 downto 0);
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when 2 => vconfig.class_code := data(31 downto 8); vconfig.revid := data(7 downto 0);
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when 3 => vconfig.bist := data(31 downto 24); vconfig.header_type := data(23 downto 16);
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vconfig.lat_timer := data(15 downto 8); vconfig.cache_lsize := data(7 downto 0);
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when 4 => vconfig.bar(0) := data;
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when 5 => vconfig.bar(1) := data;
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when 6 => vconfig.bar(2) := data;
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when 7 => vconfig.bar(3) := data;
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when 8 => vconfig.bar(4) := data;
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when 9 => vconfig.bar(5) := data;
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when 10 => vconfig.cis_p := data;
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when 11 => vconfig.subid := data(31 downto 16); vconfig.subvendid := data(15 downto 0);
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when 12 => vconfig.exp_rom_ba := data;
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when 13 => vconfig.max_lat := data(31 downto 24); vconfig.min_gnt := data(23 downto 16);
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vconfig.int_pin := data(15 downto 8); vconfig.int_line := data(7 downto 0);
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when others =>
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end case;
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end procedure;
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procedure readconf(ad : in std_logic_vector(5 downto 0); data : out std_logic_vector(31 downto 0)) is
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begin
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case conv_integer(ad) is
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when 0 => data(31 downto 16) := (conv_std_logic_vector(slot,4) & r.config.devid(11 downto 0));
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data(15 downto 0) := r.config.vendid;
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when 1 => data(31 downto 16) := r.config.status; data(15 downto 0) := r.config.command;
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when 2 => data(31 downto 8) := r.config.class_code; data(7 downto 0) := r.config.revid;
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when 3 => data(31 downto 24) := r.config.bist; data(23 downto 16) := r.config.header_type;
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data(15 downto 8) := r.config.lat_timer; data(7 downto 0) := r.config.cache_lsize;
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when 4 => data := r.config.bar(0)(31 downto abits) & zero32(abits-1 downto 0);
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when 5 => if bars > 1 then data := r.config.bar(1)(31 downto 9) & zero32(8 downto 1) & '1';
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else data := (others => '0'); end if;
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when 6 => if bars > 2 then data := r.config.bar(2)(31 downto abits) & zero32(abits-1 downto 0);
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else data := (others => '0'); end if;
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when 7 => if bars > 3 then data := r.config.bar(3)(31 downto abits) & zero32(abits-1 downto 0);
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else data := (others => '0'); end if;
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when 8 => if bars > 4 then data := r.config.bar(4)(31 downto abits) & zero32(abits-1 downto 0);
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else data := (others => '0'); end if;
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when 9 => if bars > 5 then data := r.config.bar(5)(31 downto abits) & zero32(abits-1 downto 0);
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else data := (others => '0'); end if;
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when 10 => data := r.config.cis_p;
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when 11 => data(31 downto 16) := r.config.subid; data(15 downto 0) := r.config.subvendid;
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when 12 => data := r.config.exp_rom_ba;
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when 13 => data(31 downto 24) := r.config.max_lat; data(23 downto 16) := r.config.min_gnt;
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data(15 downto 8) := r.config.int_pin; data(7 downto 0) := r.config.int_line;
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when others =>
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end case;
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end procedure;
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function pci_hit(ad : std_logic_vector(31 downto 0);
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c : std_logic_vector(3 downto 0);
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idsel : std_logic;
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con : config_header_type) return boolean is
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variable hit : boolean;
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begin
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hit := false;
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if ((c = CONF_READ or c = CONF_WRITE)
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and idsel = '1' and ad(1 downto 0) = "00")
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then hit := true;
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else
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for i in 0 to bars loop
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if i = 1 then
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if ((c = IO_READ or c = IO_WRITE)
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and ad(31 downto abits) = con.bar(i)(31 downto abits))
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then hit := true; end if;
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else
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if ((c = MEM_READ or c = MEM_WRITE or c = MEM_R_MULT or c = MEM_R_LINE or c = MEM_W_INV)
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and ad(31 downto abits) = con.bar(i)(31 downto abits))
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then hit := true; end if;
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end if;
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end loop;
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end if;
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return(hit);
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end function;
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begin
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cont : process
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file readfile,writefile : text;
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variable first : boolean := true;
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variable mem : mem_type;
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variable L : line;
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variable datahex : string(1 to 8);
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variable count : integer;
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begin
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if first then
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for i in 0 to ((2**abits)-1) loop
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mem(i) := (others => '0');
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end loop;
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first := false;
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elsif tbi.start = '1' then
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if tbi.usewfile then
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file_open(writefile, external_name => tbi.wfile(18 downto trimlen(tbi.wfile)), open_kind => write_mode);
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count := conv_integer(tbi.address);
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for i in 0 to tbi.no_words-1 loop
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write(L,printhex(mem(count),32));
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writeline(writefile,L);
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count := count+4;
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end loop;
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file_close(writefile);
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end if;
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elsif r.ad(0) /= 'U' then
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do <= mem(conv_integer(to_x01(r.ad)));
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--if r.write = '1' then mem(conv_integer(to_x01(r.ad))) := r.di; end if; -- *** sub-word write
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if r.write = '1' then
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case r.cbe is
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when "1110" =>
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mem(conv_integer(to_x01(r.ad)))(7 downto 0) := r.di(7 downto 0);
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when "1101" =>
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mem(conv_integer(to_x01(r.ad)))(15 downto 8) := r.di(15 downto 8);
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when "1011" =>
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mem(conv_integer(to_x01(r.ad)))(23 downto 16) := r.di(23 downto 16);
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when "0111" =>
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mem(conv_integer(to_x01(r.ad)))(31 downto 24) := r.di(31 downto 24);
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when "1100" =>
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mem(conv_integer(to_x01(r.ad)))(15 downto 0) := r.di(15 downto 0);
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when "0011" =>
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mem(conv_integer(to_x01(r.ad)))(31 downto 16) := r.di(31 downto 16);
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when others =>
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mem(conv_integer(to_x01(r.ad))) := r.di;
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end case;
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end if;
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end if;
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tbo.ready <= tbi.start;
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wait for 1 ns;
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end process;
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comb : process(pciin, do)
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variable v : reg_type;
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begin
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v := r; v.write := '0';
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v.pci.ad.par := xorv(r.pci.ad.ad & pciin.ad.cbe);
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v.paren := r.aden; v.erren := r.paren;
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case r.state is
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when idle =>
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if (r.pci.ifc.trdy and r.pci.ifc.stop and r.pci.ifc.devsel) = '1' then v.pcien := '1'; end if;
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v.aden := '1'; v.waitcycles := 1; v.latcnt := latency; v.first := true;
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v.pci.ifc.trdy := '1'; v.pci.ifc.stop := '1'; v.curword := 0;
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v.pci.ifc.devsel := '1'; v.pci.err.perr := '1';
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if pciin.ifc.frame = '0' then
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v.comm := pciin.ad.cbe;
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if pci_hit(pciin.ad.ad,pciin.ad.cbe,pciin.ifc.idsel(slot),v.config) then
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v.ad := zero32(31 downto abits) & pciin.ad.ad(abits-1 downto 0);
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if r.waitcycles = resptime then
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v.pci.ifc.devsel := '0'; v.pcien := '0';
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if pciin.ad.cbe(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
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else v.state := read; v.aden := '0'; end if;
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else v.state := respwait; v.waitcycles := r.waitcycles+1; end if;
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end if;
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end if;
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when respwait => -- Initial response time
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if r.waitcycles = resptime then
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v.pci.ifc.devsel := '0'; v.pcien := '0';
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if r.comm(0) = '1' then v.state := write; v.pci.ifc.trdy := '0';
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else v.state := read; v.aden := '0'; end if;
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else v.waitcycles := r.waitcycles+1; end if;
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when write => -- Write access
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if pciin.ifc.irdy = '0' then
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v.curword := r.curword+1;
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if r.comm = CONF_WRITE then writeconf(r.ad(7 downto 2),pciin.ad.ad,v.config);
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--else v.di := pciin.ad.ad; v.write := '1'; end if; -- *** sub-word write
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else v.di := pciin.ad.ad; v.write := '1'; v.cbe := pciin.ad.cbe; end if;
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end if;
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if r.write = '1' then v.ad := r.ad + "100"; end if;
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if pciin.ifc.frame = '1' then
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v.state := idle;
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v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
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elsif (r.latcnt > 0 and pciin.ifc.irdy = '0') then v.state := latw; v.pci.ifc.trdy := '1'; v.latcnt := r.latcnt-1;
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end if;
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when read => -- Read access
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v.pci.ifc.trdy := '0';
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if (pciin.ifc.irdy = '0' or r.first = true) then
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v.ad := r.ad + "100"; v.first := false;
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if r.comm = CONF_READ then readconf(r.ad(7 downto 2),v.pci.ad.ad);
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else v.pci.ad.ad := do; end if;
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end if;
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if (pciin.ifc.trdy or pciin.ifc.irdy) = '0' then v.curword := r.curword+1; end if;
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if (pciin.ifc.frame and not (pciin.ifc.trdy and pciin.ifc.stop)) = '1' then
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v.state := idle; v.aden := '1';
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v.pci.ifc.trdy := '1'; v.pci.ifc.devsel := '1';
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elsif (r.latcnt > 0 and (pciin.ifc.trdy or pciin.ifc.irdy) = '0' and pciin.ifc.stop = '1') then
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v.state := latw; v.latcnt := r.latcnt-1; v.pci.ifc.trdy := '1';
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end if;
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when latw => -- Latency between data phases
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v.pci.ifc.trdy := '1';
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if r.write = '1' then v.ad := r.ad + "100"; end if;
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if (r.latcnt <= 1 and r.comm(0) = '0') then
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v.latcnt := latency;
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v.state := read; v.aden := '0';
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292 |
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elsif r.latcnt = 0 then
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293 |
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v.latcnt := latency;
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294 |
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v.state := write; v.pci.ifc.trdy := '0';
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295 |
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else v.latcnt := r.latcnt-1; end if;
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296 |
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when others =>
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297 |
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end case;
|
298 |
|
|
|
299 |
|
|
-- Disconnect type
|
300 |
|
|
if ((v.curword+1) >= rbuf) then
|
301 |
|
|
if pciin.ifc.frame = '1' then
|
302 |
|
|
v.pci.ifc.stop := '1';
|
303 |
|
|
elsif stopwd then
|
304 |
|
|
if r.pci.ifc.stop = '1' then
|
305 |
|
|
v.pci.ifc.stop := v.pci.ifc.trdy;
|
306 |
|
|
else
|
307 |
|
|
if pciin.ifc.irdy = '0' then v.pci.ifc.trdy := '1'; end if;
|
308 |
|
|
v.pci.ifc.stop := '0';
|
309 |
|
|
end if;
|
310 |
|
|
else
|
311 |
|
|
v.pci.ifc.stop := '0';
|
312 |
|
|
v.pci.ifc.trdy := '1';
|
313 |
|
|
end if;
|
314 |
|
|
end if;
|
315 |
|
|
|
316 |
|
|
if pciin.syst.rst = '0' then
|
317 |
|
|
v.state := idle;
|
318 |
|
|
v.config := conf;
|
319 |
|
|
v.waitcycles := 1;
|
320 |
|
|
v.latcnt := latency;
|
321 |
|
|
v.ad := (others => '0');
|
322 |
|
|
v.di := (others => '0');
|
323 |
|
|
end if;
|
324 |
|
|
|
325 |
|
|
rin <= v;
|
326 |
|
|
|
327 |
|
|
end process;
|
328 |
|
|
|
329 |
|
|
clockreg : process(pciin.syst)
|
330 |
|
|
begin
|
331 |
|
|
if rising_edge(pciin.syst.clk) then
|
332 |
|
|
r <= rin;
|
333 |
|
|
end if;
|
334 |
|
|
end process;
|
335 |
|
|
|
336 |
|
|
pciout.ad.ad <= r.pci.ad.ad after tval when r.aden = '0' else (others => 'Z') after tval;
|
337 |
|
|
pciout.ad.par <= r.pci.ad.par after tval when (r.paren = '0' and (r.pci.ad.par = '1' or r.pci.ad.par = '0')) else 'Z' after tval;
|
338 |
|
|
pciout.ifc.trdy <= r.pci.ifc.trdy after tval when r.pcien = '0' else 'Z' after tval;
|
339 |
|
|
pciout.ifc.stop <= r.pci.ifc.stop after tval when r.pcien = '0' else 'Z' after tval;
|
340 |
|
|
pciout.ifc.devsel <= r.pci.ifc.devsel after tval when r.pcien = '0' else 'Z' after tval;
|
341 |
|
|
pciout.err.perr <= r.pci.err.perr after tval when r.erren = '0' else 'Z' after tval;
|
342 |
|
|
|
343 |
|
|
end;
|
344 |
|
|
|
345 |
|
|
-- pragma translate_on
|