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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ata_device
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-- File: ata_device.vhd
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-- Author: Erik Jagres, Gaisler Research
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-- Description: Simulation of ATA device
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.sim.all;
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--************************ENTITY************************************************
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Entity ata_device is
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generic(sector_length: integer :=512; --in bytes
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disk_size: integer :=32; --in sectors
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log2_size : integer :=14; --Log2(sector_length*disk_size), abits
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Tlr : time := 35 ns
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);
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port(
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--for convinience, not part of ATA interface
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clk : in std_logic;
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rst : in std_logic;
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--interface to host bus adapter
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d : inout std_logic_vector(15 downto 0) := (others=>'Z');
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atai : in ata_in_type := ATAI_RESET_VECTOR;
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atao : out ata_out_type:= ATAO_RESET_VECTOR);
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end;
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--************************ARCHITECTURE******************************************
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Architecture behaveioral of ata_device is
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type mem_reg_type is record
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a : std_logic_vector(9 downto 0); --word adress
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d : std_logic_vector(15 downto 0); --data
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lb : std_logic; --low byte access (active low)
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ub : std_logic; --upper byte access (active low)
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ce : std_logic; --chip enable (active low)
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we : std_logic; --write enable (active low)
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oe : std_logic; --output enable (active low)
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end record;
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constant MEM_RESET_VECTOR : mem_reg_type := ((others=>'0'),
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(others=>'0'),'1','1','1','1','1');
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constant CS1 : integer := 4;
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constant CS0 : integer := 3;
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--status bits
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constant BSY : integer := 7;
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constant DRQ : integer := 3;
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--control bits
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constant NIEN : integer := 1;
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--commands
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constant READ : std_logic_vector(7 downto 0):=X"20";
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constant WRITE : std_logic_vector(7 downto 0):=X"30";
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constant WRITE_DMA : std_logic_vector(7 downto 0):=X"CA";
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constant READ_DMA : std_logic_vector(7 downto 0):=X"C8";
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constant ALTSTAT : std_logic_vector(4 downto 0):="10110";
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constant CMD : std_logic_vector(4 downto 0):="01111";
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constant CHR : std_logic_vector(4 downto 0):="01101";
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constant CLR : std_logic_vector(4 downto 0):="01100";
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constant DTAR : std_logic_vector(4 downto 0):="01000";
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constant DTAP : std_logic_vector(4 downto 0):="00000"; --only CSx used
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constant CTRL : std_logic_vector(4 downto 0):="10110";
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constant DHR : std_logic_vector(4 downto 0):="01110";
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constant ERR : std_logic_vector(4 downto 0):="01001"; --read only
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constant FEAT : std_logic_vector(4 downto 0):=ERR; --write only
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constant SCR : std_logic_vector(4 downto 0):="01010";
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constant SNR : std_logic_vector(4 downto 0):="01011";
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constant STAT : std_logic_vector(4 downto 0):="01111";
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constant sramfile : string := "disk.srec"; -- ram contents
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constant w_adr: integer := log2(sector_length)-1; --word adress bits (within sector)
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type ram_type is record
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a : std_logic_vector(log2_size-2 downto 0);
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ce : std_logic;
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we : std_ulogic;
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oe : std_ulogic;
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end record;
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constant RAM_RESET_VECTOR : ram_type := ((others=>'0'),'0','0','0');
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type ata_reg_type is record --ATA task file
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altstat : std_logic_vector(7 downto 0); --Alternate Status register
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cmd : std_logic_vector(7 downto 0); --Command register
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chr : std_logic_vector(7 downto 0); --Cylinder High register
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clr : std_logic_vector(7 downto 0); --Cylinder Low register
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dtar : std_logic_vector(15 downto 0); --Data register
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dtap : std_logic_vector(15 downto 0); --Data port
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ctrl : std_logic_vector(7 downto 0); --Device Control register
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dhr : std_logic_vector(7 downto 0); --Device/Head register
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err : std_logic_vector(7 downto 0); --Error register
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feat : std_logic_vector(7 downto 0); --Features register
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scr : std_logic_vector(7 downto 0); --Sector Count register
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snr : std_logic_vector(7 downto 0); --Sector Number register
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stat : std_logic_vector(7 downto 0); --Status register
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end record;
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constant ATA_RESET_VECTOR : ata_reg_type := ((others=>'0'),
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(others=>'0'),(others=>'0'),
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(others=>'0'),(others=>'0'),
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(others=>'0'),(others=>'0'),
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(others=>'0'),(others=>'0'),
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(others=>'0'),(others=>'0'),
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(others=>'0'),(others=>'0'));
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type reg_type is record
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cmd_started : boolean;
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dtap_written : boolean;
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dtar_written : boolean;
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dtap_read : boolean;
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dtar_read : boolean;
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firstadr : boolean;
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dior : std_logic;
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diow : std_logic;
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regadr : std_logic_vector(4 downto 0);
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byte_cnt : integer;
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offset : integer;
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intrq : boolean;
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pio_started : boolean;
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tf : ata_reg_type;
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ram : ram_type;
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ram_dta : std_logic_vector(15 downto 0);
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scr : std_logic_vector(7 downto 0);
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end record;
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constant REG_RESET_VECTOR : reg_type := (false,false,false,false,false,true,
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'1','1',(others=>'0'),0,0,false,false,ATA_RESET_VECTOR,RAM_RESET_VECTOR,
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(others=>'0'),(others=>'0'));
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signal r,ri : reg_type := REG_RESET_VECTOR;
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signal s_d : std_logic_vector(15 downto 0) := (others=>'0');
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begin
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comb: process(atai,r,s_d,rst)
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variable v : reg_type:= REG_RESET_VECTOR;
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begin
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if (rst='0') then
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v:=REG_RESET_VECTOR;
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d<=(others=>'Z');
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atao.intrq<='0';
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atao.dmarq<='0';
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else
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v:=r;
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v.dior:=atai.dior; v.diow:=atai.diow;
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v.regadr(CS1):=not(atai.cs(1)); v.regadr(CS0):=not(atai.cs(0)); --CS active l
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v.regadr(2 downto 0):=atai.da(2 downto 0);
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--fix for adressing dtap
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if (v.regadr(4 downto 3)="00") then
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v.regadr(2 downto 0):="000";
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end if;
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--*********************************READ/WRITE registers*****************
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if (atai.dior='1' and atai.diow='1' and r.diow='0') then --write register
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case v.regadr is
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when CMD => v.tf.cmd:=d(7 downto 0);
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v.cmd_started:=true;
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v.tf.stat(BSY):='1';
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v.tf.feat:="00001111";
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v.byte_cnt:=0;
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atao.dmarq<='0'; -----------------------------------erik 2006-10-17
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when CHR => v.tf.chr:=d(7 downto 0);
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when CLR => v.tf.clr:=d(7 downto 0);
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when DTAR => v.tf.dtar:=d(15 downto 0);
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v.dtar_written:=true;
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when CTRL => v.tf.ctrl:=d(7 downto 0);
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when DHR => v.tf.dhr:=d(7 downto 0);
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when FEAT => v.tf.feat:=d(7 downto 0);
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when SCR => v.tf.scr:=d(7 downto 0); v.scr:=d(7 downto 0);
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when SNR => v.tf.snr:=d(7 downto 0);
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when DTAP => v.tf.dtap:=d(15 downto 0);
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v.dtap_written:=true;
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when others => v.tf.stat:=d(7 downto 0);
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end case;
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elsif (atai.dior='0' and r.dior='1' and atai.diow='1') then --read register
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case v.regadr is
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when ALTSTAT => d(7 downto 0)<=r.tf.altstat; d(15 downto 8)<="00000000";
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when CHR => d(7 downto 0)<=r.tf.chr; d(15 downto 8)<="00000000";
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when CLR => d(7 downto 0)<=r.tf.clr; d(15 downto 8)<="00000000";
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when DTAR => d<=r.tf.dtar; v.dtar_read:=true;
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when DHR => d(7 downto 0)<=r.tf.dhr; d(15 downto 8)<="00000000";
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when ERR => d(7 downto 0)<=r.tf.err; d(15 downto 8)<="00000000";
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when SCR => d(7 downto 0)<=r.tf.scr; d(15 downto 8)<="00000000";
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when SNR => d(7 downto 0)<=r.tf.snr; d(15 downto 8)<="00000000";
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when STAT => d(7 downto 0)<=r.tf.stat; d(15 downto 8)<="00000000";
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atao.intrq<='0'; v.intrq:=false;
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when DTAP =>
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d<=r.tf.dtap; v.dtap_read:=true;
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if (v.byte_cnt+2=sector_length) then
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atao.dmarq<='0' after Tlr;
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end if;
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when others => d(15 downto 0)<=(others=>'Z');
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end case;
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--*********************************READ/WRITE registers end*************
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else
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if (r.tf.stat(BSY)='1') then --simulate busy, "borrow" feat reg
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v.tf.feat:=v.tf.feat-1; --count down timer
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if (v.tf.feat="00000000") then
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v.tf.stat(BSY):='0'; --clear busy flag
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end if;
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elsif(v.cmd_started) then
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case r.tf.cmd is
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--********************************************************************
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when WRITE_DMA =>
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atao.dmarq<='1';
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v.tf.stat(DRQ):='1';
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if v.dtap_written then
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v.dtap_written:=false;
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v.byte_cnt:=v.byte_cnt+2;
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if(v.byte_cnt=sector_length) then
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v.tf.scr:=v.tf.scr-1;
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v.byte_cnt:=0;
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if v.tf.scr=X"00" then
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atao.dmarq<='0';
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v.tf.stat(DRQ):='0';
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v.cmd_started:=false;
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if v.tf.ctrl(NIEN)='0' then
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atao.intrq<='1';
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end if;
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end if;
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end if;
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if r.dtap_written then
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v.ram.a(log2_size-2 downto log2(sector_length)-1):=
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r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
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v.ram.a(log2(sector_length)-2 downto 0):=
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conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
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v.ram_dta:=v.tf.dtap; v.ram.oe:='1'; v.ram.ce:='0';v.ram.we:='0';
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end if;
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end if;
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--********************************************************************
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when WRITE =>
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if (not v.pio_started and v.tf.ctrl(NIEN)='0') then
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atao.intrq<='1'; v.pio_started:=true; v.intrq:=true;
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elsif not v.intrq then
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v.tf.stat(DRQ):='1';
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if v.dtar_written then
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v.dtar_written:=false;
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v.byte_cnt:=v.byte_cnt+2;
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if(v.byte_cnt=sector_length) then
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v.tf.scr:=v.tf.scr-1;
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if (v.tf.scr=X"00") then
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v.cmd_started:=false; v.pio_started:=false;
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end if;
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v.byte_cnt:=0;
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v.tf.stat(DRQ):='0';
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v.tf.stat(BSY):='1';
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v.tf.feat:="00001111";
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if v.tf.ctrl(NIEN)='0' then
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atao.intrq<='1';
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end if;
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end if;
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end if;
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if r.dtar_written then
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v.ram.a(log2_size-2 downto log2(sector_length)-1):=
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r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
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v.ram.a(log2(sector_length)-2 downto 0):=
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conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
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v.ram_dta:=v.tf.dtar; v.ram.oe:='1'; v.ram.ce:='0';v.ram.we:='0';
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end if;
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end if;
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--********************************************************************
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295 |
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when READ_DMA =>
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-- atao.dmarq<='1';
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v.tf.stat(DRQ):='1';
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if not (v.byte_cnt+2=sector_length) then
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atao.dmarq<='1';
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end if;
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if v.dtap_read and r.dior='0' and atai.dior='1' then --rising dior detect
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v.dtap_read:=false;
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v.byte_cnt:=v.byte_cnt+2;
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if(v.byte_cnt=sector_length) then
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v.tf.scr:=v.tf.scr-1;
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v.byte_cnt:=0;
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307 |
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if v.tf.scr=X"00" then
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308 |
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-- atao.dmarq<='0';
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309 |
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v.tf.stat(DRQ):='0';
|
310 |
|
|
v.cmd_started:=false;
|
311 |
|
|
v.ram.oe:='1'; v.ram.ce:='1';v.ram.we:='1';
|
312 |
|
|
if v.tf.ctrl(NIEN)='0' then
|
313 |
|
|
atao.intrq<='1';
|
314 |
|
|
end if;
|
315 |
|
|
end if;
|
316 |
|
|
end if;
|
317 |
|
|
end if;
|
318 |
|
|
v.ram.oe:='0'; v.ram.ce:='0';v.ram.we:='1'; v.tf.dtap:=s_d;
|
319 |
|
|
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
|
320 |
|
|
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
|
321 |
|
|
v.ram.a(log2(sector_length)-2 downto 0):=
|
322 |
|
|
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
|
323 |
|
|
--********************************************************************
|
324 |
|
|
when READ =>
|
325 |
|
|
if (not v.pio_started and v.tf.ctrl(NIEN)='0') then
|
326 |
|
|
atao.intrq<='1'; v.pio_started:=true; v.intrq:=true;
|
327 |
|
|
elsif not v.intrq then
|
328 |
|
|
v.tf.stat(DRQ):='1';
|
329 |
|
|
if v.dtar_read and r.dior='0' and atai.dior='1' then --rising dior detect
|
330 |
|
|
v.dtar_read:=false;
|
331 |
|
|
v.byte_cnt:=v.byte_cnt+2;
|
332 |
|
|
if(v.byte_cnt=sector_length) then
|
333 |
|
|
v.tf.scr:=v.tf.scr-1;
|
334 |
|
|
if (v.tf.scr=X"00") then
|
335 |
|
|
v.cmd_started:=false;
|
336 |
|
|
end if;
|
337 |
|
|
v.byte_cnt:=0;
|
338 |
|
|
v.tf.stat(DRQ):='0';
|
339 |
|
|
v.tf.stat(BSY):='1';
|
340 |
|
|
v.tf.feat:="00001111";
|
341 |
|
|
if v.tf.ctrl(NIEN)='0' then
|
342 |
|
|
atao.intrq<='1';
|
343 |
|
|
end if;
|
344 |
|
|
end if;
|
345 |
|
|
end if;
|
346 |
|
|
end if;
|
347 |
|
|
v.ram.oe:='0'; v.ram.ce:='0';v.ram.we:='1'; v.tf.dtar:=s_d;
|
348 |
|
|
v.ram.a(log2_size-2 downto log2(sector_length)-1):=
|
349 |
|
|
r.scr((log2_size-log2(sector_length)-1) downto 0) - r.tf.scr((log2_size-log2(sector_length)-1) downto 0);
|
350 |
|
|
v.ram.a(log2(sector_length)-2 downto 0):=
|
351 |
|
|
conv_std_logic_vector((r.byte_cnt/2),log2(sector_length)-1);
|
352 |
|
|
--********************************************************************
|
353 |
|
|
when others => v.tf.stat:=v.tf.stat; v.cmd_started:=false;
|
354 |
|
|
end case;
|
355 |
|
|
end if;
|
356 |
|
|
|
357 |
|
|
if r.ram.ce='0' and r.ram.oe='1' then
|
358 |
|
|
v.ram.oe:='1'; v.ram.ce:='1';v.ram.we:='1'; v.ram_dta:=(others=>'Z');
|
359 |
|
|
end if;
|
360 |
|
|
|
361 |
|
|
if (r.dior='0' and atai.dior='1') then
|
362 |
|
|
d(15 downto 0)<=(others=>'Z');
|
363 |
|
|
end if;
|
364 |
|
|
|
365 |
|
|
end if; --read write reg
|
366 |
|
|
end if; --reset
|
367 |
|
|
|
368 |
|
|
ri<=v;
|
369 |
|
|
end process comb;
|
370 |
|
|
|
371 |
|
|
with r.ram.oe select
|
372 |
|
|
s_d<=r.ram_dta when '1',
|
373 |
|
|
(others=>'Z') when others;
|
374 |
|
|
|
375 |
|
|
disk : sram16 generic map (index => 0, abits => log2_size-1, fname => sramfile)
|
376 |
|
|
port map (r.ram.a, s_d, '0', '0', r.ram.ce, r.ram.we, r.ram.oe);
|
377 |
|
|
|
378 |
|
|
--**********************SYNC PROCESS******************************************
|
379 |
|
|
sync: process(clk) --dior/diow insted?
|
380 |
|
|
begin
|
381 |
|
|
if rising_edge(clk) then
|
382 |
|
|
r<=ri;
|
383 |
|
|
end if;
|
384 |
|
|
end process sync;
|
385 |
|
|
end;
|
386 |
|
|
|
387 |
|
|
--************************END OF FILE*******************************************
|