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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: grspw
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-- File: grspw.vhd
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-- Author: Marko Isomaki - Gaisler Research
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-- Description: GRLIB wrapper for grspw core
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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use techmap.netcomp.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.spacewire.all;
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library spw;
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use spw.spwcomp.all;
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entity grspw is
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generic(
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tech : integer range 0 to NTECH := DEFFABTECH;
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hindex : integer range 0 to NAHBMST-1 := 0;
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pindex : integer range 0 to NAPBSLV-1 := 0;
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paddr : integer range 0 to 16#FFF# := 0;
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pmask : integer range 0 to 16#FFF# := 16#FFF#;
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pirq : integer range 0 to NAHBIRQ-1 := 0;
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sysfreq : integer := 10000;
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usegen : integer range 0 to 1 := 1;
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nsync : integer range 1 to 2 := 1;
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rmap : integer range 0 to 1 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxclkbuftype : integer range 0 to 2 := 0;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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techfifo : integer range 0 to 1 := 1;
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netlist : integer range 0 to 1 := 0;
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ports : integer range 1 to 2 := 1;
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memtech : integer range 0 to NTECH := DEFMEMTECH
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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swni : in grspw_in_type;
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swno : out grspw_out_type
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);
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end entity;
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architecture rtl of grspw is
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constant fabits1 : integer := log2(fifosize1);
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constant fabits2 : integer := log2(fifosize2);
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constant rfifo : integer := 5 + log2(rmapbufs);
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constant REVISION : integer := 0;
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constant pconfig : apb_config_type := (
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1 => apb_iobar(paddr, pmask));
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constant hconfig : ahb_config_type := (
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others => zero32);
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signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0);
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--rx ahb fifo
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signal rxrenable : std_ulogic;
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signal rxraddress : std_logic_vector(4 downto 0);
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signal rxwrite : std_ulogic;
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signal rxwdata : std_logic_vector(31 downto 0);
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signal rxwaddress : std_logic_vector(4 downto 0);
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signal rxrdata : std_logic_vector(31 downto 0);
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--tx ahb fifo
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signal txrenable : std_ulogic;
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signal txraddress : std_logic_vector(4 downto 0);
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signal txwrite : std_ulogic;
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signal txwdata : std_logic_vector(31 downto 0);
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signal txwaddress : std_logic_vector(4 downto 0);
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signal txrdata : std_logic_vector(31 downto 0);
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--nchar fifo
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signal ncrenable : std_ulogic;
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signal ncraddress : std_logic_vector(5 downto 0);
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signal ncwrite : std_ulogic;
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signal ncwdata : std_logic_vector(8 downto 0);
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signal ncwaddress : std_logic_vector(5 downto 0);
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signal ncrdata : std_logic_vector(8 downto 0);
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--rmap buf
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signal rmrenable : std_ulogic;
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signal rmrenablex : std_ulogic;
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signal rmraddress : std_logic_vector(7 downto 0);
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signal rmwrite : std_ulogic;
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signal rmwdata : std_logic_vector(7 downto 0);
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signal rmwaddress : std_logic_vector(7 downto 0);
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signal rmrdata : std_logic_vector(7 downto 0);
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--misc
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signal irq : std_ulogic;
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signal rxclk, nrxclk : std_logic_vector(ports-1 downto 0);
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signal testin : std_logic_vector(3 downto 0);
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begin
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testin <= ahbmi.testen & "000";
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rtl : if netlist = 0 generate
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grspwc0 : grspwc
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generic map(
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sysfreq => sysfreq,
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usegen => usegen,
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nsync => nsync,
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rmap => rmap,
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rmapcrc => rmapcrc,
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fifosize1 => fifosize1,
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fifosize2 => fifosize2,
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rxunaligned => rxunaligned,
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rmapbufs => rmapbufs,
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scantest => scantest,
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ports => ports,
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tech => tech)
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port map(
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rst => rst,
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clk => clk,
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txclk => txclk,
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--ahb mst in
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hgrant => ahbmi.hgrant(hindex),
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hready => ahbmi.hready,
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hresp => ahbmi.hresp,
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hrdata => ahbmi.hrdata,
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--ahb mst out
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hbusreq => ahbmo.hbusreq,
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hlock => ahbmo.hlock,
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htrans => ahbmo.htrans,
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haddr => ahbmo.haddr,
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hwrite => ahbmo.hwrite,
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hsize => ahbmo.hsize,
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hburst => ahbmo.hburst,
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hprot => ahbmo.hprot,
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hwdata => ahbmo.hwdata,
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--apb slv in
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psel => apbi.psel(pindex),
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penable => apbi.penable,
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paddr => apbi.paddr,
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pwrite => apbi.pwrite,
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pwdata => apbi.pwdata,
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--apb slv out
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prdata => apbo.prdata,
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--spw in
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di => swni.d,
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si => swni.s,
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--spw out
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do => swno.d,
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so => swno.s,
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--time iface
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tickin => swni.tickin,
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tickout => swno.tickout,
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--clk bufs
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rxclki => rxclki,
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nrxclki => nrxclki,
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rxclko => rxclko,
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--irq
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irq => irq,
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--misc
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clkdiv10 => swni.clkdiv10,
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dcrstval => swni.dcrstval,
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timerrstval => swni.timerrstval,
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--rmapen
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rmapen => swni.rmapen,
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--rx ahb fifo
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rxrenable => rxrenable,
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rxraddress => rxraddress,
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rxwrite => rxwrite,
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rxwdata => rxwdata,
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rxwaddress => rxwaddress,
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rxrdata => rxrdata,
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--tx ahb fifo
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txrenable => txrenable,
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txraddress => txraddress,
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txwrite => txwrite,
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txwdata => txwdata,
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txwaddress => txwaddress,
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txrdata => txrdata,
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--nchar fifo
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ncrenable => ncrenable,
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ncraddress => ncraddress,
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ncwrite => ncwrite,
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ncwdata => ncwdata,
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ncwaddress => ncwaddress,
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ncrdata => ncrdata,
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--rmap buf
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rmrenable => rmrenable,
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rmraddress => rmraddress,
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rmwrite => rmwrite,
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rmwdata => rmwdata,
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rmwaddress => rmwaddress,
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rmrdata => rmrdata,
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linkdis => swno.linkdis,
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testclk => clk,
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testrst => ahbmi.testrst,
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testen => ahbmi.testen
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);
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end generate;
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struct : if netlist = 1 generate
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grspwc0 : grspwc_net
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generic map(
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tech => tech,
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sysfreq => sysfreq,
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usegen => usegen,
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nsync => nsync,
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rmap => rmap,
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rmapcrc => rmapcrc,
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fifosize1 => fifosize1,
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fifosize2 => fifosize2,
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rxunaligned => rxunaligned,
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rmapbufs => rmapbufs,
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scantest => scantest)
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port map(
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rst => rst,
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clk => clk,
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txclk => txclk,
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--ahb mst in
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hgrant => ahbmi.hgrant(hindex),
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hready => ahbmi.hready,
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hresp => ahbmi.hresp,
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hrdata => ahbmi.hrdata,
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--ahb mst out
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hbusreq => ahbmo.hbusreq,
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hlock => ahbmo.hlock,
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htrans => ahbmo.htrans,
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haddr => ahbmo.haddr,
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hwrite => ahbmo.hwrite,
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hsize => ahbmo.hsize,
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hburst => ahbmo.hburst,
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hprot => ahbmo.hprot,
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hwdata => ahbmo.hwdata,
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--apb slv in
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psel => apbi.psel(pindex),
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penable => apbi.penable,
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paddr => apbi.paddr,
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pwrite => apbi.pwrite,
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pwdata => apbi.pwdata,
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--apb slv out
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prdata => apbo.prdata,
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--spw in
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di => swni.d,
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si => swni.s,
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271 |
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--spw out
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272 |
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do => swno.d,
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273 |
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so => swno.s,
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274 |
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--time iface
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275 |
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tickin => swni.tickin,
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276 |
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tickout => swno.tickout,
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277 |
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--clk bufs
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278 |
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rxclki => rxclki,
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279 |
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nrxclki => nrxclki,
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280 |
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rxclko => rxclko,
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281 |
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--irq
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282 |
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irq => irq,
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283 |
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--misc
|
284 |
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clkdiv10 => swni.clkdiv10,
|
285 |
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dcrstval => swni.dcrstval,
|
286 |
|
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timerrstval => swni.timerrstval,
|
287 |
|
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--rmapen
|
288 |
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rmapen => swni.rmapen,
|
289 |
|
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--rx ahb fifo
|
290 |
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rxrenable => rxrenable,
|
291 |
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rxraddress => rxraddress,
|
292 |
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rxwrite => rxwrite,
|
293 |
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rxwdata => rxwdata,
|
294 |
|
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rxwaddress => rxwaddress,
|
295 |
|
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rxrdata => rxrdata,
|
296 |
|
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--tx ahb fifo
|
297 |
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txrenable => txrenable,
|
298 |
|
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txraddress => txraddress,
|
299 |
|
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txwrite => txwrite,
|
300 |
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txwdata => txwdata,
|
301 |
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txwaddress => txwaddress,
|
302 |
|
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txrdata => txrdata,
|
303 |
|
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--nchar fifo
|
304 |
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ncrenable => ncrenable,
|
305 |
|
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ncraddress => ncraddress,
|
306 |
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ncwrite => ncwrite,
|
307 |
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ncwdata => ncwdata,
|
308 |
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ncwaddress => ncwaddress,
|
309 |
|
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ncrdata => ncrdata,
|
310 |
|
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--rmap buf
|
311 |
|
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rmrenable => rmrenable,
|
312 |
|
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rmraddress => rmraddress,
|
313 |
|
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rmwrite => rmwrite,
|
314 |
|
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rmwdata => rmwdata,
|
315 |
|
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rmwaddress => rmwaddress,
|
316 |
|
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rmrdata => rmrdata,
|
317 |
|
|
linkdis => swno.linkdis,
|
318 |
|
|
testclk => clk,
|
319 |
|
|
testrst => ahbmi.testrst,
|
320 |
|
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testen => ahbmi.testen
|
321 |
|
|
);
|
322 |
|
|
end generate;
|
323 |
|
|
|
324 |
|
|
irqdrv : process(irq)
|
325 |
|
|
begin
|
326 |
|
|
apbo.pirq <= (others => '0');
|
327 |
|
|
apbo.pirq(pirq) <= irq;
|
328 |
|
|
end process;
|
329 |
|
|
|
330 |
|
|
ahbmo.hirq <= (others => '0');
|
331 |
|
|
ahbmo.hconfig <= hconfig;
|
332 |
|
|
ahbmo.hindex <= hindex;
|
333 |
|
|
|
334 |
|
|
apbo.pconfig <= pconfig;
|
335 |
|
|
apbo.pindex <= pindex;
|
336 |
|
|
|
337 |
|
|
ntst: if scantest = 0 generate
|
338 |
|
|
cloop : for i in 0 to ports-1 generate
|
339 |
|
|
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
|
340 |
|
|
port map(i => rxclko(i), o => rxclki(i));
|
341 |
|
|
end generate;
|
342 |
|
|
rmrenablex <= rmrenable;
|
343 |
|
|
end generate;
|
344 |
|
|
tst: if scantest = 1 generate
|
345 |
|
|
cloop : for i in 0 to ports-1 generate
|
346 |
|
|
rxclk(i) <= clk when ahbmi.testen = '1' else rxclko(i);
|
347 |
|
|
nrxclk(i) <= clk when ahbmi.testen = '1' else not rxclko(i);
|
348 |
|
|
rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
|
349 |
|
|
port map(i => rxclk(i), o => rxclki(i));
|
350 |
|
|
nrx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
|
351 |
|
|
port map(i => nrxclk(i), o => nrxclki(i));
|
352 |
|
|
end generate;
|
353 |
|
|
rmrenablex <= rmrenable and not ahbmi.testen;
|
354 |
|
|
end generate;
|
355 |
|
|
|
356 |
|
|
------------------------------------------------------------------------------
|
357 |
|
|
-- FIFOS ---------------------------------------------------------------------
|
358 |
|
|
------------------------------------------------------------------------------
|
359 |
|
|
|
360 |
|
|
nft : if ft = 0 generate
|
361 |
|
|
--receiver AHB FIFO
|
362 |
|
|
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
|
363 |
|
|
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0), rxrdata, clk,
|
364 |
|
|
rxwrite, rxwaddress(fabits1-1 downto 0), rxwdata, testin);
|
365 |
|
|
|
366 |
|
|
--receiver nchar FIFO
|
367 |
|
|
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
|
368 |
|
|
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0), ncrdata, clk,
|
369 |
|
|
ncwrite, ncwaddress(fabits2-1 downto 0), ncwdata, testin);
|
370 |
|
|
|
371 |
|
|
--transmitter FIFO
|
372 |
|
|
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
|
373 |
|
|
port map(clk, txrenable, txraddress(fabits1-1 downto 0), txrdata, clk,
|
374 |
|
|
txwrite, txwaddress(fabits1-1 downto 0), txwdata, testin);
|
375 |
|
|
|
376 |
|
|
--RMAP Buffer
|
377 |
|
|
rmap_ram : if (rmap = 1) generate
|
378 |
|
|
ram0 : syncram_2p generic map(memtech, rfifo, 8)
|
379 |
|
|
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0), rmrdata, clk,
|
380 |
|
|
rmwrite, rmwaddress(rfifo-1 downto 0), rmwdata, testin);
|
381 |
|
|
end generate;
|
382 |
|
|
end generate;
|
383 |
|
|
|
384 |
|
|
ft1 : if ft /= 0 generate
|
385 |
|
|
--receiver AHB FIFO
|
386 |
|
|
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
|
387 |
|
|
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0), rxrdata, clk,
|
388 |
|
|
rxwrite, rxwaddress(fabits1-1 downto 0), rxwdata, open, testin);
|
389 |
|
|
|
390 |
|
|
--receiver nchar FIFO
|
391 |
|
|
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
|
392 |
|
|
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
|
393 |
|
|
ncrdata, clk, ncwrite,
|
394 |
|
|
ncwaddress(fabits2-1 downto 0), ncwdata, open, testin);
|
395 |
|
|
|
396 |
|
|
--transmitter FIFO
|
397 |
|
|
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
|
398 |
|
|
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
|
399 |
|
|
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata, open, testin);
|
400 |
|
|
|
401 |
|
|
--RMAP Buffer
|
402 |
|
|
rmap_ram : if (rmap = 1) generate
|
403 |
|
|
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
|
404 |
|
|
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
|
405 |
|
|
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
|
406 |
|
|
rmwdata, open, testin);
|
407 |
|
|
end generate;
|
408 |
|
|
end generate;
|
409 |
|
|
|
410 |
|
|
-- pragma translate_off
|
411 |
|
|
msg0 : if (rmap = 0) generate
|
412 |
|
|
bootmsg : report_version
|
413 |
|
|
generic map ("grspw" & tost(pindex) &
|
414 |
|
|
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x" &
|
415 |
|
|
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
|
416 |
|
|
" bytes, irq " & tost(pirq));
|
417 |
|
|
end generate;
|
418 |
|
|
|
419 |
|
|
msg1 : if (rmap = 1) generate
|
420 |
|
|
bootmsg : report_version
|
421 |
|
|
generic map ("grspw" & tost(pindex) &
|
422 |
|
|
": Spacewire link rev " & tost(REVISION) & ", AHB fifos 2x " &
|
423 |
|
|
tost(fifosize1*4) & " bytes, rx fifo " & tost(fifosize2) &
|
424 |
|
|
" bytes, irq " & tost(pirq) & " , RMAP Buffer " &
|
425 |
|
|
tost(rmapbufs*32) & " bytes");
|
426 |
|
|
end generate;
|
427 |
|
|
|
428 |
|
|
pr0 : process is
|
429 |
|
|
begin
|
430 |
|
|
wait for 100 ns;
|
431 |
|
|
if sysfreq < 10000 then
|
432 |
|
|
print("WARNING: System frequency too low for GRSPW");
|
433 |
|
|
end if;
|
434 |
|
|
wait;
|
435 |
|
|
end process;
|
436 |
|
|
|
437 |
|
|
-- pragma translate_on
|
438 |
|
|
|
439 |
|
|
end architecture;
|