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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: grspwm
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-- File: grspwm.vhd
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-- Author: Nils-Johan Wessman - Gaisler Research
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-- Description: Module to select between grspw and grspw2
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.spacewire.all;
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entity grspwm is
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generic(
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tech : integer range 0 to NTECH := DEFFABTECH;
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hindex : integer range 0 to NAHBMST-1 := 0;
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pindex : integer range 0 to NAPBSLV-1 := 0;
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paddr : integer range 0 to 16#FFF# := 0;
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pmask : integer range 0 to 16#FFF# := 16#FFF#;
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pirq : integer range 0 to NAHBIRQ-1 := 0;
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sysfreq : integer := 10000; -- spw1
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usegen : integer range 0 to 1 := 1; -- spw1
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nsync : integer range 1 to 2 := 1;
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rmap : integer range 0 to 1 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxclkbuftype : integer range 0 to 2 := 0;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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techfifo : integer range 0 to 1 := 1;
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netlist : integer range 0 to 1 := 0; -- spw1
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ports : integer range 1 to 2 := 1;
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dmachan : integer range 1 to 4 := 1; -- spw2
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memtech : integer range 0 to NTECH := DEFMEMTECH;
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spwcore : integer range 1 to 2 := 2 -- select spw core spw1/spw2
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbmo : out ahb_mst_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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swni : in grspw_in_type;
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swno : out grspw_out_type
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);
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end entity;
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architecture rtl of grspwm is
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begin
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spw1 : if spwcore = 1 generate
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u0 : grspw
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generic map(tech, hindex, pindex, paddr, pmask, pirq,
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sysfreq, usegen, nsync, rmap, rmapcrc, fifosize1, fifosize2,
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rxclkbuftype, rxunaligned, rmapbufs, ft, scantest, techfifo,
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netlist, ports, memtech)
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port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
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end generate;
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spw2 : if spwcore = 2 generate
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u0 : grspw2
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generic map(tech, hindex, pindex, paddr, pmask, pirq,
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nsync, rmap, rmapcrc, fifosize1, fifosize2, rxclkbuftype,
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rxunaligned, rmapbufs, ft, scantest, techfifo, ports,
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dmachan, memtech)
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port map(rst, clk, txclk, ahbmi, ahbmo, apbi, apbo, swni, swno);
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end generate;
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end architecture;
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