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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [spacewire/] [spacewire.vhd] - Blame information for rev 2

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1 2 dimamali 
------------------------------------------------------------------------------
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--  This file is a part of the GRLIB VHDL IP LIBRARY
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--  Copyright (C) 2003, Gaisler Research
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--
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  This program is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this program; if not, write to the Free Software
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--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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library techmap;
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use techmap.gencomp.all;
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package spacewire is
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  type grspw_in_type is record
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    d           : std_logic_vector(1 downto 0);
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    s           : std_logic_vector(1 downto 0);
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    tickin      : std_ulogic;
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    clkdiv10    : std_logic_vector(7 downto 0);
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    rmapen      : std_ulogic;
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    dcrstval    : std_logic_vector(9 downto 0);
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    timerrstval : std_logic_vector(11 downto 0);
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  end record;
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  type grspw_out_type is record
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    d           : std_logic_vector(1 downto 0);
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    s           : std_logic_vector(1 downto 0);
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    tickout     : std_ulogic;
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    linkdis     : std_ulogic;
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  end record;
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  component grspw2 is
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    generic(
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      tech         : integer range 0 to NTECH     := inferred;
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      hindex       : integer range 0 to NAHBMST-1 := 0;
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      pindex       : integer range 0 to NAPBSLV-1 := 0;
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      paddr        : integer range 0 to 16#FFF#   := 0;
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      pmask        : integer range 0 to 16#FFF#   := 16#FFF#;
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      pirq         : integer range 0 to NAHBIRQ-1 := 0;
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      nsync        : integer range 1 to 2  := 1;
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      rmap         : integer range 0 to 1  := 0;
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      rmapcrc      : integer range 0 to 1  := 0;
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      fifosize1    : integer range 4 to 32 := 32;
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      fifosize2    : integer range 16 to 64 := 64;
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      rxclkbuftype : integer range 0 to 2 := 0;
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      rxunaligned  : integer range 0 to 1 := 0;
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      rmapbufs     : integer range 2 to 8 := 4;
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      ft           : integer range 0 to 2 := 0;
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      scantest     : integer range 0 to 1 := 0;
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      techfifo     : integer range 0 to 1 := 1;
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      ports        : integer range 1 to 2 := 1;
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      dmachan      : integer range 1 to 4 := 1;
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      memtech      : integer range 0 to NTECH := DEFMEMTECH
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    );
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    port(
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      rst        : in  std_ulogic;
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      clk        : in  std_ulogic;
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      txclk      : in  std_ulogic;
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      ahbmi      : in  ahb_mst_in_type;
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      ahbmo      : out ahb_mst_out_type;
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      apbi       : in  apb_slv_in_type;
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      apbo       : out apb_slv_out_type;
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      swni       : in  grspw_in_type;
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      swno       : out grspw_out_type
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    );
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  end component;
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  component grspw is
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    generic(
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      tech         : integer range 0 to NTECH := DEFFABTECH;
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      hindex       : integer range 0 to NAHBMST-1 := 0;
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      pindex       : integer range 0 to NAPBSLV-1 := 0;
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      paddr        : integer range 0 to 16#FFF#   := 0;
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      pmask        : integer range 0 to 16#FFF#   := 16#FFF#;
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      pirq         : integer range 0 to NAHBIRQ-1 := 0;
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      sysfreq      : integer := 10000;
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      usegen       : integer range 0 to 1  := 1;
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      nsync        : integer range 1 to 2  := 1;
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      rmap         : integer range 0 to 1  := 0;
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      rmapcrc      : integer range 0 to 1  := 0;
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      fifosize1    : integer range 4 to 32 := 32;
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      fifosize2    : integer range 16 to 64 := 64;
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      rxclkbuftype : integer range 0 to 2 := 0;
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      rxunaligned  : integer range 0 to 1 := 0;
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      rmapbufs     : integer range 2 to 8 := 4;
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      ft           : integer range 0 to 2 := 0;
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      scantest     : integer range 0 to 1 := 0;
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      techfifo     : integer range 0 to 1 := 1;
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      netlist      : integer range 0 to 1 := 0;
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      ports        : integer range 1 to 2 := 1;
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      memtech      : integer range 0 to NTECH := DEFMEMTECH
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    );
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    port(
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      rst        : in  std_ulogic;
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      clk        : in  std_ulogic;
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      txclk      : in  std_ulogic;
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      ahbmi      : in  ahb_mst_in_type;
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      ahbmo      : out ahb_mst_out_type;
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      apbi       : in  apb_slv_in_type;
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      apbo       : out apb_slv_out_type;
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      swni       : in  grspw_in_type;
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      swno       : out grspw_out_type);
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  end component;
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  type grspw_in_type_vector is array (natural range <>) of grspw_in_type;
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  type grspw_out_type_vector is array (natural range <>) of grspw_out_type;
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  component grspwm is
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    generic(
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      tech         : integer range 0 to NTECH := DEFFABTECH;
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      hindex       : integer range 0 to NAHBMST-1 := 0;
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      pindex       : integer range 0 to NAPBSLV-1 := 0;
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      paddr        : integer range 0 to 16#FFF#   := 0;
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      pmask        : integer range 0 to 16#FFF#   := 16#FFF#;
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      pirq         : integer range 0 to NAHBIRQ-1 := 0;
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      sysfreq      : integer := 10000;
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      usegen       : integer range 0 to 1  := 1;
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      nsync        : integer range 1 to 2  := 1;
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      rmap         : integer range 0 to 1  := 0;
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      rmapcrc      : integer range 0 to 1  := 0;
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      fifosize1    : integer range 4 to 32 := 32;
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      fifosize2    : integer range 16 to 64 := 64;
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      rxclkbuftype : integer range 0 to 2 := 0;
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      rxunaligned  : integer range 0 to 1 := 0;
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      rmapbufs     : integer range 2 to 8 := 4;
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      ft           : integer range 0 to 2 := 0;
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      scantest     : integer range 0 to 1 := 0;
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      techfifo     : integer range 0 to 1 := 1;
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      netlist      : integer range 0 to 1 := 0;
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      ports        : integer range 1 to 2 := 1;
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      dmachan      : integer range 1 to 4 := 1;
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      memtech      : integer range 0 to NTECH := DEFMEMTECH;
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      spwcore      : integer range 1 to 2 := 2
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    );
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    port(
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      rst        : in  std_ulogic;
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      clk        : in  std_ulogic;
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      txclk      : in  std_ulogic;
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      ahbmi      : in  ahb_mst_in_type;
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      ahbmo      : out ahb_mst_out_type;
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      apbi       : in  apb_slv_in_type;
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      apbo       : out apb_slv_out_type;
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      swni       : in  grspw_in_type;
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      swno       : out grspw_out_type
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    );
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  end component;
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end package;

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