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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: dcom_uart
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-- File: dcom_uart.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: Asynchronous UART with baud-rate detection.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.uart.all;
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--pragma translate_off
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use std.textio.all;
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--pragma translate_on
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entity dcom_uart is
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generic (
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pindex : integer := 0;
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paddr : integer := 0;
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pmask : integer := 16#fff#
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ui : in uart_in_type;
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uo : out uart_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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uarti : in dcom_uart_in_type;
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uarto : out dcom_uart_out_type
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);
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end;
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architecture rtl of dcom_uart is
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constant REVISION : integer := 0;
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constant pconfig : apb_config_type := (
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1 => apb_iobar(paddr, pmask));
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type rxfsmtype is (idle, startbit, data, stopbit);
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type txfsmtype is (idle, data, stopbit);
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type uartregs is record
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rxen : std_ulogic; -- receiver enabled
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dready : std_ulogic; -- data ready
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rsempty : std_ulogic; -- receiver shift register empty (internal)
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tsempty : std_ulogic; -- transmitter shift register empty
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thempty : std_ulogic; -- transmitter hold register empty
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break : std_ulogic; -- break detected
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ovf : std_ulogic; -- receiver overflow
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frame : std_ulogic; -- framing error
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rhold : std_logic_vector(7 downto 0);
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rshift : std_logic_vector(7 downto 0);
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tshift : std_logic_vector(10 downto 0);
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thold : std_logic_vector(7 downto 0);
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txstate : txfsmtype;
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txclk : std_logic_vector(2 downto 0); -- tx clock divider
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txtick : std_ulogic; -- tx clock (internal)
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rxstate : rxfsmtype;
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rxclk : std_logic_vector(2 downto 0); -- rx clock divider
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rxdb : std_ulogic; -- rx data filtering buffer
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rxtick : std_ulogic; -- rx clock (internal)
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tick : std_ulogic; -- rx clock (internal)
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scaler : std_logic_vector(17 downto 0);
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brate : std_logic_vector(17 downto 0);
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tcnt : std_logic_vector(1 downto 0); -- autobaud counter
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rxdb2 : std_ulogic; -- delayed rx data
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rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
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fedge : std_ulogic; -- rx falling edge
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end record;
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signal r, rin : uartregs;
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begin
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uartop : process(rst, r, apbi, uarti, ui )
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variable rdata : std_logic_vector(31 downto 0);
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variable scaler : std_logic_vector(17 downto 0);
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variable rxclk, txclk : std_logic_vector(2 downto 0);
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variable irxd : std_ulogic;
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variable v : uartregs;
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begin
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v := r;
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v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
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-- scaler
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if r.tcnt = "11" then scaler := r.scaler - 1;
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else scaler := r.scaler + 1; end if;
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v.rxdb2 := r.rxdb;
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if r.tcnt /= "11" then
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if (r.rxdb2 and not r.rxdb) = '1' then v.fedge := '1'; end if;
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if (r.fedge) = '1' then
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v.scaler := scaler;
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if (v.scaler(17) and not r.scaler(16)) = '1' then
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v.scaler := "111111111111111011";
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v.fedge := '0'; v.tcnt := "00";
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end if;
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end if;
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if (r.rxdb2 and r.fedge and not r.rxdb) = '1' then
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if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
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v.brate := r.scaler; v.tcnt := "00";
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end if;
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v.scaler := "111111111111111011";
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if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
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v.tcnt := r.tcnt + 1;
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if r.tcnt = "10" then
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v.brate := "0000" & r.scaler(17 downto 4);
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v.scaler := v.brate; v.rxen := '1';
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end if;
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end if;
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end if;
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else
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if (r.break and r.rxdb2) = '1' then
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v.scaler := "111111111111111011";
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v.brate := (others => '1'); v.tcnt := "00";
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v.break := '0'; v.rxen := '0';
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end if;
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end if;
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if r.rxen = '1' then
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v.scaler := scaler;
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v.tick := scaler(15) and not r.scaler(15);
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if v.tick = '1' then v.scaler := r.brate; end if;
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end if;
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-- read/write registers
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if uarti.read = '1' then v.dready := '0'; end if;
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case apbi.paddr(3 downto 2) is
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when "01" =>
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rdata(6 downto 0) := r.frame & '0' & r.ovf &
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r.break & r.thempty & r.tsempty & r.dready;
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when "10" =>
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rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
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when others =>
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rdata(17 downto 0) := r.brate;
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end case;
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if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
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case apbi.paddr(3 downto 2) is
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when "01" =>
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v.frame := apbi.pwdata(6);
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v.ovf := apbi.pwdata(4);
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v.break := apbi.pwdata(3);
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when "10" =>
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v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
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v.rxen := apbi.pwdata(0);
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when "11" =>
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v.brate := apbi.pwdata(17 downto 0);
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v.scaler := apbi.pwdata(17 downto 0);
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when others =>
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end case;
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end if;
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-- tx clock
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txclk := r.txclk + 1;
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if r.tick = '1' then
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v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
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end if;
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-- rx clock
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rxclk := r.rxclk + 1;
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if r.tick = '1' then
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v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
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end if;
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-- filter rx data
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v.rxf := r.rxf(6 downto 0) & ui.rxd;
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if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
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r.rxf(7)) = r.rxf(6 downto 0))
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then v.rxdb := r.rxf(7); end if;
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irxd := r.rxdb;
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-- transmitter operation
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case r.txstate is
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when idle => -- idle state
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if (r.txtick = '1') then v.tsempty := '1'; end if;
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if (r.rxen and (not r.thempty) and r.txtick) = '1' then
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v.tshift := "10" & r.thold & '0'; v.txstate := data;
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v.thempty := '1';
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v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
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end if;
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when data => -- transmitt data frame
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if r.txtick = '1' then
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v.tshift := '1' & r.tshift(10 downto 1);
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if r.tshift(10 downto 1) = "1111111110" then
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v.tshift(0) := '1'; v.txstate := stopbit;
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end if;
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end if;
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when stopbit => -- transmitt stop bit
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if r.txtick = '1' then
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v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
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end if;
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end case;
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-- writing of tx data register must be done after tx fsm to get correct
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-- operation of thempty flag
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if uarti.write = '1' then
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v.thold := uarti.data(7 downto 0); v.thempty := '0';
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end if;
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-- receiver operation
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case r.rxstate is
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when idle => -- wait for start bit
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if ((not r.rsempty) and not r.dready) = '1' then
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v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
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end if;
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if (r.rxen and r.rxdb2 and (not irxd)) = '1' then
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v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
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if v.rsempty = '0' then v.ovf := '1'; end if;
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v.rsempty := '0'; v.rxtick := '0';
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end if;
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when startbit => -- check validity of start bit
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if r.rxtick = '1' then
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if irxd = '0' then
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v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
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else
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v.rxstate := idle;
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end if;
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end if;
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when data => -- receive data frame
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if r.rxtick = '1' then
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v.rshift := irxd & r.rshift(7 downto 1);
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if r.rshift(0) = '0' then
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v.rxstate := stopbit;
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end if;
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end if;
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when stopbit => -- receive stop bit
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if r.rxtick = '1' then
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if irxd = '1' then
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v.rsempty := '0';
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if v.dready = '0' then
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v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
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end if;
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else
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if r.rshift = "00000000" then
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v.break := '1'; -- break
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else
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v.frame := '1'; -- framing error
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end if;
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v.rsempty := '1';
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end if;
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v.rxstate := idle;
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end if;
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end case;
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284 |
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285 |
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-- reset operation
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286 |
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287 |
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if rst = '0' then
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v.frame := '0'; v.rsempty := '1';
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v.ovf := '0'; v.break := '0'; v.thempty := '1';
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290 |
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v.tsempty := '1'; v.dready := '0'; v.fedge := '0';
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291 |
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v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
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292 |
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v.scaler := "111111111111111011"; v.brate := (others => '1');
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293 |
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v.rxen := '0'; v.tcnt := "00";
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294 |
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v.txclk := (others => '0'); v.rxclk := (others => '0');
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295 |
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end if;
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296 |
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297 |
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-- update registers
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298 |
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299 |
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rin <= v;
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300 |
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301 |
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-- drive outputs
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302 |
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uo.txd <= r.tshift(0);
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303 |
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uo.scaler <= r.brate;
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304 |
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uo.rtsn <= '0';
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305 |
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uarto.dready <= r.dready;
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306 |
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uarto.tsempty <= r.tsempty;
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307 |
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uarto.thempty <= r.thempty;
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308 |
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uarto.lock <= r.tcnt(1) and r.tcnt(0);
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309 |
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uarto.enable <= r.rxen;
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310 |
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uarto.data <= r.rhold;
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311 |
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312 |
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apbo.prdata <= rdata;
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313 |
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314 |
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end process;
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315 |
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316 |
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apbo.pirq <= (others => '0');
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317 |
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apbo.pconfig <= pconfig;
|
318 |
|
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apbo.pindex <= pindex;
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319 |
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320 |
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regs : process(clk)
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321 |
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begin if rising_edge(clk) then r <= rin; end if; end process;
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322 |
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323 |
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end;
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