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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [vlog/] [ctl_fsm1.v] - Blame information for rev 2

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1 2 dimamali 
/******************************************************************
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 *                                                                *
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 *    Author: Liwei                                               *
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 *                                                                *
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 *    This file is part of the "mips789" project.                 *
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 *    Downloaded from:                                            *
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 *    http://www.opencores.org/pdownloads.cgi/list/mips789        *
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 *                                                                *
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 *    If you encountered any problem, please contact me via       *
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 *    Email:mcupro@opencores.org  or mcupro@163.com               *
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 *                                                                *
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 ******************************************************************/
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`include "mips789_defs.v"
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module ctl_FSM (
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    input   clk,
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    input   hold,
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    input   [2:0] id_cmd,
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//  input   irq,
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    input   rst,
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    output  reg iack,
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    output  reg zz_is_nop,
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    output  reg id2ra_ctl_clr,
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    output  reg id2ra_ctl_cls,
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    output  reg id2ra_ins_clr,
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    output  reg id2ra_ins_cls,
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    output  reg [3:0] pc_prectl,
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    output  reg ra2exec_ctl_clr
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    );
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    parameter
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        ID_CUR   = `FSM_CUR,   ID_LD    = `FSM_LD ,
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        ID_MUL   = `FSM_MUL,   ID_NOI   = `FSM_NOI,
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        ID_RET   = `FSM_RET,
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        PC_IGN   = `PC_IGN ,   PC_IRQ   = `PC_IRQ,
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        PC_KEP   = `PC_KEP ,   PC_RST   = `PC_RST;
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    reg [5:0] delay_counter;
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    reg [4:0] CurrState ;
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    reg [4:0] NextState ;
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    reg     riack;
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    always @(posedge clk) if (~rst) riack<=0; else riack<=iack;
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    always @(*)
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    begin //deal with iack
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        case (CurrState )
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            `IRQ:iack=1'b1;
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            `RET:iack=1'b0;
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            //onlt this 2 states those will change the iack state
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            default iack=riack;
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        endcase
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    end
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    always @ (posedge clk )
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        if (~rst)delay_counter  <=0;
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        else
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        case (CurrState)
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            //any delay state can be added here
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            `MUL:       delay_counter  <=delay_counter + 1;
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            default :     delay_counter  <=0;
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        endcase
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/////////////////////////////////////////////////////////
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//    Finite State Machine
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//
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  /*Finite State Machine part1*/
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    always @ (posedge clk) if (~rst) CurrState  <= `RST; else if (hold) CurrState  <= NextState ;
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    always @ (*)/*Finite State Machine part2*/
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    begin
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        case (CurrState)
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            `IDLE:
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            begin
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                if (~rst)                    NextState  = `RST;
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//                else if ((irq)&&(~riack))    NextState  = `IRQ;
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                else if (id_cmd ==ID_NOI)    NextState  = `NOI;
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                else if (id_cmd==ID_CUR)     NextState  = `CUR;
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                else if (id_cmd==ID_MUL)     NextState  = `MUL;
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                else if (id_cmd==ID_LD)      NextState  = `LD;
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                else if (id_cmd==ID_RET)     NextState  = `RET;
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                else                         NextState  = `IDLE;
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            end
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            `NOI:
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            begin
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                if (id_cmd ==ID_NOI)         NextState  = `NOI;
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                else if (id_cmd==ID_CUR)     NextState  = `CUR;
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                else if (id_cmd==ID_MUL)     NextState  = `MUL;
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                else if (id_cmd==ID_LD)      NextState  = `LD;
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                else if (id_cmd==ID_RET)     NextState  = `RET;
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                else                         NextState  = `IDLE;
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            end
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            `CUR:   NextState  = `NOI;
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            `RET:   NextState  = `IDLE;
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            `IRQ:   NextState  = `IDLE;
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            `RST:   NextState  = `IDLE;
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            `LD:    NextState  = `IDLE;
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            `MUL:   NextState  = (delay_counter==32)?`IDLE:`MUL;
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            default NextState  =`IDLE;
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        endcase
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    end
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    always @ (*)/*Finite State Machine part3*/
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    begin
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        case (CurrState )
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            `IDLE: begin id2ra_ins_clr  =  1'b0;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b0;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr   =  1'b0;
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                pc_prectl=PC_IGN;
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                zz_is_nop = 0;end
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      `MUL:  begin
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                id2ra_ins_clr  =  1'b1;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b1;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr  =  1'b0;
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                pc_prectl =PC_KEP;
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                zz_is_nop =0; end
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      `CUR:  begin
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                id2ra_ins_clr  =  1'b0;
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                id2ra_ins_cls  =  1'b1;
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                id2ra_ctl_clr  =  1'b0;
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                id2ra_ctl_cls  =  1'b1;
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                ra2exec_ctl_clr  =  1'b1;
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                pc_prectl =PC_KEP;
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                zz_is_nop = 1; end
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      `RET: begin id2ra_ins_clr  =  1'b0;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b0;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr   =  1'b0;
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                pc_prectl =PC_IGN;
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                zz_is_nop = 1'b0;  end
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      `IRQ: begin
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                id2ra_ins_clr  =  1'b1;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b1;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr  =  1'b1;
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                pc_prectl =PC_IRQ;
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                zz_is_nop = 1'b0;end
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      `RST: begin
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                id2ra_ins_clr  =  1'b1;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b1;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr  =  1'b1;
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                pc_prectl=PC_RST;
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                zz_is_nop = 1'b1; end
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      `LD:begin
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                id2ra_ins_clr  =  1'b1;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b1;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr  =  1'b0;
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                pc_prectl =PC_KEP;
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                zz_is_nop = 1'b0;end
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      `NOI:begin
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                id2ra_ins_clr  =  1'b0;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b0;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr   =  1'b0;
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                pc_prectl=PC_IGN;
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                zz_is_nop = 1'b0;end
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      default   begin
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                id2ra_ins_clr  =  1'b1;
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                id2ra_ins_cls  =  1'b0;
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                id2ra_ctl_clr  =  1'b1;
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                id2ra_ctl_cls  =  1'b0;
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                ra2exec_ctl_clr  =  1'b1;
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                pc_prectl=PC_RST;
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                zz_is_nop = 1'b1;end
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      endcase
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    end
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endmodule
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