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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: apbctrl
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-- File: apbctrl.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: AMBA AHB/APB bridge with plug&play support
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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-- pragma translate_off
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use grlib.devices.all;
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use std.textio.all;
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-- pragma translate_on
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entity apbctrl is
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generic (
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hindex : integer := 0;
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haddr : integer := 0;
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hmask : integer := 16#fff#;
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nslaves : integer range 1 to NAPBSLV := NAPBSLV;
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debug : integer range 0 to 2 := 2;
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icheck : integer range 0 to 1 := 1;
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enbusmon : integer range 0 to 1 := 0;
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asserterr : integer range 0 to 1 := 0;
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assertwarn : integer range 0 to 1 := 0;
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pslvdisable : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbi : in ahb_slv_in_type;
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ahbo : out ahb_slv_out_type;
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apbi : out apb_slv_in_type;
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apbo : in apb_slv_out_vector
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);
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end;
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architecture rtl of apbctrl is
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constant apbmax : integer := 19;
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constant VERSION : amba_version_type := 0;
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constant hconfig : ahb_config_type := (
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4 => ahb_membar(haddr, '0', '0', hmask),
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others => zero32);
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constant IOAREA : std_logic_vector(11 downto 0) :=
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conv_std_logic_vector(haddr, 12);
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constant IOMSK : std_logic_vector(11 downto 0) :=
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conv_std_logic_vector(hmask, 12);
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type reg_type is record
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haddr : std_logic_vector(apbmax downto 0); -- address bus
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hwrite : std_logic; -- read/write
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hready : std_logic; -- ready
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penable : std_logic;
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psel : std_logic;
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prdata : std_logic_vector(31 downto 0); -- read data
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pwdata : std_logic_vector(31 downto 0); -- write data
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state : std_logic_vector(1 downto 0); -- state
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cfgsel : std_ulogic;
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end record;
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signal r, rin : reg_type;
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--pragma translate_off
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signal lapbi : apb_slv_in_type;
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--pragma translate_on
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begin
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comb : process(ahbi, apbo, r, rst)
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variable v : reg_type;
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variable psel : std_logic_vector(0 to 31);
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variable pwdata : std_logic_vector(31 downto 0);
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variable apbaddr : std_logic_vector(apbmax downto 0);
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variable apbaddr2 : std_logic_vector(31 downto 0);
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variable hirq, pirq : std_logic_vector(NAHBIRQ-1 downto 0);
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variable nslave : integer range 0 to nslaves-1;
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variable bnslave : std_logic_vector(3 downto 0);
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begin
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v := r; v.psel := '0'; v.penable := '0'; psel := (others => '0');
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hirq := (others => '0'); pirq := (others => '0');
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-- detect start of cycle
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if (ahbi.hready = '1') then
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if ((ahbi.htrans = HTRANS_NONSEQ) or (ahbi.htrans = HTRANS_SEQ)) and
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(ahbi.hsel(hindex) = '1')
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then
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v.hready := '0'; v.hwrite := ahbi.hwrite;
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v.haddr(apbmax downto 0) := ahbi.haddr(apbmax downto 0);
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v.state := "01"; v.psel := not ahbi.hwrite;
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end if;
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end if;
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case r.state is
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when "00" => null; -- idle
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when "01" =>
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if r.hwrite = '0' then v.penable := '1';
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else v.pwdata := ahbi.hwdata; end if;
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v.psel := '1'; v.state := "10";
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when others =>
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if r.penable = '0' then v.psel := '1'; v.penable := '1'; end if;
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v.state := "00"; v.hready := '1';
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end case;
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psel := (others => '0');
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for i in 0 to nslaves-1 loop
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if ((apbo(i).pconfig(1)(1 downto 0) = "01") and
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((apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4)) =
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(r.haddr(19 downto 8) and apbo(i).pconfig(1)(15 downto 4))))
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then psel(i) := '1'; end if;
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end loop;
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bnslave(0) := psel(1) or psel(3) or psel(5) or psel(7) or
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psel(9) or psel(11) or psel(13) or psel(15);
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bnslave(1) := psel(2) or psel(3) or psel(6) or psel(7) or
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psel(10) or psel(11) or psel(14) or psel(15);
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bnslave(2) := psel(4) or psel(5) or psel(6) or psel(7) or
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psel(12) or psel(13) or psel(14) or psel(15);
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bnslave(3) := psel(8) or psel(9) or psel(10) or psel(11) or
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psel(12) or psel(13) or psel(14) or psel(15);
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nslave := conv_integer(bnslave);
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if (r.haddr(19 downto 12) = "11111111") then
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v.cfgsel := '1'; psel := (others => '0'); v.penable := '0';
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else v.cfgsel := '0'; end if;
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v.prdata := apbo(nslave).prdata;
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if r.cfgsel = '1' then
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v.prdata := apbo(conv_integer(r.haddr(log2x(nslaves)+2 downto 3))).pconfig(conv_integer(r.haddr(2 downto 2)));
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end if;
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for i in 0 to nslaves-1 loop pirq := pirq or apbo(i).pirq; end loop;
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-- AHB respons
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ahbo.hready <= r.hready;
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ahbo.hrdata <= r.prdata;
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ahbo.hirq <= pirq;
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if rst = '0' then
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v.penable := '0'; v.hready := '1'; v.psel := '0'; v.state := "00";
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v.hwrite := '0';
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-- pragma translate_off
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v.haddr := (others => '0');
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-- pragma translate_on
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end if;
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rin <= v;
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-- drive APB bus
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apbaddr2 := (others => '0');
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apbaddr2(apbmax downto 0) := r.haddr(apbmax downto 0);
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apbi.paddr <= apbaddr2;
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apbi.pwdata <= r.pwdata;
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apbi.pwrite <= r.hwrite;
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apbi.penable <= r.penable;
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apbi.pirq <= ahbi.hirq;
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apbi.testen <= ahbi.testen;
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apbi.testoen <= ahbi.testoen;
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apbi.scanen <= ahbi.scanen;
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apbi.testrst <= ahbi.testrst;
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for i in 0 to nslaves-1 loop apbi.psel(i) <= psel(i) and r.psel; end loop;
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--pragma translate_off
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lapbi.paddr <= apbaddr2;
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lapbi.pwdata <= r.pwdata;
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lapbi.pwrite <= r.hwrite;
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lapbi.penable <= r.penable;
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lapbi.pirq <= ahbi.hirq;
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for i in 0 to nslaves-1 loop lapbi.psel(i) <= psel(i) and r.psel; end loop;
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--pragma translate_on
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end process;
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ahbo.hindex <= hindex;
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ahbo.hconfig <= hconfig;
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ahbo.hcache <= '0';
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ahbo.hsplit <= (others => '0');
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ahbo.hresp <= HRESP_OKAY;
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reg : process(clk)
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begin if rising_edge(clk) then r <= rin; end if; end process;
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-- pragma translate_off
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mon0 : if enbusmon /= 0 generate
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mon : apbmon
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generic map(
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asserterr => asserterr,
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assertwarn => assertwarn,
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pslvdisable => pslvdisable,
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napb => nslaves)
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port map(
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rst => rst,
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clk => clk,
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apbi => lapbi,
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apbo => apbo,
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err => open);
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end generate;
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diag : process
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variable k : integer;
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variable mask : std_logic_vector(11 downto 0);
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variable device : std_logic_vector(11 downto 0);
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variable devicei : integer;
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variable vendor : std_logic_vector( 7 downto 0);
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variable vendori : integer;
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variable iosize : integer;
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variable iounit : string(1 to 5) := "byte ";
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variable memstart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
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variable L1 : line := new string'("");
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begin
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wait for 3 ns;
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if debug = 0 then wait; end if;
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print("apbctrl: APB Bridge at " & tost(memstart) & "00000 rev 1");
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if debug = 1 then wait; end if;
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for i in 0 to nslaves-1 loop
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vendor := apbo(i).pconfig(0)(31 downto 24);
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vendori := conv_integer(vendor);
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if vendori /= 0 then
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device := apbo(i).pconfig(0)(23 downto 12);
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devicei := conv_integer(device);
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std.textio.write(L1, "apbctrl: slv" & tost(i) & ": " &
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iptable(vendori).vendordesc & iptable(vendori).device_table(devicei));
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std.textio.writeline(OUTPUT, L1);
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mask := apbo(i).pconfig(1)(15 downto 4);
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k := 0;
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while (k<15) and (mask(k) = '0') loop k := k+1; end loop;
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iosize := 256 * 2**k; iounit := "byte ";
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if (iosize > 1023) then iosize := iosize/1024; iounit := "kbyte"; end if;
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print("apbctrl: I/O ports at " &
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tost(memstart & (apbo(i).pconfig(1)(31 downto 20) and apbo(i).pconfig(1)(15 downto 4))) &
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"00, size " & tost(iosize) & " " & iounit);
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assert (apbo(i).pindex = i) or (icheck = 0)
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report "APB slave index error on slave " & tost(i) severity failure;
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end if;
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end loop;
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wait;
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end process;
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-- pragma translate_on
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end;
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