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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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--============================================================================--
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-- Design unit : DMA2AHB (Entity & architecture declarations)
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--
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-- File name : dma2ahb.vhd
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--
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-- Purpose : AMBA AHB master interface with DMA input
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--
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-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
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-- 13th May 1999, issue A, first release, ARM Limited
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-- The document can be retrieved from http://www.arm.com
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-- AMBA is a trademark of ARM Limited.
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-- ARM is a registered trademark of ARM Limited.
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--
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-- Note : Naming convention according to AMBA(TM) Specification:
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-- Signal names are in upper case, except for the following:
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-- A lower case 'n' in the name indicates that the signal
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-- is active low.
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-- Constant names are in upper case.
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-- The least significant bit of an array is located to the right,
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-- carrying the index number zero.
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--
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-- Limitations : The AMBA AHB interface has been reduced in function to support
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-- only what is required. The following features are constrained:
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-- Optionally generates HSIZE=BYTE, HWORD and WORD
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-- Only generates HPROT="0000"
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-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
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-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
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--
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-- Generates the following on reponses on DMA interface:
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-- HRESP=HRESP_OKAY => DMAOut.Ready
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-- HRESP=HRESP_ERROR => DMAOut.Fault
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-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
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-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
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--
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-- Assumes pipelined data input (after OKAY asserted).
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--
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-- Only big-endianness is supported.
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--
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-- Supports Early Bus Termination with automatic restart.
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-- Supports Retry/Split with automatic restart.
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--
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-- Library : gaisler
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--
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-- Authors : Mr Sandi Habinc
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-- Gaisler Research AB
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-- Forsta Langgatan 19
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-- SE-413 27 Göteborg
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-- Sweden
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--
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-- Contact : mailto:sandi@gaisler.com
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-- http://www.gaisler.com
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--
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-- Disclaimer : All information is provided "as is", there is no warranty that
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-- the information is correct or suitable for any purpose,
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-- neither implicit nor explicit.
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--
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--------------------------------------------------------------------------------
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-- Version Author Date Changes
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--
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-- 0.1 SH 1 Jul 2003 New version
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-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
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-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
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-- (early burst termination)
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-- Optimised coding
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-- Idle transfer initiated in 1st error phase
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-- 1.3 SH 1 Oct 2004 Ported to GRLIB
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-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
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-- Support for record types
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-- 1.5 SH 1 Sep 2005 New library gaisler
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-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
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-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
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-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
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-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
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-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
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-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
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-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
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-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
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-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
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-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
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-- 1.9.7 MI 4 Aug 2008 Support for Lock
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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library GRLIB;
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use GRLIB.AMBA.all;
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use GRLIB.STDLIB.all;
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use GRLIB.DMA2AHB_Package.all;
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entity DMA2AHB is
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generic(
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hindex: in Integer := 0;
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vendorid: in Integer := 0;
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deviceid: in Integer := 0;
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version: in Integer := 0;
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syncrst: in Integer := 1;
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boundary: in Integer := 1);
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port(
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-- AMBA AHB system signals
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HCLK: in Std_ULogic; -- system clock
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HRESETn: in Std_ULogic; -- asynchronous reset
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-- Direct Memory Access Interface
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DMAIn: in DMA_In_Type;
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DMAOut: out DMA_OUt_Type;
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-- AMBA AHB Master Interface
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AHBIn: in AHB_Mst_In_Type;
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AHBOut: out AHB_Mst_Out_Type);
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end entity DMA2AHB;
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--============================== Architecture ================================--
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architecture RTL of DMA2AHB is
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--=========================================================================--
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-- Configuration GRLIB
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-----------------------------------------------------------------------------
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constant HConfig: AHB_Config_Type := (
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others => (others => '0'));
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--=========================================================================--
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-----------------------------------------------------------------------------
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-- Local signals
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-----------------------------------------------------------------------------
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signal Address: Std_Logic_Vector(31 downto 0);
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signal AddressSave: Std_Logic_Vector(31 downto 0);
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signal ActivePhase: Std_ULogic; -- ongoing access
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signal AddressPhase: Std_ULogic; -- address phase
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signal DataPhase: Std_ULogic; -- data phase
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signal ReDataPhase: Std_ULogic; -- restart first
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signal ReAddrPhase: Std_ULogic; -- restart second
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signal IdlePhase: Std_ULogic; -- idle phase
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signal EarlyPhase: Std_ULogic; -- early termination
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signal BoundaryPhase: Std_ULogic; -- boundary crossing
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signal SingleAcc: Std_ULogic; -- single access
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signal WriteAcc: Std_ULogic; -- write access
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signal DelDataPhase: Std_ULogic; -- restart first
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signal DelAddrPhase: Std_ULogic; -- restart second
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signal AHBInHGRANTx: Std_ULogic; -- decoded grant
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begin
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--=========================================================================--
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-- AMBA AHB master interface
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-----------------------------------------------------------------------------
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AHBOut.HIRQ <= (others => '0');
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AHBOut.HCONFIG <= HConfig;
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AHBOut.HINDEX <= hindex;
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AHBInHGRANTx <= AHBIn.HGRANT(hindex);
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--=========================================================================--
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-----------------------------------------------------------------------------
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-- AMBA AHB Master interface with fast issuing of accesses
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Fixed AMBA AHB signals
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-----------------------------------------------------------------------------
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AHBOut.HPROT <= (others => '0');
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-----------------------------------------------------------------------------
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-- Combinatorial paths
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-----------------------------------------------------------------------------
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AHBOut.HADDR <= Address; -- internal to external
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AHBOut.HWDATA <= DMAIn.Data; -- combinatorial path
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DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
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DataPhase ='1' and
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AHBIN.HRESP=HRESP_OKAY else
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'0';
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DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
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DataPhase ='1' and
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(AHBIN.HRESP=HRESP_RETRY or
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AHBIN.HRESP=HRESP_SPLIT) else
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'0';
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DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
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DataPhase ='1' and
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AHBIN.HRESP=HRESP_ERROR else
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'0';
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DMAOut.Grant <= '0' when DelDataPhase='1' or ReDataPhase='1' else
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'1' when AHBIn.HREADY='1' and
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AHBInHGRANTx='1' and
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DMAIn.Request='1' else
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'0';
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AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
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'1' when DMAIn.Request='1' else
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'1' when DMAIn.Burst='1' else
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'1' when ReDataPhase='1' else
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'1' when ReAddrPhase='1' else
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'0';
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AHBOut.HLOCK <= '0' when IdlePhase='1' else
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'1' when (DMAIn.Lock and
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(DMAIn.Request or ReDataPhase)) = '1'else
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'0';
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-----------------------------------------------------------------------------
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-- The AMBA AHB interfacing is done in this process
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-----------------------------------------------------------------------------
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AHBMaster: process(HCLK, HRESETn)
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variable BoundaryCrossing: Std_ULogic;
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variable AddressInc: Std_Logic_Vector(3 downto 0);
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--------------------------------------------------------------------------
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-- This procedure is used to define all reset values for the
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-- asynchronous or synchronous reset statements in this process. This
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-- is done to avoid source code duplication.
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--------------------------------------------------------------------------
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procedure Reset is
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begin
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ActivePhase <= '0';
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EarlyPhase <= '0';
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AddressPhase <= '0';
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DataPhase <= '0';
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ReDataPhase <= '0';
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ReAddrPhase <= '0';
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DelDataPhase <= '0';
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DelAddrPhase <= '0';
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BoundaryPhase <= '0';
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IdlePhase <= '0';
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EarlyPhase <= '0';
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SingleAcc <= '0';
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WriteAcc <= '0';
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Address <= (others => '0');
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AddressSave <= (others => '0');
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DMAOut.Ready <= '0';
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DMAOut.Data <= (others => '0');
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AHBOut.HSIZE <= HSIZE_BYTE;
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AHBOut.HBURST <= HBURST_SINGLE;
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AHBOut.HTRANS <= HTRANS_IDLE;
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AHBOut.HWRITE <= '0';
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end Reset; ---------------------------------------------------------------
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begin
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if HRESETn='0' and syncrst=0 then -- asynchronous reset
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Reset;
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elsif Rising_Edge(HCLK) then
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if DMAIn.Reset='1' or -- functional reset
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(syncrst/=0 and HRESETn='0') then -- synchronous reset
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Reset;
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else -- no reset
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--------------------------------------------------------------------
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-- Temporary variables
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--------------------------------------------------------------------
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BoundaryCrossing := '0';
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AddressInc := (others => '0');
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--------------------------------------------------------------------
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-- AMBA AHB interface - data phase handling
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--------------------------------------------------------------------
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-- indicate when no more activies are pending
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if AddressPhase='0' and DataPhase='0' and
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ReDataPhase='0' and ReAddrPhase='0' and
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DMAIn.Burst='0' then
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ActivePhase <= '0';
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end if;
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if AHBIn.HREADY='0' and DataPhase='1' then
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-- error check
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if AHBIN.HRESP=HRESP_ERROR then
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DataPhase <= '0'; -- data phase aborted
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end if;
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-- split or retry check
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if AHBIN.HRESP=HRESP_SPLIT or
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AHBIN.HRESP=HRESP_RETRY then
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ReDataPhase <= DataPhase; -- restart phases
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ReAddrPhase <= AddressPhase or ReAddrPhase;
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AddressPhase <= '0'; -- addr phase aborted
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DataPhase <= '0'; -- data phase aborted
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-- go back with address
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if boundary=1 then
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Address <= AddressSave;
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else
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Address(9 downto 0) <= AddressSave(9 downto 0);
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end if;
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if DMAIn.Size=HSIZE8 then
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AHBOut.HSIZE <= HSIZE_BYTE;
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elsif DMAIn.Size=HSIZE16 then
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AHBOut.HSIZE <= HSIZE_HWORD;
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else
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AHBOut.HSIZE <= HSIZE_WORD;
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end if;
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end if;
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end if;
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322 |
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if AHBIn.HREADY='1' and DataPhase='1' then
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-- sample AHB input data at end of data phase
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DMAOut.Data <= AHBIn.HRDATA;
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DataPhase <= '0'; -- data phase ends
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DMAOut.Ready <= '1';
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else
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-- remove acknowledgement after one cycle
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DMAOut.Ready <= '0';
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end if;
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--------------------------------------------------------------------
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334 |
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-- AMBA AHB interface - address phase handling
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335 |
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--------------------------------------------------------------------
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336 |
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-- initialize data phase on AHB after previous address phase
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337 |
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if AddressPhase='1' and AHBIn.HREADY='1' then
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DataPhase <= '1'; -- data phase start
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end if;
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340 |
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341 |
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-- address generation on AHB
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342 |
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if AHBIn.HREADY='1' then
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if AddressPhase='1' then
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-- burst continuation, sequential transfer
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345 |
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AddressInc(conv_integer(DMAIn.Size)) := '1';
|
346 |
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if boundary=1 then -- automatic boundary
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Address <= Address + AddressInc;
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AddressSave <= Address;
|
349 |
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if Address(9 downto 2)="11111111" then
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BoundaryCrossing := '1';
|
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BoundaryPhase <= '1';
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end if;
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353 |
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else
|
354 |
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Address(31 downto 10) <= DMAIn.Address(31 downto 10);
|
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Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
|
356 |
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AddressSave(9 downto 0) <= Address(9 downto 0);
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357 |
|
|
end if;
|
358 |
|
|
if DMAIn.Size=HSIZE8 then
|
359 |
|
|
AHBOut.HSIZE <= HSIZE_BYTE;
|
360 |
|
|
elsif DMAIn.Size=HSIZE16 then
|
361 |
|
|
AHBOut.HSIZE <= HSIZE_HWORD;
|
362 |
|
|
else
|
363 |
|
|
AHBOut.HSIZE <= HSIZE_WORD;
|
364 |
|
|
end if;
|
365 |
|
|
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
|
366 |
|
|
-- start of burst, non-sequential transfer
|
367 |
|
|
-- start of single, non-sequential transfer
|
368 |
|
|
if boundary=1 then -- automatic boundary
|
369 |
|
|
Address <= DMAIn.Address;
|
370 |
|
|
AddressSave <= DMAIn.Address;
|
371 |
|
|
BoundaryCrossing := '0';
|
372 |
|
|
BoundaryPhase <= '0';
|
373 |
|
|
else
|
374 |
|
|
Address <= DMAIn.Address;
|
375 |
|
|
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
|
376 |
|
|
end if;
|
377 |
|
|
|
378 |
|
|
if DMAIn.Size=HSIZE8 then
|
379 |
|
|
AHBOut.HSIZE <= HSIZE_BYTE;
|
380 |
|
|
elsif DMAIn.Size=HSIZE16 then
|
381 |
|
|
AHBOut.HSIZE <= HSIZE_HWORD;
|
382 |
|
|
else
|
383 |
|
|
AHBOut.HSIZE <= HSIZE_WORD;
|
384 |
|
|
end if;
|
385 |
|
|
end if;
|
386 |
|
|
end if;
|
387 |
|
|
|
388 |
|
|
-- address generation on AHB
|
389 |
|
|
if AHBIn.HREADY='1' then
|
390 |
|
|
IdlePhase <= '0'; -- one clock cycle only
|
391 |
|
|
end if;
|
392 |
|
|
|
393 |
|
|
-- initialize address phase on AHB
|
394 |
|
|
if AHBIn.HREADY='1' then
|
395 |
|
|
-- granted the AHB bus
|
396 |
|
|
if AHBInHGRANTx='1' then
|
397 |
|
|
if ReDataPhase='1' then
|
398 |
|
|
ReDataPhase <= '0';
|
399 |
|
|
AddressPhase <= '1'; -- address phase start
|
400 |
|
|
EarlyPhase <= '0';
|
401 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
402 |
|
|
if SingleAcc='1' then
|
403 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
404 |
|
|
else
|
405 |
|
|
AHBOut.HBURST <= HBURST_INCR;
|
406 |
|
|
end if;
|
407 |
|
|
AHBOut.HWRITE <= WriteAcc;
|
408 |
|
|
|
409 |
|
|
elsif ReAddrPhase='1' then
|
410 |
|
|
AddressPhase <= '1'; -- address phase start
|
411 |
|
|
ReAddrPhase <= '0';
|
412 |
|
|
if AddressPhase='1' then
|
413 |
|
|
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
|
414 |
|
|
-- new bursts, non-sequential transfer
|
415 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
416 |
|
|
BoundaryPhase <= '0';
|
417 |
|
|
else
|
418 |
|
|
-- burst continuation, sequential transfer
|
419 |
|
|
AHBOut.HTRANS <= HTRANS_SEQ;
|
420 |
|
|
end if;
|
421 |
|
|
else
|
422 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
423 |
|
|
end if;
|
424 |
|
|
EarlyPhase <= '0';
|
425 |
|
|
if SingleAcc='1' then
|
426 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
427 |
|
|
else
|
428 |
|
|
AHBOut.HBURST <= HBURST_INCR;
|
429 |
|
|
end if;
|
430 |
|
|
AHBOut.HWRITE <= WriteAcc;
|
431 |
|
|
|
432 |
|
|
elsif EarlyPhase='1' then
|
433 |
|
|
-- early terminated burst resumed
|
434 |
|
|
AddressPhase <= '1'; -- address phase start
|
435 |
|
|
EarlyPhase <= '0';
|
436 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
437 |
|
|
AHBOut.HBURST <= HBURST_INCR;
|
438 |
|
|
AHBOut.HWRITE <= WriteAcc;
|
439 |
|
|
|
440 |
|
|
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
|
441 |
|
|
AddressPhase <= '1'; -- address phase start
|
442 |
|
|
if ActivePhase='1' then
|
443 |
|
|
-- burst continuation, sequential transfer
|
444 |
|
|
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
|
445 |
|
|
-- new bursts, non-sequential transfer
|
446 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
447 |
|
|
BoundaryPhase <= '0';
|
448 |
|
|
else
|
449 |
|
|
-- burst continuation, sequential transfer
|
450 |
|
|
AHBOut.HTRANS <= HTRANS_SEQ;
|
451 |
|
|
end if;
|
452 |
|
|
else
|
453 |
|
|
-- start of burst, non-sequential transfer
|
454 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
455 |
|
|
if DMAIn.Beat ="00" then
|
456 |
|
|
AHBOut.HBURST <= HBURST_INCR;
|
457 |
|
|
elsif DMAIn.Beat ="01" then
|
458 |
|
|
AHBOut.HBURST <= HBURST_INCR4;
|
459 |
|
|
elsif DMAIn.Beat ="10" then
|
460 |
|
|
AHBOut.HBURST <= HBURST_INCR8;
|
461 |
|
|
else
|
462 |
|
|
AHBOut.HBURST <= HBURST_INCR16;
|
463 |
|
|
end if;
|
464 |
|
|
AHBOut.HWRITE <= DMAIn.Store;
|
465 |
|
|
ActivePhase <= '1';
|
466 |
|
|
SingleAcc <= '0';
|
467 |
|
|
WriteAcc <= DMAIn.Store;
|
468 |
|
|
end if;
|
469 |
|
|
|
470 |
|
|
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
|
471 |
|
|
-- burst in wait state
|
472 |
|
|
AddressPhase <= '0'; -- no address phase
|
473 |
|
|
AHBOut.HTRANS <= HTRANS_BUSY;
|
474 |
|
|
|
475 |
|
|
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
|
476 |
|
|
-- start of single, non-sequential transfer
|
477 |
|
|
AddressPhase <= '1'; -- address phase start
|
478 |
|
|
ActivePhase <= '1';
|
479 |
|
|
SingleAcc <= '1';
|
480 |
|
|
WriteAcc <= DMAIn.Store;
|
481 |
|
|
AHBOut.HTRANS <= HTRANS_NONSEQ;
|
482 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
483 |
|
|
AHBOut.HWRITE <= DMAIn.Store;
|
484 |
|
|
else
|
485 |
|
|
-- drive idle transfer as default master
|
486 |
|
|
-- the next cycle will start the address phase
|
487 |
|
|
AddressPhase <= '0'; -- no useful address
|
488 |
|
|
AHBOut.HTRANS <= HTRANS_IDLE;
|
489 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
490 |
|
|
AHBOut.HWRITE <= '0';
|
491 |
|
|
end if;
|
492 |
|
|
|
493 |
|
|
-- not granted the AHB bus, but early burst termination
|
494 |
|
|
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
|
495 |
|
|
-- must restart a burst transfer since grant removed
|
496 |
|
|
AddressPhase <= '0'; -- no address phase
|
497 |
|
|
EarlyPhase <= '1';
|
498 |
|
|
AHBOut.HTRANS <= HTRANS_IDLE;
|
499 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
500 |
|
|
AHBOut.HWRITE <= '0';
|
501 |
|
|
|
502 |
|
|
-- not granted the AHB bus
|
503 |
|
|
else
|
504 |
|
|
-- drive idle transfer as default master
|
505 |
|
|
-- the next cycle will start the address phase
|
506 |
|
|
AddressPhase <= '0'; -- no useful address
|
507 |
|
|
AHBOut.HTRANS <= HTRANS_IDLE;
|
508 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
509 |
|
|
AHBOut.HWRITE <= '0';
|
510 |
|
|
end if;
|
511 |
|
|
|
512 |
|
|
elsif AHBIn.HREADY='0' and DataPhase='1' then
|
513 |
|
|
if AHBIN.HRESP=HRESP_ERROR or
|
514 |
|
|
AHBIN.HRESP=HRESP_SPLIT or
|
515 |
|
|
AHBIN.HRESP=HRESP_RETRY then
|
516 |
|
|
-- drive idle transfer due to error, retry or split
|
517 |
|
|
-- the next cycle will start the address phase
|
518 |
|
|
AddressPhase <= '0'; -- no useful address
|
519 |
|
|
IdlePhase <= '1';
|
520 |
|
|
AHBOut.HTRANS <= HTRANS_IDLE;
|
521 |
|
|
AHBOut.HBURST <= HBURST_SINGLE;
|
522 |
|
|
AHBOut.HWRITE <= '0';
|
523 |
|
|
end if;
|
524 |
|
|
end if;
|
525 |
|
|
end if;
|
526 |
|
|
|
527 |
|
|
if AHBIn.HREADY='1' then -- delay one phase
|
528 |
|
|
DelDataPhase <= ReDataPhase;
|
529 |
|
|
DelAddrPhase <= ReAddrPhase;
|
530 |
|
|
end if;
|
531 |
|
|
|
532 |
|
|
-- temporary variables cleared
|
533 |
|
|
BoundaryCrossing := '0';
|
534 |
|
|
AddressInc := (others => '0');
|
535 |
|
|
else
|
536 |
|
|
null;
|
537 |
|
|
end if;
|
538 |
|
|
end process AHBMaster;
|
539 |
|
|
end architecture RTL; --======================================================--
|
540 |
|
|
|