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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gsi/] [ssram/] [g880e18bt.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 dimamali 
--      Copyright 2000. GSI Technology
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--                                              GSI Appications
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--                                              apps@gsitechnology.com
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--  v 1.0 4/23/2002 Jeff Duagherty  1) based on G16272
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY G880E18BT IS
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  GENERIC (
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    CONSTANT A_size      : integer := 19;
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    CONSTANT DQ_size     : integer := 9;
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    CONSTANT bank_size   : integer := 1024 * 512;-- *8M /4 bytes in parallel
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--250MHZ
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--    CONSTANT tKQpipe     : time    := 2.5 ns ;
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--    CONSTANT tKQflow     : time    := 5.5 ns ;
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--    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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--    CONSTANT tKQXflow     : time    := 3.0 ns );
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--225MHZ
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--    CONSTANT tKQpipe     : time    := 2.7 ns ;
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--    CONSTANT tKQflow     : time    := 6.0 ns ;
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--    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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--    CONSTANT tKQXflow     : time    := 3.0 ns );
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--200MHZ
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--    CONSTANT tKQpipe     : time    := 3.0 ns ;
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--    CONSTANT tKQflow     : time    := 6.5 ns ;
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--    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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--    CONSTANT tKQXflow     : time    := 3.0 ns );
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--166MHZ
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    CONSTANT tKQpipe     : time    := 3.4 ns ;
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    CONSTANT tKQflow     : time    := 7.0 ns ;
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    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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    CONSTANT tKQXflow     : time    := 3.0 ns );
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--150MHZ
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--    CONSTANT tKQpipe     : time    := 3.8 ns ;
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--    CONSTANT tKQflow     : time    := 6.7 ns ;
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--    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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--    CONSTANT tKQXflow     : time    := 3.0 ns );
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--133MHZ
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--    CONSTANT tKQpipe     : time    := 4.0 ns ;
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--    CONSTANT tKQflow     : time    := 8.5 ns ;
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--    CONSTANT tKQXpipe     : time    := 1.5 ns ;
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--    CONSTANT tKQXflow     : time    := 3.0 ns );
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  PORT (
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    SIGNAL A88   : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
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    SIGNAL DQa   : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte A data
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    SIGNAL DQb   : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte B data
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    SIGNAL nBa   : IN std_logic;-- bank A write enable
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    SIGNAL nBb   : IN std_logic;-- bank B write enable
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    SIGNAL CK    : IN std_logic;-- clock
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    SIGNAL nBW   : IN std_logic;-- byte write enable
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    SIGNAL nGW   : IN std_logic;-- Global write enable
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    SIGNAL nE1   : IN std_logic;-- chip enable 1
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    SIGNAL E2    : IN std_logic;-- chip enable 1
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    SIGNAL nE3   : IN std_logic;-- chip enable 1
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    SIGNAL nG    : IN std_logic;-- output enable
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    SIGNAL nADV  : IN std_logic;-- Advance not / load
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    SIGNAL nADSC : IN std_logic;      -- ONLY FOR BURST DEVICES
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    SIGNAL nADSP : IN std_logic;      -- ONLY FOR BURST DEVICES
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    SIGNAL ZZ    : IN std_logic;-- power down
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    SIGNAL nFT   : IN std_logic;-- Pipeline / Flow through
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    SIGNAL nLBO  : IN std_logic);-- Linear Burst Order not
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END G880E18BT;
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LIBRARY GSI;
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LIBRARY Std;
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ARCHITECTURE BURST_8MEG_x18 OF G880E18BT IS
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  USE GSI.FUNCTIONS.ALL;
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  USE Std.textio.ALL;
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  component VHDL_BURST_CORE
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    generic (
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      CONSTANT bank_size   : integer := 1024 * 512;-- *8M /4 bytes in parallel
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      CONSTANT A_size      : integer := 19;
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      CONSTANT DQ_size     : integer := 9);
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    port (
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      signal       A           : in    std_logic_vector(A_size - 1 downto 0);  -- address
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      signal       DQa         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte A data
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      signal       DQb         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte B data
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      signal       DQc         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte C data
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      signal       DQd         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte D data
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      signal       DQe         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte E data
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      signal       DQf         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte F data
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      signal       DQg         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte G data
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      signal       DQh         : inout std_logic_vector(DQ_size downto 1) bus;  -- byte H data
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      signal       nBa         : in    std_logic;  -- bank A write enable
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      signal       nBb         : in    std_logic;  -- bank B write enable
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      signal       nBc         : in    std_logic;  -- bank C write enable
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      signal       nBd         : in    std_logic;  -- bank D write enable
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      signal       nBe         : in    std_logic;
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      signal       nBf         : in    std_logic;
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      signal       nBg         : in    std_logic;
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      signal       nBh         : in    std_logic;
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      signal       CK          : in    std_logic;  -- clock
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      signal       nBW         : in    std_logic;  -- byte write enable
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      signal       nGW         : in    std_logic;  -- Global write enable
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      signal       nE1         : in    std_logic;  -- chip enable 1
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      signal       E2          : in    std_logic;  -- chip enable 2
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      signal       nE3         : in    std_logic;  -- chip enable 3
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      signal       nG          : in    std_logic;  -- output enable
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      signal       nADV        : in    std_logic;  -- Advance not / load
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      signal       nADSC       : in    std_logic;  -- ONLY FOR BURST DEVICES
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      signal       nADSP       : in    std_logic;  -- ONLY FOR BURST DEVICES
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      signal       ZZ          : in    std_logic;  -- power down
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      signal       nFT         : in    std_logic;  -- Pipeline / Flow through
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      signal       nLBO        : in    std_logic;  -- Linear Burst Order not
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      signal       SCD         : in    std_logic;  -- ONLY FOR BURST DEVICES
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      SIGNAL       HighZ       : std_logic_vector(DQ_size downto 1) ;
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      signal       tKQ         :       time;
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      signal       tKQX         :       time);
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  end component;
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  SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
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  SIGNAL nBc   : std_logic := '1';
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  SIGNAL nBd   : std_logic := '1';
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  SIGNAL nBe   : std_logic := '1';
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  SIGNAL nBf   : std_logic := '1';
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  SIGNAL nBg   : std_logic := '1';
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  SIGNAL nBh   : std_logic := '1';
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  SIGNAL SCD   : std_logic := '0';-- ONLY FOR BURST DEVICES
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  SIGNAL DQc   : std_logic_vector(DQ_size DOWNTO 1);-- byte C data
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  SIGNAL DQd   : std_logic_vector(DQ_size DOWNTO 1);-- byte D data
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  SIGNAL DQe   : std_logic_vector(DQ_size DOWNTO 1);-- byte E data
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  SIGNAL DQf   : std_logic_vector(DQ_size DOWNTO 1);-- byte F data
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  SIGNAL DQg   : std_logic_vector(DQ_size DOWNTO 1);-- byte G data
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  SIGNAL DQh   : std_logic_vector(DQ_size DOWNTO 1);-- byte H data
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  signal A     : std_logic_vector(A_size - 1 downto 0);
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  signal tKQ   : time;
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  signal tKQX   : time;
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begin
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  tKQ <= TERNARY(nFT, tKQpipe, tKQflow);
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  tKQX <= TERNARY(nFT, tKQXpipe, tKQXflow);
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  HighZ <= to_stdlogicvector( "ZZZZZZZZZZ" ,DQ_size);
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  A     <= to_stdlogicvector(A88, A_size);
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  CORE_CALL : VHDL_BURST_CORE port map (
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    A, DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH, NBA, NBB, NBC, NBD, NBE, NBF, NBG, NBH, CK, NBW, NGW, NE1, E2, NE3, NG, NADV, NADSC, NADSP, ZZ, NFT, NLBO, SCD, HighZ, tKQ, tKQX);
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END BURST_8MEG_x18;

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