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dimamali |
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-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
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-- --
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-- VHDL Modeling --
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-- --
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-- PART : HY5PS121621F-B400/B533/B667/B800 --
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-- --
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-- HHHH HHHH --
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-- HHHH HHHH --
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-- ,O0O. ,O0 .HH ,O0 .HH --
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-- (O000O)(O00 )H(O00 )H --
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-- `O0O' `O0 'HH `O0 'HH --
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-- HHHH HHHH Hynix --
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-- HHHH HHHH Semiconductor --
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------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.all;
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library grlib;
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use grlib.stdlib.all;
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--USE IEEE.STD_LOGIC_ARITH.all;
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--USE IEEE.STD_LOGIC_UNSIGNED.all;
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USE work.HY5PS121621F_PACK.all;
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---------------------------------------------------------------------------------------------------
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Entity HY5PS121621F Is
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generic (
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TimingCheckFlag : boolean := TRUE;
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PUSCheckFlag : boolean := FALSE;
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Part_Number : PART_NUM_TYPE := B400);
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Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z');
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LDQS : inout std_logic := 'Z';
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LDQSB : inout std_logic := 'Z';
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UDQS : inout std_logic := 'Z';
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UDQSB : inout std_logic := 'Z';
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LDM : in std_logic;
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WEB : in std_logic;
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CASB : in std_logic;
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RASB : in std_logic;
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CSB : in std_logic;
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BA : in std_logic_vector(1 downto 0);
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ADDR : in std_logic_vector(12 downto 0);
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CKE : in std_logic;
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CLK : in std_logic;
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CLKB : in std_logic;
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UDM : in std_logic );
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End HY5PS121621F;
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-----------------------------------------------------------------------------------------------------
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Architecture Behavioral_Model_HY5PS121621F Of HY5PS121621F Is
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signal RD_PIPE_REG : std_logic_vector(6 downto 0) := "0000000";
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signal WT_PIPE_REG : std_logic_vector(12 downto 0) := "0000000000000";
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signal ADD_PIPE_REG : ADD_PIPE_TYPE;
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signal DLL_reset, DLL_lock_enable : std_logic := '0';
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signal yburst, RD_WR_ST, caspwt, casp6_rd, casp6_wt : std_logic := '0';
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signal casp_wtI, casp_wtII, wt_stdby : std_logic := '0';
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signal udspre_enable, ldspre_enable, udsh_dsl_enable, ldsh_dsl_enable : std_logic := '0';
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signal dq_bufferH, dq_bufferL : DATA_BUFFER_TYPE := ("0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ",
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"0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ");
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signal DQS_S : std_logic := 'Z';
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signal dqs_count : integer := 0;
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signal dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6 : std_logic := '0';
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signal cur_time : time := 0 ns;
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signal Ref_time, clk_cycle_rising : time := 0 ns;
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signal tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3 : std_logic := '0';
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signal mrs_cmd_in : std_logic := '0';
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signal CKEN : CKE_TYPE := (others => '0');
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signal CLK_DLY2, CLK_DLY1, CLK_DLY15 : std_logic := '0';
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signal tmp_ref_addr1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
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signal tmp_ref_addr2 : std_logic_vector((NUM_OF_ROW_ADD + 1) downto 0) := (others => '0');
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signal tmp_ref_addr3_B0 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
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signal tmp_ref_addr3_B1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
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signal tmp_ref_addr3_B2 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
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signal tmp_ref_addr3_B3 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0');
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signal tmp_ref_addr3_0, tmp_ref_addr3_1, tmp_ref_addr3_2, tmp_ref_addr3_3 : std_logic := '0';
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signal tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans : std_logic := '0';
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signal RefChkTimeInit : boolean := FALSE;
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signal refresh_check : REF_CHECK;
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signal real_col_addr : COL_ADDR_TYPE ;
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signal Read_CA, Write_CA : std_logic := '0';
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signal tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3 : std_logic := '0';
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signal RA_Activated_B0 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
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signal RA_Activated_B1 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
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signal RA_Activated_B2 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
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signal RA_Activated_B3 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U');
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signal SA_ARRAY : SA_ARRAY_TYPE;
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signal SA_ARRAY_A0 : SA_TYPE;
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signal SA_ARRAY_A1 : SA_TYPE;
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signal SA_ARRAY_A2 : SA_TYPE;
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signal SA_ARRAY_A3 : SA_TYPE;
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signal SA_ARRAY_W0 : SA_TYPE;
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signal SA_ARRAY_W1 : SA_TYPE;
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signal SA_ARRAY_W2 : SA_TYPE;
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signal SA_ARRAY_W3 : SA_TYPE;
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signal PcgPdExtFlag, ActPdExtFlag, SlowActPdExtFlag : boolean := FALSE;
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signal PUSPCGAFlag1, PUSPCGAFlag2 : boolean := FALSE;
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signal PUS_DLL_RESET : boolean := FALSE;
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signal ModeRegisterSetFlag : boolean := FALSE;
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signal ModeRegisterFlag : boolean := FALSE;
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signal BankActivateFlag : boolean := FALSE;
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signal BankActivateFinFlag : boolean := FALSE;
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signal BankActivatedFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0');
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signal PcgPdFlag, ReadFlag : boolean := FALSE;
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signal WriteFlag : boolean := FALSE;
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signal DataBuffer : BUFFER_TYPE;
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signal PrechargeFlag : boolean := FALSE;
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signal AutoPrechargeFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0');
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signal PrechargeFinFlag : boolean := FALSE;
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signal PrechargeAllFlag : boolean := FALSE;
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signal PrechargeAllFinFlag : boolean := FALSE;
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signal ReadFinFlag : boolean := FALSE;
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signal WriteFinFlag : boolean := FALSE;
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signal AutoRefFlag : boolean := FALSE;
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signal SelfRefFlag : boolean := FALSE;
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signal SelfRefExt2NRFlag, SelfRefExt2RDFlag : boolean := FALSE;
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signal PUSCheckFinFlag : boolean := FALSE;
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signal CurrentState : STATE_TYPE := PWRUP;
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signal ModeRegister : MODE_REGISTER := (
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CAS_LATENCY => 2,
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BURST_MODE => SEQUENTIAL,
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BURST_LENGTH => 4,
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DLL_STATE => NORST,
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SAPD => '0',
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TWR => 2 );
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signal ExtModeRegister : EMR_TYPE := (
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DLL_EN => '0',
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AL => 0,
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QOFF => '0',
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DQSB_ENB => '0',
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RDQS_EN => '0',
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OCD_PGM => CAL_EXIT );
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signal ExtModeRegister2 : EMR2_TYPE := (
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SREF_HOT => '0' );
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signal last_ocd_adjust_cmd, clk_cycle : time := 0 ns;
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signal clk_last_rising : time := 0 ns;
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signal cke_last_rising : time := 0 ns;
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signal clk_last_falling : time := 0 ns;
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signal udqs_last_rising : time := 0 ns;
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signal udqs_last_falling : time := 0 ns;
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signal ldqs_last_rising : time := 0 ns;
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signal ldqs_last_falling : time := 0 ns;
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signal wr_cmd_time : time := 0 ns;
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signal ldm_last_rising : time := 0 ns;
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signal udm_last_rising : time := 0 ns;
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signal b0_last_activate : time := 0 ns;
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signal b1_last_activate : time := 0 ns;
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signal b2_last_activate : time := 0 ns;
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signal b3_last_activate : time := 0 ns;
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signal b0_last_precharge : time := 0 ns;
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signal b1_last_precharge : time := 0 ns;
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signal b2_last_precharge : time := 0 ns;
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signal b3_last_precharge : time := 0 ns;
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signal b0_last_column_access : time := 0 ns;
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signal b1_last_column_access : time := 0 ns;
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signal b2_last_column_access : time := 0 ns;
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signal b3_last_column_access : time := 0 ns;
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signal b0_last_data_in : time := 0 ns;
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signal b1_last_data_in : time := 0 ns;
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signal b2_last_data_in : time := 0 ns;
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signal b3_last_data_in : time := 0 ns;
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signal last_mrs_set : time := 0 ns;
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signal last_aref : time := 0 ns;
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signal tCH : time := 0 ns;
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signal tCL : time := 0 ns;
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signal tWPRE : time := 0 ns;
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signal tRAS, tRCD, tRP, tRC, tCCD : time := 0 ns;
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signal tWTR : time := 0 ns;
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signal tDQSH : time := 0 ns;
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signal tDQSL : time := 0 ns;
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signal tWPSTmin : time := 0 ns;
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signal tWPSTmax : time := 0 ns;
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signal tDQSSmin : time := 0 ns;
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signal tDQSSmax : time := 0 ns;
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signal tMRD : time := 0 ns;
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signal cke_ch : time := 0 ns;
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signal rasb_ch : time := 0 ns;
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signal casb_ch : time := 0 ns;
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signal web_ch : time := 0 ns;
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signal csb_ch : time := 0 ns;
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signal udm_ch : time := 0 ns;
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signal ldm_ch : time := 0 ns;
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signal a0_ch : time := 0 ns;
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signal a1_ch : time := 0 ns;
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signal a2_ch : time := 0 ns;
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signal a3_ch : time := 0 ns;
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signal a4_ch : time := 0 ns;
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signal a5_ch : time := 0 ns;
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signal a6_ch : time := 0 ns;
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signal a7_ch : time := 0 ns;
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signal a8_ch : time := 0 ns;
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signal a9_ch : time := 0 ns;
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signal a10_ch : time := 0 ns;
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signal a11_ch : time := 0 ns;
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signal a12_ch : time := 0 ns;
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signal ba0_ch : time := 0 ns;
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signal ba1_ch : time := 0 ns;
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signal dq0_ch : time := 0 ns;
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signal dq1_ch : time := 0 ns;
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signal dq2_ch : time := 0 ns;
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signal dq3_ch : time := 0 ns;
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signal dq4_ch : time := 0 ns;
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signal dq5_ch : time := 0 ns;
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signal dq6_ch : time := 0 ns;
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signal dq7_ch : time := 0 ns;
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signal dq8_ch : time := 0 ns;
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signal dq9_ch : time := 0 ns;
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signal dq10_ch : time := 0 ns;
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signal dq11_ch : time := 0 ns;
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signal dq12_ch : time := 0 ns;
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signal dq13_ch : time := 0 ns;
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signal dq14_ch : time := 0 ns;
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signal dq15_ch : time := 0 ns;
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begin
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-----------------------------------------------------------------------------------------------------
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CLK_CYCLE_CHECK : process(CLK)
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begin
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CLK_DLY15 <= transport CLK after 1.5 ns;
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CLK_DLY1 <= transport CLK after 1 ns;
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CLK_DLY2 <= transport CLK after 2 ns;
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if (rising_edge(CLK)) then
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clk_cycle <= transport now - clk_cycle_rising;
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clk_cycle_rising <= transport now;
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end if;
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end Process;
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-----------------------------------------------------------------------------------------------------
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REFRESH_TIME_CHECK : process(tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans)
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variable i, j : integer := 0;
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begin
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i := 0;
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j := 0;
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if (RefChkTimeInit = FALSE) then
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loop
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exit when (i > NUM_OF_BANKS - 1);
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j := 0;
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loop
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exit when (j >= NUM_OF_ROWS);
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refresh_check (i, j) <= 0 ns;
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j := j + 1;
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end loop;
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i := i + 1;
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end loop;
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RefChkTimeInit <= TRUE;
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end if;
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if (tmp_ref_addr1_trans'event and tmp_ref_addr1_trans = '1') then
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refresh_check (0, conv_integer(tmp_ref_addr1)) <= transport now;
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refresh_check (1, conv_integer(tmp_ref_addr1)) <= transport now;
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refresh_check (2, conv_integer(tmp_ref_addr1)) <= transport now;
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refresh_check (3, conv_integer(tmp_ref_addr1)) <= transport now;
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end if;
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if (tmp_ref_addr2_trans'event and tmp_ref_addr2_trans = '1') then
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refresh_check (conv_integer(tmp_ref_addr2(1 downto 0)), conv_integer(tmp_ref_addr2((NUM_OF_ROW_ADD + 1) downto 2))) <= transport now;
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end if;
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if (tmp_ref_addr3_trans'event and tmp_ref_addr3_trans = '1') then
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if (tmp_ref_addr3_0 = '1') then
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refresh_check (0, conv_integer(tmp_ref_addr3_B0)) <= transport now;
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end if;
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if (tmp_ref_addr3_1 = '1') then
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refresh_check (1, conv_integer(tmp_ref_addr3_B1)) <= transport now;
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end if;
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if (tmp_ref_addr3_2 = '1') then
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refresh_check (2, conv_integer(tmp_ref_addr3_B2)) <= transport now;
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end if;
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if (tmp_ref_addr3_3 = '1') then
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refresh_check (3, conv_integer(tmp_ref_addr3_B3)) <= transport now;
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end if;
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end if;
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end process;
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-----------------------------------------------------------------------------------------------------
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CKE_EVAL : process (CLK, CKE)
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begin
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if (CKE'EVENT and CKE = '1' and CKE'LAST_VALUE = '0') then
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cke_last_rising <= transport now;
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end if;
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if (CLK'EVENT and CLK = '0' and CLK'LAST_VALUE = '1') then
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CKEN(-1) <= CKEN(0);
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elsif (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
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CKEN(0) <= CKE;
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end if;
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end process;
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-----------------------------------------------------------------------------------------------------
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STATE_MACHINE : process (CLK, CKE, BankActivateFinFlag, PrechargeFinFlag, PrechargeAllFinFlag, BankActivatedFlag, PUSCheckFinFlag)
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297 |
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|
|
variable ChipSelectBar : std_logic := '0';
|
299 |
|
|
variable RowAddrStrobeBar : std_logic := '0';
|
300 |
|
|
variable ColAddrStrobeBar : std_logic := '0';
|
301 |
|
|
variable WriteEnableBar : std_logic := '0';
|
302 |
|
|
variable Address10 : std_logic := '0';
|
303 |
|
|
variable ClockEnable : CKE_TYPE := (others => '0');
|
304 |
|
|
variable NextState, Cur_State : STATE_TYPE := PWRUP;
|
305 |
|
|
variable CurrentCommand : COMMAND_TYPE := NOP;
|
306 |
|
|
variable OpCode : MROPCODE_TYPE := (others => 'X');
|
307 |
|
|
variable MR : MODE_REGISTER;
|
308 |
|
|
variable EMR : EMR_TYPE;
|
309 |
|
|
variable EMR2 : EMR2_TYPE;
|
310 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
311 |
|
|
variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0');
|
312 |
|
|
|
313 |
|
|
begin
|
314 |
|
|
if (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then
|
315 |
|
|
ClockEnable(-1) := CKEN(-1);
|
316 |
|
|
ClockEnable(0) := CKE;
|
317 |
|
|
ChipSelectBar := CSB;
|
318 |
|
|
RowAddrStrobeBar := RASB;
|
319 |
|
|
ColAddrStrobeBar := CASB;
|
320 |
|
|
WriteEnableBar := WEB;
|
321 |
|
|
Address10 := ADDR(10);
|
322 |
|
|
BkAdd := BA;
|
323 |
|
|
BankActFlag := BankActivatedFlag;
|
324 |
|
|
Cur_State := CurrentState;
|
325 |
|
|
COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar,
|
326 |
|
|
WriteEnableBar, Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State);
|
327 |
|
|
if (DLL_reset = '1' and (CurrentCommand = RD or CurrentCommand = RDAP)) then
|
328 |
|
|
if (TimingCheckFlag = TRUE) then
|
329 |
|
|
assert false report
|
330 |
|
|
"ERROR : (DLL Locking) : 200 clock cycles are needed after DLL reset."
|
331 |
|
|
severity ERROR;
|
332 |
|
|
end if;
|
333 |
|
|
end if;
|
334 |
|
|
Case CurrentState Is
|
335 |
|
|
When IDLE =>
|
336 |
|
|
Case CurrentCommand Is
|
337 |
|
|
When DSEL =>
|
338 |
|
|
NextState := IDLE;
|
339 |
|
|
When NOP =>
|
340 |
|
|
NextState := IDLE;
|
341 |
|
|
When ACT =>
|
342 |
|
|
if (TimingCheckFlag = TRUE) then
|
343 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
344 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
345 |
|
|
severity WARNING;
|
346 |
|
|
assert (now - last_aref >= tRFC) report
|
347 |
|
|
"WARNING : (tRFC_CHECK) : tRFC timing error!"
|
348 |
|
|
severity WARNING;
|
349 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
350 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
351 |
|
|
severity error;
|
352 |
|
|
end if;
|
353 |
|
|
BankActivateFlag <= TRUE;
|
354 |
|
|
NextState := RACT;
|
355 |
|
|
When PCG =>
|
356 |
|
|
if (TimingCheckFlag = TRUE) then
|
357 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
358 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
359 |
|
|
severity error;
|
360 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
361 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
362 |
|
|
severity WARNING;
|
363 |
|
|
end if;
|
364 |
|
|
NextState := IDLE;
|
365 |
|
|
When PCGA =>
|
366 |
|
|
if (TimingCheckFlag = TRUE) then
|
367 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
368 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
369 |
|
|
severity error;
|
370 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
371 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
372 |
|
|
severity WARNING;
|
373 |
|
|
end if;
|
374 |
|
|
NextState := IDLE;
|
375 |
|
|
When AREF =>
|
376 |
|
|
if (TimingCheckFlag = TRUE) then
|
377 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
378 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
379 |
|
|
severity WARNING;
|
380 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
381 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
382 |
|
|
severity error;
|
383 |
|
|
assert (now - last_aref >= tRFC) report
|
384 |
|
|
"WARNING : (tRFC_CHECK) : tRFC timing error!"
|
385 |
|
|
severity WARNING;
|
386 |
|
|
end if;
|
387 |
|
|
last_aref <= transport now after 1 ns;
|
388 |
|
|
AutoRefFlag <= TRUE, FALSE after 2 ns;
|
389 |
|
|
NextState := IDLE;
|
390 |
|
|
When SREF =>
|
391 |
|
|
if (TimingCheckFlag = TRUE) then
|
392 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
393 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
394 |
|
|
severity WARNING;
|
395 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
396 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
397 |
|
|
severity error;
|
398 |
|
|
end if;
|
399 |
|
|
SelfRefFlag <= TRUE;
|
400 |
|
|
NextState := SLFREF;
|
401 |
|
|
When PDEN =>
|
402 |
|
|
if (TimingCheckFlag = TRUE) then
|
403 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
404 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
405 |
|
|
severity WARNING;
|
406 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
407 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
408 |
|
|
severity error;
|
409 |
|
|
end if;
|
410 |
|
|
PcgPdFlag <= TRUE;
|
411 |
|
|
NextState := PWRDN;
|
412 |
|
|
When EMRS3 =>
|
413 |
|
|
NextState := IDLE;
|
414 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
415 |
|
|
When EMRS1 =>
|
416 |
|
|
OpCode := ADDR(12 downto 0);
|
417 |
|
|
EXT_MODE_REGISTER_SET (OpCode, EMR);
|
418 |
|
|
ExtModeRegister <= EMR;
|
419 |
|
|
NextState := IDLE;
|
420 |
|
|
if (ADDR(0) = '0') then
|
421 |
|
|
DLL_lock_enable <= '1';
|
422 |
|
|
end if;
|
423 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
424 |
|
|
When EMRS2 =>
|
425 |
|
|
OpCode := ADDR(12 downto 0);
|
426 |
|
|
EXT_MODE_REGISTER_SET2 (OpCode, EMR2);
|
427 |
|
|
ExtModeRegister2 <= EMR2;
|
428 |
|
|
NextState := IDLE;
|
429 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
430 |
|
|
When MRS =>
|
431 |
|
|
if (TimingCheckFlag = TRUE) then
|
432 |
|
|
assert (PcgPdExtFlag = FALSE) report
|
433 |
|
|
"WARNING : (tXP_CHECK) : tXP timing error!"
|
434 |
|
|
severity WARNING;
|
435 |
|
|
assert (SelfRefExt2NRFlag /= TRUE) report
|
436 |
|
|
"ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh."
|
437 |
|
|
severity error;
|
438 |
|
|
end if;
|
439 |
|
|
OpCode := ADDR(12 downto 0);
|
440 |
|
|
MODE_REGISTER_SET (OpCode, MR);
|
441 |
|
|
ModeRegister <= MR;
|
442 |
|
|
ModeRegisterSetFlag <= TRUE;
|
443 |
|
|
if (ADDR(8) = '1') then
|
444 |
|
|
DLL_reset <= transport '1', '0' after 200 * clk_cycle;
|
445 |
|
|
end if;
|
446 |
|
|
NextState := IDLE;
|
447 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
448 |
|
|
When others =>
|
449 |
|
|
assert false report
|
450 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
451 |
|
|
severity warning;
|
452 |
|
|
NextState := IDLE;
|
453 |
|
|
End Case;
|
454 |
|
|
When PWRUP =>
|
455 |
|
|
Case CurrentCommand Is
|
456 |
|
|
When DSEL =>
|
457 |
|
|
if (PUSCheckFlag = TRUE) then
|
458 |
|
|
NextState := PWRUP;
|
459 |
|
|
else
|
460 |
|
|
NextState := IDLE;
|
461 |
|
|
end if;
|
462 |
|
|
When NOP =>
|
463 |
|
|
if (PUSCheckFlag = TRUE) then
|
464 |
|
|
NextState := PWRUP;
|
465 |
|
|
else
|
466 |
|
|
NextState := IDLE;
|
467 |
|
|
end if;
|
468 |
|
|
When EMRS3 =>
|
469 |
|
|
NextState := PWRUP;
|
470 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
471 |
|
|
When EMRS1 =>
|
472 |
|
|
if (TimingCheckFlag = TRUE and PUSCheckFlag = TRUE) then
|
473 |
|
|
assert (PUSPCGAFlag1 = TRUE) report
|
474 |
|
|
"ERROR : (Power Up Sequence) : PCGA Command must be issued before EMRS setting!"
|
475 |
|
|
severity error;
|
476 |
|
|
end if;
|
477 |
|
|
OpCode := ADDR(12 downto 0);
|
478 |
|
|
EXT_MODE_REGISTER_SET (OpCode, EMR);
|
479 |
|
|
ExtModeRegister <= EMR;
|
480 |
|
|
NextState := PWRUP;
|
481 |
|
|
if (ADDR(0) = '0') then
|
482 |
|
|
DLL_lock_enable <= '1';
|
483 |
|
|
end if;
|
484 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
485 |
|
|
When EMRS2 =>
|
486 |
|
|
OpCode := ADDR(12 downto 0);
|
487 |
|
|
EXT_MODE_REGISTER_SET2 (OpCode, EMR2);
|
488 |
|
|
ExtModeRegister2 <= EMR2;
|
489 |
|
|
NextState := PWRUP;
|
490 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
491 |
|
|
When MRS =>
|
492 |
|
|
if (TimingCheckFlag = TRUE) then
|
493 |
|
|
assert (DLL_lock_enable = '1') report
|
494 |
|
|
"WARNING : (STATE_MACHINE) : EMRS Command (with DLL enable flag) Must be Issued before MRS Command !"
|
495 |
|
|
severity warning;
|
496 |
|
|
end if;
|
497 |
|
|
OpCode := ADDR(12 downto 0);
|
498 |
|
|
MODE_REGISTER_SET (OpCode, MR);
|
499 |
|
|
ModeRegister <= MR;
|
500 |
|
|
ModeRegisterSetFlag <= TRUE;
|
501 |
|
|
NextState := PWRUP;
|
502 |
|
|
if (ADDR(8) = '1') then
|
503 |
|
|
DLL_reset <= transport '1', '0' after 200 * clk_cycle;
|
504 |
|
|
end if;
|
505 |
|
|
mrs_cmd_in <= transport '1', '0' after 2 ns;
|
506 |
|
|
When PCGA =>
|
507 |
|
|
PrechargeAllFlag <= TRUE;
|
508 |
|
|
NextState := PWRUP;
|
509 |
|
|
When AREF =>
|
510 |
|
|
AutoRefFlag <= TRUE, FALSE after 2 ns;
|
511 |
|
|
if (PUSCheckFinFlag = TRUE) then
|
512 |
|
|
NextState := IDLE;
|
513 |
|
|
else
|
514 |
|
|
NextState := PWRUP;
|
515 |
|
|
end if;
|
516 |
|
|
last_aref <= transport now after 1 ns;
|
517 |
|
|
When others =>
|
518 |
|
|
assert false report
|
519 |
|
|
"ERROR : (STATE_MACHINE) : Invalid Command Issued during Power Up Sequence."
|
520 |
|
|
severity error;
|
521 |
|
|
End Case;
|
522 |
|
|
When PWRDN =>
|
523 |
|
|
Case CurrentCommand Is
|
524 |
|
|
When NOP =>
|
525 |
|
|
NextState := PWRDN;
|
526 |
|
|
When PDEX =>
|
527 |
|
|
if (PcgPdFlag = TRUE) then
|
528 |
|
|
PcgPdExtFlag <= transport TRUE, FALSE after tXP * clk_cycle;
|
529 |
|
|
PcgPdFlag <= FALSE;
|
530 |
|
|
NextState := IDLE;
|
531 |
|
|
elsif (ModeRegister.SAPD = '0') then
|
532 |
|
|
ActPdExtFlag <= transport TRUE, FALSE after tXARD * clk_cycle;
|
533 |
|
|
NextState := RACT;
|
534 |
|
|
elsif (ModeRegister.SAPD = '1') then
|
535 |
|
|
SlowActPdExtFlag <= transport TRUE, FALSE after (6 - ExtModeRegister.AL) * clk_cycle;
|
536 |
|
|
NextState := RACT;
|
537 |
|
|
end if;
|
538 |
|
|
When others =>
|
539 |
|
|
assert false report
|
540 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
541 |
|
|
severity warning;
|
542 |
|
|
NextState := PWRDN;
|
543 |
|
|
End Case;
|
544 |
|
|
When SLFREF =>
|
545 |
|
|
Case CurrentCommand Is
|
546 |
|
|
When NOP =>
|
547 |
|
|
NextState := SLFREF;
|
548 |
|
|
When SREX =>
|
549 |
|
|
SelfRefExt2NRFlag <= transport TRUE, FALSE after tXSNR;
|
550 |
|
|
SelfRefExt2RDFlag <= transport TRUE, FALSE after tXSRD * clk_cycle;
|
551 |
|
|
SelfRefFlag <= FALSE;
|
552 |
|
|
NextState := IDLE;
|
553 |
|
|
When others =>
|
554 |
|
|
assert false report
|
555 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
556 |
|
|
severity warning;
|
557 |
|
|
NextState := SLFREF;
|
558 |
|
|
End Case;
|
559 |
|
|
When RACT =>
|
560 |
|
|
Case CurrentCommand Is
|
561 |
|
|
When DSEL =>
|
562 |
|
|
NextState := RACT;
|
563 |
|
|
When NOP =>
|
564 |
|
|
NextState := RACT;
|
565 |
|
|
When RD =>
|
566 |
|
|
if (TimingCheckFlag = TRUE) then
|
567 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
568 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
569 |
|
|
severity error;
|
570 |
|
|
assert (ActPdExtFlag = FALSE) report
|
571 |
|
|
"WARNING : (tXARD_CHECK) : tXARD timing error!"
|
572 |
|
|
severity WARNING;
|
573 |
|
|
assert (SlowActPdExtFlag = FALSE) report
|
574 |
|
|
"WARNING : (tXARDS_CHECK) : tXARDS timing error!"
|
575 |
|
|
severity WARNING;
|
576 |
|
|
end if;
|
577 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
578 |
|
|
NextState := READ;
|
579 |
|
|
When RDAP =>
|
580 |
|
|
if (TimingCheckFlag = TRUE) then
|
581 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
582 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
583 |
|
|
severity error;
|
584 |
|
|
assert (ActPdExtFlag = FALSE) report
|
585 |
|
|
"WARNING : (tXARD_CHECK) : tXARD timing error!"
|
586 |
|
|
severity WARNING;
|
587 |
|
|
assert (SlowActPdExtFlag = FALSE) report
|
588 |
|
|
"WARNING : (tXARDS_CHECK) : tXARDS timing error!"
|
589 |
|
|
severity WARNING;
|
590 |
|
|
end if;
|
591 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
592 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
|
593 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
|
594 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
595 |
|
|
NextState := READ;
|
596 |
|
|
When WR =>
|
597 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
598 |
|
|
NextState := WRITE;
|
599 |
|
|
When WRAP =>
|
600 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
601 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
602 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
|
603 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
604 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
|
605 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
606 |
|
|
NextState := WRITE;
|
607 |
|
|
When ACT =>
|
608 |
|
|
BankActivateFlag <= TRUE;
|
609 |
|
|
NextState := RACT;
|
610 |
|
|
When PCG =>
|
611 |
|
|
PrechargeFlag <= TRUE;
|
612 |
|
|
if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or
|
613 |
|
|
(BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then
|
614 |
|
|
NextState := IDLE;
|
615 |
|
|
else
|
616 |
|
|
NextState := RACT;
|
617 |
|
|
end if;
|
618 |
|
|
When PCGA =>
|
619 |
|
|
PrechargeAllFlag <= TRUE;
|
620 |
|
|
NextState := IDLE;
|
621 |
|
|
When PDEN =>
|
622 |
|
|
NextState := PWRDN;
|
623 |
|
|
When others =>
|
624 |
|
|
assert false report
|
625 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
626 |
|
|
severity warning;
|
627 |
|
|
NextState := RACT;
|
628 |
|
|
End Case;
|
629 |
|
|
When READ =>
|
630 |
|
|
Case CurrentCommand Is
|
631 |
|
|
When DSEL =>
|
632 |
|
|
NextState := READ;
|
633 |
|
|
When NOP =>
|
634 |
|
|
NextState := READ;
|
635 |
|
|
When RD =>
|
636 |
|
|
if (TimingCheckFlag = TRUE) then
|
637 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
638 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
639 |
|
|
severity error;
|
640 |
|
|
end if;
|
641 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
642 |
|
|
NextState := READ;
|
643 |
|
|
When RDAP =>
|
644 |
|
|
if (TimingCheckFlag = TRUE) then
|
645 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
646 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
647 |
|
|
severity error;
|
648 |
|
|
end if;
|
649 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
650 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
|
651 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
|
652 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
653 |
|
|
NextState := READ;
|
654 |
|
|
When WR =>
|
655 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
656 |
|
|
NextState := WRITE;
|
657 |
|
|
When WRAP =>
|
658 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
659 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
660 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
|
661 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
662 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
|
663 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
664 |
|
|
NextState := WRITE;
|
665 |
|
|
When ACT =>
|
666 |
|
|
BankActivateFlag <= TRUE;
|
667 |
|
|
NextState := READ;
|
668 |
|
|
When PCG =>
|
669 |
|
|
PrechargeFlag <= TRUE;
|
670 |
|
|
NextState := READ;
|
671 |
|
|
When PCGA =>
|
672 |
|
|
PrechargeAllFlag <= TRUE;
|
673 |
|
|
NextState := READ;
|
674 |
|
|
When others =>
|
675 |
|
|
assert false report
|
676 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
677 |
|
|
severity warning;
|
678 |
|
|
NextState := READ;
|
679 |
|
|
End Case;
|
680 |
|
|
When WRITE =>
|
681 |
|
|
Case CurrentCommand Is
|
682 |
|
|
When DSEL =>
|
683 |
|
|
NextState := WRITE;
|
684 |
|
|
When NOP =>
|
685 |
|
|
NextState := WRITE;
|
686 |
|
|
When RD =>
|
687 |
|
|
if (TimingCheckFlag = TRUE) then
|
688 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
689 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
690 |
|
|
severity error;
|
691 |
|
|
end if;
|
692 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
693 |
|
|
NextState := READ;
|
694 |
|
|
When RDAP =>
|
695 |
|
|
if (TimingCheckFlag = TRUE) then
|
696 |
|
|
assert (SelfRefExt2RDFlag /= TRUE) report
|
697 |
|
|
"ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh."
|
698 |
|
|
severity error;
|
699 |
|
|
end if;
|
700 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
701 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP,
|
702 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns;
|
703 |
|
|
Read_CA <= '1', '0' after 2 ns;
|
704 |
|
|
NextState := READ;
|
705 |
|
|
When WR =>
|
706 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
707 |
|
|
NextState := WRITE;
|
708 |
|
|
When WRAP =>
|
709 |
|
|
AutoPrechargeFlag(conv_integer(BkAdd)) <= transport
|
710 |
|
|
'1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
711 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle,
|
712 |
|
|
'0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 +
|
713 |
|
|
ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns;
|
714 |
|
|
Write_CA <= '1', '0' after 2 ns;
|
715 |
|
|
NextState := WRITE;
|
716 |
|
|
When ACT =>
|
717 |
|
|
BankActivateFlag <= TRUE;
|
718 |
|
|
NextState := WRITE;
|
719 |
|
|
When PCG =>
|
720 |
|
|
PrechargeFlag <= TRUE;
|
721 |
|
|
NextState := WRITE;
|
722 |
|
|
When PCGA =>
|
723 |
|
|
PrechargeAllFlag <= TRUE;
|
724 |
|
|
NextState := WRITE;
|
725 |
|
|
When others =>
|
726 |
|
|
assert false report
|
727 |
|
|
"WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored."
|
728 |
|
|
severity warning;
|
729 |
|
|
NextState := WRITE;
|
730 |
|
|
End Case;
|
731 |
|
|
When others =>
|
732 |
|
|
assert false report
|
733 |
|
|
"ERROR : (STATE_MACHINE) : Invalid Command Issued."
|
734 |
|
|
severity error;
|
735 |
|
|
End case;
|
736 |
|
|
end if;
|
737 |
|
|
if (BankActivateFinFlag = TRUE) then
|
738 |
|
|
BankActivateFlag <= FALSE;
|
739 |
|
|
end if;
|
740 |
|
|
if (PrechargeFinFlag = TRUE) then
|
741 |
|
|
PrechargeFlag <= FALSE;
|
742 |
|
|
end if;
|
743 |
|
|
if (PrechargeAllFinFlag = TRUE) then
|
744 |
|
|
PrechargeAllFlag <= FALSE;
|
745 |
|
|
end if;
|
746 |
|
|
if (PUSCheckFinFlag'EVENT and PUSCheckFinFlag = TRUE) then
|
747 |
|
|
NextState := IDLE;
|
748 |
|
|
end if;
|
749 |
|
|
if (BankActivatedFlag'EVENT and BankActivatedFlag /= BankActivatedFlag'LAST_VALUE) then
|
750 |
|
|
if (BankActivatedFlag = "0000") then
|
751 |
|
|
NextState := IDLE;
|
752 |
|
|
else
|
753 |
|
|
NextState := RACT;
|
754 |
|
|
end if;
|
755 |
|
|
end if;
|
756 |
|
|
CurrentState <= NextState;
|
757 |
|
|
end process;
|
758 |
|
|
|
759 |
|
|
-----------------------------------------------------------------------------------------------------
|
760 |
|
|
|
761 |
|
|
MEMORY_BANK_ACTIVATE_PRECHARGE : process (PrechargeFlag, AutoPrechargeFlag, PrechargeAllFlag, BankActivateFlag, CLK)
|
762 |
|
|
|
763 |
|
|
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
764 |
|
|
variable RA : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'X');
|
765 |
|
|
variable MEM_CELL_ARRAY0, MEM_CELL_ARRAY1, MEM_CELL_ARRAY2, MEM_CELL_ARRAY3 : MEM_CELL_TYPE;
|
766 |
|
|
variable i, j, k, l, m, u : integer := 0;
|
767 |
|
|
|
768 |
|
|
begin
|
769 |
|
|
if (CLK'EVENT and CLK = '0') then
|
770 |
|
|
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans0 = '1'))) Then
|
771 |
|
|
tmp_act_trans0 <= '0';
|
772 |
|
|
end if;
|
773 |
|
|
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans1 = '1'))) Then
|
774 |
|
|
tmp_act_trans1 <= '0';
|
775 |
|
|
end if;
|
776 |
|
|
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans2 = '1'))) Then
|
777 |
|
|
tmp_act_trans2 <= '0';
|
778 |
|
|
end if;
|
779 |
|
|
if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans3 = '1'))) Then
|
780 |
|
|
tmp_act_trans3 <= '0';
|
781 |
|
|
end if;
|
782 |
|
|
end if;
|
783 |
|
|
if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then
|
784 |
|
|
BkAdd := (BA);
|
785 |
|
|
RA := ADDR(NUM_OF_ROW_ADD - 1 downto 0);
|
786 |
|
|
BankActivatedFlag(conv_integer(BkAdd)) <= '1';
|
787 |
|
|
i := 0;
|
788 |
|
|
j := 0;
|
789 |
|
|
u := 0;
|
790 |
|
|
if (BankActivatedFlag (conv_integer (BkAdd)) = '1') then
|
791 |
|
|
assert false report
|
792 |
|
|
"WARNING : (MEMORY_BANK_ACTIVATE) : Activating same bank without precharge. Command Ignored."
|
793 |
|
|
severity warning;
|
794 |
|
|
BankActivateFinFlag <= TRUE, FALSE after 2 ns;
|
795 |
|
|
elsif (BankActivatedFlag (conv_integer (BkAdd)) = '0') then
|
796 |
|
|
if (TimingCheckFlag = TRUE) then
|
797 |
|
|
if (now - refresh_check(conv_integer(BkAdd), conv_integer(RA)) > tREF) then
|
798 |
|
|
assert false report
|
799 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms. So, This Row's Data Is Lost."
|
800 |
|
|
severity warning;
|
801 |
|
|
end if;
|
802 |
|
|
end if;
|
803 |
|
|
case BkAdd is
|
804 |
|
|
when "00" =>
|
805 |
|
|
b0_last_activate <= transport now;
|
806 |
|
|
RA_Activated_B0 <= RA;
|
807 |
|
|
when "01" =>
|
808 |
|
|
b1_last_activate <= transport now;
|
809 |
|
|
RA_Activated_B1 <= RA;
|
810 |
|
|
when "10" =>
|
811 |
|
|
b2_last_activate <= transport now;
|
812 |
|
|
RA_Activated_B2 <= RA;
|
813 |
|
|
when "11" =>
|
814 |
|
|
b3_last_activate <= transport now;
|
815 |
|
|
RA_Activated_B3 <= RA;
|
816 |
|
|
when others =>
|
817 |
|
|
assert false report
|
818 |
|
|
"WARNING : (MEMORY_REFRESH) : Impossible Bank Address"
|
819 |
|
|
severity warning;
|
820 |
|
|
end case;
|
821 |
|
|
if (conv_integer (BkAdd) = 0) then
|
822 |
|
|
if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then
|
823 |
|
|
MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE;
|
824 |
|
|
loop
|
825 |
|
|
exit when u >= NUM_OF_COLS;
|
826 |
|
|
MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0;
|
827 |
|
|
u := u + 1;
|
828 |
|
|
end loop;
|
829 |
|
|
end if;
|
830 |
|
|
loop
|
831 |
|
|
exit when i >= NUM_OF_COLS;
|
832 |
|
|
SA_ARRAY_A0(i) <= MEM_CELL_ARRAY0(conv_integer (RA))(i);
|
833 |
|
|
i := i + 1;
|
834 |
|
|
end loop;
|
835 |
|
|
tmp_act_trans0 <= '1';
|
836 |
|
|
elsif (conv_integer (BkAdd) = 1) then
|
837 |
|
|
if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then
|
838 |
|
|
MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE;
|
839 |
|
|
loop
|
840 |
|
|
exit when u >= NUM_OF_COLS;
|
841 |
|
|
MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0;
|
842 |
|
|
u := u + 1;
|
843 |
|
|
end loop;
|
844 |
|
|
end if;
|
845 |
|
|
loop
|
846 |
|
|
exit when i >= NUM_OF_COLS;
|
847 |
|
|
SA_ARRAY_A1(i) <= MEM_CELL_ARRAY1(conv_integer (RA))(i);
|
848 |
|
|
i := i + 1;
|
849 |
|
|
end loop;
|
850 |
|
|
tmp_act_trans1 <= '1';
|
851 |
|
|
elsif (conv_integer (BkAdd) = 2) then
|
852 |
|
|
if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then
|
853 |
|
|
MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE;
|
854 |
|
|
loop
|
855 |
|
|
exit when u >= NUM_OF_COLS;
|
856 |
|
|
MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0;
|
857 |
|
|
u := u + 1;
|
858 |
|
|
end loop;
|
859 |
|
|
end if;
|
860 |
|
|
loop
|
861 |
|
|
exit when i >= NUM_OF_COLS;
|
862 |
|
|
SA_ARRAY_A2(i) <= MEM_CELL_ARRAY2(conv_integer (RA))(i);
|
863 |
|
|
i := i + 1;
|
864 |
|
|
end loop;
|
865 |
|
|
tmp_act_trans2 <= '1';
|
866 |
|
|
elsif (conv_integer (BkAdd) = 3) then
|
867 |
|
|
if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then
|
868 |
|
|
MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE;
|
869 |
|
|
loop
|
870 |
|
|
exit when u >= NUM_OF_COLS;
|
871 |
|
|
MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0;
|
872 |
|
|
u := u + 1;
|
873 |
|
|
end loop;
|
874 |
|
|
end if;
|
875 |
|
|
loop
|
876 |
|
|
exit when i >= NUM_OF_COLS;
|
877 |
|
|
SA_ARRAY_A3(i) <= MEM_CELL_ARRAY3(conv_integer (RA))(i);
|
878 |
|
|
i := i + 1;
|
879 |
|
|
end loop;
|
880 |
|
|
tmp_act_trans3 <= '1';
|
881 |
|
|
end if;
|
882 |
|
|
BankActivateFinFlag <= TRUE, FALSE after 2 ns;
|
883 |
|
|
else
|
884 |
|
|
end if;
|
885 |
|
|
end if;
|
886 |
|
|
if ((PrechargeFlag'EVENT and PrechargeFlag = TRUE) or
|
887 |
|
|
(AutoPrechargeFlag(0)'EVENT and AutoPrechargeFlag(0) = '1') or
|
888 |
|
|
(AutoPrechargeFlag(1)'EVENT and AutoPrechargeFlag(1) = '1') or
|
889 |
|
|
(AutoPrechargeFlag(2)'EVENT and AutoPrechargeFlag(2) = '1') or
|
890 |
|
|
(AutoPrechargeFlag(3)'EVENT and AutoPrechargeFlag(3) = '1')) then
|
891 |
|
|
i := 0;
|
892 |
|
|
j := 0;
|
893 |
|
|
if (PrechargeFlag = TRUE) then
|
894 |
|
|
BkAdd := (BA);
|
895 |
|
|
elsif (AutoPrechargeFlag(0) = '1') then
|
896 |
|
|
BkAdd := "00";
|
897 |
|
|
elsif (AutoPrechargeFlag(1) = '1') then
|
898 |
|
|
BkAdd := "01";
|
899 |
|
|
elsif (AutoPrechargeFlag(2) = '1') then
|
900 |
|
|
BkAdd := "10";
|
901 |
|
|
elsif (AutoPrechargeFlag(3) = '1') then
|
902 |
|
|
BkAdd := "11";
|
903 |
|
|
end if;
|
904 |
|
|
if (BkAdd = "00") then
|
905 |
|
|
if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then
|
906 |
|
|
b0_last_precharge <= transport (tRAS + b0_last_activate) after 1 ns;
|
907 |
|
|
else
|
908 |
|
|
b0_last_precharge <= transport now after 1 ns;
|
909 |
|
|
end if;
|
910 |
|
|
if (BankActivatedFlag (0) /= '1') then
|
911 |
|
|
assert false report
|
912 |
|
|
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
|
913 |
|
|
severity warning;
|
914 |
|
|
else
|
915 |
|
|
RA := RA_Activated_B0;
|
916 |
|
|
i := 0;
|
917 |
|
|
loop
|
918 |
|
|
exit when i >= NUM_OF_COLS;
|
919 |
|
|
MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
920 |
|
|
i := i + 1;
|
921 |
|
|
end loop;
|
922 |
|
|
if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then
|
923 |
|
|
BankActivatedFlag (0) <= transport '0' after (tRAS - (now - b0_last_activate));
|
924 |
|
|
else
|
925 |
|
|
BankActivatedFlag (0) <= '0';
|
926 |
|
|
end if;
|
927 |
|
|
tmp_ref_addr2 <= RA&"00";
|
928 |
|
|
end if;
|
929 |
|
|
elsif (BkAdd = "01") then
|
930 |
|
|
if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then
|
931 |
|
|
b1_last_precharge <= transport (tRAS + b1_last_activate) after 1 ns;
|
932 |
|
|
else
|
933 |
|
|
b1_last_precharge <= transport now after 1 ns;
|
934 |
|
|
end if;
|
935 |
|
|
if (BankActivatedFlag (1) /= '1') then
|
936 |
|
|
assert false report
|
937 |
|
|
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
|
938 |
|
|
severity warning;
|
939 |
|
|
else
|
940 |
|
|
RA := RA_Activated_B1;
|
941 |
|
|
i := 0;
|
942 |
|
|
loop
|
943 |
|
|
exit when i >= NUM_OF_COLS;
|
944 |
|
|
MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
945 |
|
|
i := i + 1;
|
946 |
|
|
end loop;
|
947 |
|
|
if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then
|
948 |
|
|
BankActivatedFlag (1) <= transport '0' after (tRAS - (now - b1_last_activate));
|
949 |
|
|
else
|
950 |
|
|
BankActivatedFlag (1) <= '0';
|
951 |
|
|
end if;
|
952 |
|
|
tmp_ref_addr2 <= RA&"01";
|
953 |
|
|
end if;
|
954 |
|
|
elsif (BkAdd = "10") then
|
955 |
|
|
if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then
|
956 |
|
|
b2_last_precharge <= transport (tRAS + b2_last_activate) after 1 ns;
|
957 |
|
|
else
|
958 |
|
|
b2_last_precharge <= transport now after 1 ns;
|
959 |
|
|
end if;
|
960 |
|
|
if (BankActivatedFlag (2) /= '1') then
|
961 |
|
|
assert false report
|
962 |
|
|
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
|
963 |
|
|
severity warning;
|
964 |
|
|
else
|
965 |
|
|
RA := RA_Activated_B2;
|
966 |
|
|
i := 0;
|
967 |
|
|
loop
|
968 |
|
|
exit when i >= NUM_OF_COLS;
|
969 |
|
|
MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
970 |
|
|
i := i + 1;
|
971 |
|
|
end loop;
|
972 |
|
|
if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then
|
973 |
|
|
BankActivatedFlag (2) <= transport '0' after (tRAS - (now - b2_last_activate));
|
974 |
|
|
else
|
975 |
|
|
BankActivatedFlag (2) <= '0';
|
976 |
|
|
end if;
|
977 |
|
|
tmp_ref_addr2 <= RA&"10";
|
978 |
|
|
end if;
|
979 |
|
|
elsif (BkAdd = "11") then
|
980 |
|
|
if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then
|
981 |
|
|
b3_last_precharge <= transport (tRAS + b3_last_activate) after 1 ns;
|
982 |
|
|
else
|
983 |
|
|
b3_last_precharge <= transport now after 1 ns;
|
984 |
|
|
end if;
|
985 |
|
|
if (BankActivatedFlag (3) /= '1') then
|
986 |
|
|
assert false report
|
987 |
|
|
"WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank."
|
988 |
|
|
severity warning;
|
989 |
|
|
else
|
990 |
|
|
RA := RA_Activated_B3;
|
991 |
|
|
i := 0;
|
992 |
|
|
loop
|
993 |
|
|
exit when i >= NUM_OF_COLS;
|
994 |
|
|
MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
995 |
|
|
i := i + 1;
|
996 |
|
|
end loop;
|
997 |
|
|
if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then
|
998 |
|
|
BankActivatedFlag (3) <= transport '0' after (tRAS - (now - b3_last_activate));
|
999 |
|
|
else
|
1000 |
|
|
BankActivatedFlag (3) <= '0';
|
1001 |
|
|
end if;
|
1002 |
|
|
tmp_ref_addr2 <= RA&"11";
|
1003 |
|
|
end if;
|
1004 |
|
|
end if;
|
1005 |
|
|
if (PrechargeFlag = TRUE) then
|
1006 |
|
|
PrechargeFinFlag <= TRUE, FALSE after 2 ns;
|
1007 |
|
|
end if;
|
1008 |
|
|
tmp_ref_addr2_trans <= transport '1', '0' after 1 ns;
|
1009 |
|
|
end if;
|
1010 |
|
|
if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then
|
1011 |
|
|
if BankActivatedFlag (0) = '1' then
|
1012 |
|
|
BkAdd := "00";
|
1013 |
|
|
RA := RA_Activated_B0;
|
1014 |
|
|
i := 0;
|
1015 |
|
|
loop
|
1016 |
|
|
exit when i >= NUM_OF_COLS;
|
1017 |
|
|
MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
1018 |
|
|
i := i + 1;
|
1019 |
|
|
end loop;
|
1020 |
|
|
BankActivatedFlag (0) <= '0';
|
1021 |
|
|
tmp_ref_addr3_B0 <= RA;
|
1022 |
|
|
tmp_ref_addr3_0 <= transport '1', '0' after 1 ns;
|
1023 |
|
|
b0_last_precharge <= transport now after 1 ns;
|
1024 |
|
|
end if;
|
1025 |
|
|
if BankActivatedFlag (1) = '1' then
|
1026 |
|
|
BkAdd := "01";
|
1027 |
|
|
RA := RA_Activated_B1;
|
1028 |
|
|
i := 0;
|
1029 |
|
|
loop
|
1030 |
|
|
exit when i >= NUM_OF_COLS;
|
1031 |
|
|
MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
1032 |
|
|
i := i + 1;
|
1033 |
|
|
end loop;
|
1034 |
|
|
BankActivatedFlag (1) <= '0';
|
1035 |
|
|
tmp_ref_addr3_B1 <= RA;
|
1036 |
|
|
tmp_ref_addr3_1 <= transport '1', '0' after 1 ns;
|
1037 |
|
|
b1_last_precharge <= transport now after 1 ns;
|
1038 |
|
|
end if;
|
1039 |
|
|
if BankActivatedFlag (2) = '1' then
|
1040 |
|
|
BkAdd := "10";
|
1041 |
|
|
RA := RA_Activated_B2;
|
1042 |
|
|
i := 0;
|
1043 |
|
|
loop
|
1044 |
|
|
exit when i >= NUM_OF_COLS;
|
1045 |
|
|
MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
1046 |
|
|
i := i + 1;
|
1047 |
|
|
end loop;
|
1048 |
|
|
BankActivatedFlag (2) <= '0';
|
1049 |
|
|
tmp_ref_addr3_B2 <= RA;
|
1050 |
|
|
tmp_ref_addr3_2 <= transport '1', '0' after 1 ns;
|
1051 |
|
|
b2_last_precharge <= transport now after 1 ns;
|
1052 |
|
|
end if;
|
1053 |
|
|
if BankActivatedFlag (3) = '1' then
|
1054 |
|
|
BkAdd := "11";
|
1055 |
|
|
RA := RA_Activated_B3;
|
1056 |
|
|
i := 0;
|
1057 |
|
|
loop
|
1058 |
|
|
exit when i >= NUM_OF_COLS;
|
1059 |
|
|
MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i);
|
1060 |
|
|
i := i + 1;
|
1061 |
|
|
end loop;
|
1062 |
|
|
BankActivatedFlag (3) <= '0';
|
1063 |
|
|
tmp_ref_addr3_B3 <= RA;
|
1064 |
|
|
tmp_ref_addr3_3 <= transport '1', '0' after 1 ns;
|
1065 |
|
|
b3_last_precharge <= transport now after 1 ns;
|
1066 |
|
|
end if;
|
1067 |
|
|
tmp_ref_addr3_trans <= transport '1', '0' after 1 ns;
|
1068 |
|
|
if (BankActivatedFlag = "0000") then
|
1069 |
|
|
if (PUSCheckFinFlag = TRUE) then
|
1070 |
|
|
assert false report
|
1071 |
|
|
"WARNING : (PRECHARGE_ALL) : No Activated Banks, PCGA command ignored."
|
1072 |
|
|
severity WARNING;
|
1073 |
|
|
else
|
1074 |
|
|
BankActivatedFlag (0) <= '0';
|
1075 |
|
|
BankActivatedFlag (1) <= '0';
|
1076 |
|
|
BankActivatedFlag (2) <= '0';
|
1077 |
|
|
BankActivatedFlag (3) <= '0';
|
1078 |
|
|
end if;
|
1079 |
|
|
end if;
|
1080 |
|
|
PrechargeAllFinFlag <= TRUE, FALSE after 2 ns;
|
1081 |
|
|
end if;
|
1082 |
|
|
end process;
|
1083 |
|
|
|
1084 |
|
|
-----------------------------------------------------------------------------------------------------
|
1085 |
|
|
|
1086 |
|
|
SENSE_AMPLIFIER_UPDATE : process (tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3, tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3)
|
1087 |
|
|
begin
|
1088 |
|
|
if (tmp_act_trans0'EVENT and tmp_act_trans0 = '1') then
|
1089 |
|
|
SA_ARRAY(0) <= SA_ARRAY_A0;
|
1090 |
|
|
elsif (tmp_act_trans1'EVENT and tmp_act_trans1 = '1') then
|
1091 |
|
|
SA_ARRAY(1) <= SA_ARRAY_A1;
|
1092 |
|
|
elsif (tmp_act_trans2'EVENT and tmp_act_trans2 = '1') then
|
1093 |
|
|
SA_ARRAY(2) <= SA_ARRAY_A2;
|
1094 |
|
|
elsif (tmp_act_trans3'EVENT and tmp_act_trans3 = '1') then
|
1095 |
|
|
SA_ARRAY(3) <= SA_ARRAY_A3;
|
1096 |
|
|
elsif (tmp_w_trans0'EVENT and tmp_w_trans0 = '1') then
|
1097 |
|
|
SA_ARRAY(0) <= SA_ARRAY_W0;
|
1098 |
|
|
elsif (tmp_w_trans1'EVENT and tmp_w_trans1 = '1') then
|
1099 |
|
|
SA_ARRAY(1) <= SA_ARRAY_W1;
|
1100 |
|
|
elsif (tmp_w_trans2'EVENT and tmp_w_trans2 = '1') then
|
1101 |
|
|
SA_ARRAY(2) <= SA_ARRAY_W2;
|
1102 |
|
|
elsif (tmp_w_trans3'EVENT and tmp_w_trans3 = '1') then
|
1103 |
|
|
SA_ARRAY(3) <= SA_ARRAY_W3;
|
1104 |
|
|
End if;
|
1105 |
|
|
end process;
|
1106 |
|
|
|
1107 |
|
|
-----------------------------------------------------------------------------------------------------
|
1108 |
|
|
|
1109 |
|
|
RD_WR_PIPE : process (CLK_DLY1, CLK)
|
1110 |
|
|
|
1111 |
|
|
variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
|
1112 |
|
|
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
1113 |
|
|
|
1114 |
|
|
begin
|
1115 |
|
|
|
1116 |
|
|
if (CLK'EVENT and CLK = '1') then
|
1117 |
|
|
BkAdd := (BA);
|
1118 |
|
|
CA := ADDR(NUM_OF_COL_ADD - 1 downto 0);
|
1119 |
|
|
end if;
|
1120 |
|
|
if (CLK_DLY1'EVENT and CLK_DLY1 = '1') then
|
1121 |
|
|
RD_PIPE_REG(6 downto 1) <= RD_PIPE_REG(5 downto 0);
|
1122 |
|
|
WT_PIPE_REG(12 downto 1) <= WT_PIPE_REG(11 downto 0);
|
1123 |
|
|
ADD_PIPE_REG(12) <= ADD_PIPE_REG(11);
|
1124 |
|
|
ADD_PIPE_REG(11) <= ADD_PIPE_REG(10);
|
1125 |
|
|
ADD_PIPE_REG(10) <= ADD_PIPE_REG(9);
|
1126 |
|
|
ADD_PIPE_REG(9) <= ADD_PIPE_REG(8);
|
1127 |
|
|
ADD_PIPE_REG(8) <= ADD_PIPE_REG(7);
|
1128 |
|
|
ADD_PIPE_REG(7) <= ADD_PIPE_REG(6);
|
1129 |
|
|
ADD_PIPE_REG(6) <= ADD_PIPE_REG(5);
|
1130 |
|
|
ADD_PIPE_REG(5) <= ADD_PIPE_REG(4);
|
1131 |
|
|
ADD_PIPE_REG(4) <= ADD_PIPE_REG(3);
|
1132 |
|
|
ADD_PIPE_REG(3) <= ADD_PIPE_REG(2);
|
1133 |
|
|
ADD_PIPE_REG(2) <= ADD_PIPE_REG(1);
|
1134 |
|
|
ADD_PIPE_REG(1) <= ADD_PIPE_REG(0);
|
1135 |
|
|
if (Read_CA = '1' or Write_CA = '1') then
|
1136 |
|
|
ADD_PIPE_REG(0) <= BkAdd & CA;
|
1137 |
|
|
if (Read_CA = '1') then
|
1138 |
|
|
RD_PIPE_REG(0) <= '1';
|
1139 |
|
|
else
|
1140 |
|
|
RD_PIPE_REG(0) <= '0';
|
1141 |
|
|
end if;
|
1142 |
|
|
if (Write_CA = '1') then
|
1143 |
|
|
WT_PIPE_REG(0) <= '1';
|
1144 |
|
|
else
|
1145 |
|
|
WT_PIPE_REG(0) <= '0';
|
1146 |
|
|
end if;
|
1147 |
|
|
else
|
1148 |
|
|
ADD_PIPE_REG(0) <= (others => '0');
|
1149 |
|
|
RD_PIPE_REG(0) <= '0';
|
1150 |
|
|
WT_PIPE_REG(0) <= '0';
|
1151 |
|
|
end if;
|
1152 |
|
|
end if;
|
1153 |
|
|
end process;
|
1154 |
|
|
|
1155 |
|
|
-----------------------------------------------------------------------------------------------------
|
1156 |
|
|
|
1157 |
|
|
casp6_XX_Gen : process (RD_PIPE_REG, WT_PIPE_REG)
|
1158 |
|
|
|
1159 |
|
|
begin
|
1160 |
|
|
if (RD_PIPE_REG'event and RD_PIPE_REG(ExtModeRegister.AL) = '1') then
|
1161 |
|
|
casp6_rd <= transport '1' after 0.5 ns, '0' after 2 ns;
|
1162 |
|
|
elsif (WT_PIPE_REG'event and WT_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 2) = '1') then
|
1163 |
|
|
caspwt <= transport '1', '0' after 2 ns;
|
1164 |
|
|
end if;
|
1165 |
|
|
end process;
|
1166 |
|
|
|
1167 |
|
|
-----------------------------------------------------------------------------------------------------
|
1168 |
|
|
|
1169 |
|
|
RD_WT_Flag_GEN : process (caspwt, casp6_rd, ReadFinFlag, WriteFinFlag)
|
1170 |
|
|
|
1171 |
|
|
begin
|
1172 |
|
|
if (ReadFinFlag'EVENT and ReadFinFlag = TRUE) then
|
1173 |
|
|
ReadFlag <= FALSE;
|
1174 |
|
|
elsif (WriteFinFlag'EVENT and WriteFinFlag = TRUE) then
|
1175 |
|
|
WriteFlag <= FALSE;
|
1176 |
|
|
end if;
|
1177 |
|
|
if (casp6_rd'event and casp6_rd = '1') then
|
1178 |
|
|
ReadFlag <= TRUE;
|
1179 |
|
|
elsif (caspwt'event and caspwt = '1') then
|
1180 |
|
|
WriteFlag <= TRUE;
|
1181 |
|
|
end if;
|
1182 |
|
|
end process;
|
1183 |
|
|
|
1184 |
|
|
-----------------------------------------------------------------------------------------------------
|
1185 |
|
|
|
1186 |
|
|
WRITE_ST_GEN : process(CLK_DLY1, caspwt)
|
1187 |
|
|
|
1188 |
|
|
begin
|
1189 |
|
|
if (caspwt'event and caspwt = '1') then
|
1190 |
|
|
wt_stdby <= '1';
|
1191 |
|
|
end if;
|
1192 |
|
|
if (CLK_DLY1'event and CLK_DLY1 = '1') then
|
1193 |
|
|
if (casp_wtII = '1') then
|
1194 |
|
|
casp6_wt <= transport '1' after 0.5 ns, '0' after 2 ns;
|
1195 |
|
|
end if;
|
1196 |
|
|
casp_wtII <= casp_wtI;
|
1197 |
|
|
casp_wtI <= wt_stdby;
|
1198 |
|
|
wt_stdby <= '0';
|
1199 |
|
|
end if;
|
1200 |
|
|
end process;
|
1201 |
|
|
|
1202 |
|
|
-----------------------------------------------------------------------------------------------------
|
1203 |
|
|
|
1204 |
|
|
YBURST_GEN : process (casp6_rd, casp6_wt, CLK, ReadFinFlag, WriteFinFlag)
|
1205 |
|
|
|
1206 |
|
|
begin
|
1207 |
|
|
if ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1')) then
|
1208 |
|
|
RD_WR_ST <= '1';
|
1209 |
|
|
yburst <= '0';
|
1210 |
|
|
end if;
|
1211 |
|
|
if (CLK'event and CLK = '1') then
|
1212 |
|
|
if (RD_WR_ST = '1' and ModeRegister.BURST_LENGTH = 8) then
|
1213 |
|
|
yburst <= transport '1' after 2.1 ns;
|
1214 |
|
|
end if;
|
1215 |
|
|
RD_WR_ST <= '0';
|
1216 |
|
|
end if;
|
1217 |
|
|
if ((ReadFinFlag'event and ReadFinFlag = TRUE) or (WriteFinFlag'event and WriteFinFlag = TRUE)) then
|
1218 |
|
|
yburst <= '0';
|
1219 |
|
|
end if;
|
1220 |
|
|
end process;
|
1221 |
|
|
|
1222 |
|
|
-----------------------------------------------------------------------------------------------------
|
1223 |
|
|
|
1224 |
|
|
DQS_PULSE_GEN : process (CLK, casp6_rd)
|
1225 |
|
|
|
1226 |
|
|
begin
|
1227 |
|
|
|
1228 |
|
|
if (casp6_rd'EVENT and casp6_rd = '1') then
|
1229 |
|
|
dqs_pulse1 <= '1';
|
1230 |
|
|
end if;
|
1231 |
|
|
if (CLK'EVENT and CLK = '1') then
|
1232 |
|
|
dqs_pulse6 <= dqs_pulse5;
|
1233 |
|
|
dqs_pulse5 <= dqs_pulse4;
|
1234 |
|
|
dqs_pulse4 <= dqs_pulse3;
|
1235 |
|
|
dqs_pulse3 <= dqs_pulse2;
|
1236 |
|
|
dqs_pulse2 <= dqs_pulse1;
|
1237 |
|
|
dqs_pulse1 <= '0';
|
1238 |
|
|
end if;
|
1239 |
|
|
end process;
|
1240 |
|
|
|
1241 |
|
|
-----------------------------------------------------------------------------------------------------
|
1242 |
|
|
|
1243 |
|
|
DQS_GENERATION : process(CLK, dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6)
|
1244 |
|
|
|
1245 |
|
|
begin
|
1246 |
|
|
if (CLK'event and CLK = '1') then
|
1247 |
|
|
if ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse1 = '1') or
|
1248 |
|
|
(ModeRegister.CAS_LATENCY = 3 and dqs_pulse2 = '1') or
|
1249 |
|
|
(ModeRegister.CAS_LATENCY = 4 and dqs_pulse3 = '1') or
|
1250 |
|
|
(ModeRegister.CAS_LATENCY = 5 and dqs_pulse4 = '1') or
|
1251 |
|
|
(ModeRegister.CAS_LATENCY = 6 and dqs_pulse5 = '1')) then
|
1252 |
|
|
if (DQS_S = 'Z') then
|
1253 |
|
|
DQS_S <= '0';
|
1254 |
|
|
elsif (dqs_count = ModeRegister.BURST_LENGTH) then
|
1255 |
|
|
DQS_S <= '0';
|
1256 |
|
|
else
|
1257 |
|
|
DQS_S <= '1';
|
1258 |
|
|
end if;
|
1259 |
|
|
elsif ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse2 = '1') or
|
1260 |
|
|
(ModeRegister.CAS_LATENCY = 3 and dqs_pulse3 = '1') or
|
1261 |
|
|
(ModeRegister.CAS_LATENCY = 4 and dqs_pulse4 = '1') or
|
1262 |
|
|
(ModeRegister.CAS_LATENCY = 5 and dqs_pulse5 = '1') or
|
1263 |
|
|
(ModeRegister.CAS_LATENCY = 6 and dqs_pulse6 = '1')) then
|
1264 |
|
|
if (DQS_S = '0') then
|
1265 |
|
|
DQS_S <= '1';
|
1266 |
|
|
end if;
|
1267 |
|
|
dqs_count <= 1;
|
1268 |
|
|
elsif (dqs_count = ModeRegister.BURST_LENGTH) then
|
1269 |
|
|
if (DQS_S = '0') then
|
1270 |
|
|
DQS_S <= 'Z';
|
1271 |
|
|
end if;
|
1272 |
|
|
dqs_count <= 0;
|
1273 |
|
|
elsif (DQS_S = '0') then
|
1274 |
|
|
DQS_S <= '1';
|
1275 |
|
|
dqs_count <= dqs_count + 1;
|
1276 |
|
|
end if;
|
1277 |
|
|
elsif (CLK'event and CLK = '0') then
|
1278 |
|
|
if (DQS_S = '1') then
|
1279 |
|
|
DQS_S <= '0';
|
1280 |
|
|
dqs_count <= dqs_count + 1;
|
1281 |
|
|
end if;
|
1282 |
|
|
end if;
|
1283 |
|
|
end process;
|
1284 |
|
|
|
1285 |
|
|
-----------------------------------------------------------------------------------------------------
|
1286 |
|
|
|
1287 |
|
|
DQS_OPERATION : process(DQS_S, ExtModeRegister.OCD_PGM)
|
1288 |
|
|
|
1289 |
|
|
begin
|
1290 |
|
|
if (ExtModeRegister.QOFF = '0') then
|
1291 |
|
|
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then
|
1292 |
|
|
UDQS <= '0';
|
1293 |
|
|
LDQS <= '0';
|
1294 |
|
|
if (ExtModeRegister.DQSB_ENB = '1') then
|
1295 |
|
|
UDQSB <= '1';
|
1296 |
|
|
LDQSB <= '1';
|
1297 |
|
|
else
|
1298 |
|
|
UDQSB <= 'Z';
|
1299 |
|
|
LDQSB <= 'Z';
|
1300 |
|
|
end if;
|
1301 |
|
|
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then
|
1302 |
|
|
UDQS <= '1';
|
1303 |
|
|
LDQS <= '1';
|
1304 |
|
|
if (ExtModeRegister.DQSB_ENB = '1') then
|
1305 |
|
|
UDQSB <= '0';
|
1306 |
|
|
LDQSB <= '0';
|
1307 |
|
|
else
|
1308 |
|
|
UDQSB <= 'Z';
|
1309 |
|
|
LDQSB <= 'Z';
|
1310 |
|
|
end if;
|
1311 |
|
|
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
|
1312 |
|
|
UDQS <= 'Z';
|
1313 |
|
|
LDQS <= 'Z';
|
1314 |
|
|
UDQSB <= 'Z';
|
1315 |
|
|
LDQSB <= 'Z';
|
1316 |
|
|
elsif (DQS_S'event and DQS_S = '1') then
|
1317 |
|
|
UDQS <= '1';
|
1318 |
|
|
LDQS <= '1';
|
1319 |
|
|
if (ExtModeRegister.DQSB_ENB = '0') then
|
1320 |
|
|
UDQSB <= '0';
|
1321 |
|
|
LDQSB <= '0';
|
1322 |
|
|
else
|
1323 |
|
|
UDQSB <= 'Z';
|
1324 |
|
|
LDQSB <= 'Z';
|
1325 |
|
|
end if;
|
1326 |
|
|
elsif (DQS_S'event and DQS_S = '0') then
|
1327 |
|
|
UDQS <= '0';
|
1328 |
|
|
LDQS <= '0';
|
1329 |
|
|
if (ExtModeRegister.DQSB_ENB = '0') then
|
1330 |
|
|
UDQSB <= '1';
|
1331 |
|
|
LDQSB <= '1';
|
1332 |
|
|
else
|
1333 |
|
|
UDQSB <= 'Z';
|
1334 |
|
|
LDQSB <= 'Z';
|
1335 |
|
|
end if;
|
1336 |
|
|
elsif (DQS_S'event and DQS_S = 'Z' and DQS_S /= DQS_S'LAST_VALUE) then
|
1337 |
|
|
UDQS <= 'Z';
|
1338 |
|
|
LDQS <= 'Z';
|
1339 |
|
|
UDQSB <= 'Z';
|
1340 |
|
|
LDQSB <= 'Z';
|
1341 |
|
|
end if;
|
1342 |
|
|
else
|
1343 |
|
|
UDQS <= 'Z';
|
1344 |
|
|
LDQS <= 'Z';
|
1345 |
|
|
UDQSB <= 'Z';
|
1346 |
|
|
LDQSB <= 'Z';
|
1347 |
|
|
end if;
|
1348 |
|
|
end process;
|
1349 |
|
|
|
1350 |
|
|
-----------------------------------------------------------------------------------------------------
|
1351 |
|
|
|
1352 |
|
|
MEMORY_READ : process (DQS_S, CLK_DLY2, ExtModeRegister.OCD_PGM)
|
1353 |
|
|
|
1354 |
|
|
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
1355 |
|
|
variable CRBI : integer := 0;
|
1356 |
|
|
variable i, k, l : integer := 0;
|
1357 |
|
|
begin
|
1358 |
|
|
if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then
|
1359 |
|
|
if (casp6_rd = '1' or (ReadFlag = TRUE and yburst = '1')) then
|
1360 |
|
|
if (casp6_rd = '1') then
|
1361 |
|
|
BkAdd := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto
|
1362 |
|
|
NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2);
|
1363 |
|
|
CRBI := 0;
|
1364 |
|
|
end if;
|
1365 |
|
|
if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then
|
1366 |
|
|
DataBuffer(i, 0) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(0))), WORD_SIZE);
|
1367 |
|
|
DataBuffer(i, 1) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(1))), WORD_SIZE);
|
1368 |
|
|
DataBuffer(i, 2) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(2))), WORD_SIZE);
|
1369 |
|
|
DataBuffer(i, 3) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(3))), WORD_SIZE);
|
1370 |
|
|
i := i + 1;
|
1371 |
|
|
if (i = NUM_OF_BUFFERS) then
|
1372 |
|
|
i := 0;
|
1373 |
|
|
end if;
|
1374 |
|
|
CRBI := CRBI + 4;
|
1375 |
|
|
if (CRBI = ModeRegister.BURST_LENGTH) then
|
1376 |
|
|
ReadFinFlag <= TRUE, FALSE after 2 ns;
|
1377 |
|
|
CRBI := 0;
|
1378 |
|
|
end if;
|
1379 |
|
|
else
|
1380 |
|
|
assert false report
|
1381 |
|
|
"WARNING : (MEMORY_READ_PROCESS) : Accessing deactivated bank."
|
1382 |
|
|
severity WARNING;
|
1383 |
|
|
CRBI := CRBI + 4;
|
1384 |
|
|
if (CRBI = ModeRegister.BURST_LENGTH) then
|
1385 |
|
|
ReadFinFlag <= TRUE, FALSE after 2 ns;
|
1386 |
|
|
CRBI := 0;
|
1387 |
|
|
end if;
|
1388 |
|
|
end if;
|
1389 |
|
|
end if;
|
1390 |
|
|
end if;
|
1391 |
|
|
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then
|
1392 |
|
|
DQ <= (others => '0');
|
1393 |
|
|
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then
|
1394 |
|
|
DQ <= (others => '1');
|
1395 |
|
|
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
|
1396 |
|
|
DQ <= (others => 'Z');
|
1397 |
|
|
end if;
|
1398 |
|
|
if (DQS_S'EVENT and DQS_S = '1' and DQS_S'LAST_VALUE = '0' and WriteFlag = FALSE) then
|
1399 |
|
|
DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle;
|
1400 |
|
|
l := l + 1;
|
1401 |
|
|
elsif (DQS_S'EVENT and DQS_S = '0' and DQS_S'LAST_VALUE = '1' and WriteFlag = FALSE) then
|
1402 |
|
|
DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle;
|
1403 |
|
|
if (l = 3) then
|
1404 |
|
|
l := 0;
|
1405 |
|
|
k := k + 1;
|
1406 |
|
|
if (k = NUM_OF_BUFFERS) then
|
1407 |
|
|
k := 0;
|
1408 |
|
|
end if;
|
1409 |
|
|
else
|
1410 |
|
|
l := l + 1;
|
1411 |
|
|
end if;
|
1412 |
|
|
end if;
|
1413 |
|
|
end process;
|
1414 |
|
|
|
1415 |
|
|
-----------------------------------------------------------------------------------------------------
|
1416 |
|
|
|
1417 |
|
|
BURST_RD_WR_ADDR_GEN : process(CLK_DLY15, casp6_rd, casp6_wt, ReadFlag, WriteFlag)
|
1418 |
|
|
|
1419 |
|
|
variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X');
|
1420 |
|
|
variable i, j : integer := 0;
|
1421 |
|
|
variable col_addr_count : integer := 0;
|
1422 |
|
|
|
1423 |
|
|
begin
|
1424 |
|
|
if ((ReadFlag = FALSE) and (WriteFlag = FALSE)) then
|
1425 |
|
|
real_col_addr(0) <= (others => '0');
|
1426 |
|
|
real_col_addr(1) <= (others => '0');
|
1427 |
|
|
real_col_addr(2) <= (others => '0');
|
1428 |
|
|
real_col_addr(3) <= (others => '0');
|
1429 |
|
|
col_addr_count := 0;
|
1430 |
|
|
i := 0;
|
1431 |
|
|
j := 0;
|
1432 |
|
|
end if;
|
1433 |
|
|
if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1') or
|
1434 |
|
|
(CLK_DLY15'EVENT and CLK_DLY15 = '1' and yburst = '1')) then
|
1435 |
|
|
if (casp6_rd = '1') then
|
1436 |
|
|
CA := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_COL_ADD - 1 downto 0);
|
1437 |
|
|
col_addr_count := 0;
|
1438 |
|
|
i := 0;
|
1439 |
|
|
j := 0;
|
1440 |
|
|
elsif (casp6_wt = '1') then
|
1441 |
|
|
CA := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1)(NUM_OF_COL_ADD - 1 downto 0);
|
1442 |
|
|
col_addr_count := 0;
|
1443 |
|
|
i := 0;
|
1444 |
|
|
j := 0;
|
1445 |
|
|
end if;
|
1446 |
|
|
if (col_addr_count < ModeRegister.BURST_LENGTH/4) then
|
1447 |
|
|
loop
|
1448 |
|
|
exit when (j > 3);
|
1449 |
|
|
if ((col_addr_count = 0) and (j = 0)) then
|
1450 |
|
|
real_col_addr(0) <= CA;
|
1451 |
|
|
elsif (ModeRegister.BURST_LENGTH = 4) then
|
1452 |
|
|
if (ModeRegister.BURST_MODE = SEQUENTIAL) then
|
1453 |
|
|
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)&
|
1454 |
|
|
conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2);
|
1455 |
|
|
elsif (ModeRegister.BURST_MODE = INTERLEAVE) then
|
1456 |
|
|
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)&
|
1457 |
|
|
xor_func(CA(1 downto 0), conv_std_logic_vector(i, 2));
|
1458 |
|
|
end if;
|
1459 |
|
|
elsif (ModeRegister.BURST_LENGTH = 8) then
|
1460 |
|
|
if (ModeRegister.BURST_MODE = SEQUENTIAL) then
|
1461 |
|
|
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)&
|
1462 |
|
|
conv_std_logic_vector((conv_integer(CA(2)) + col_addr_count), 2)(0)&
|
1463 |
|
|
conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2);
|
1464 |
|
|
elsif (ModeRegister.BURST_MODE = INTERLEAVE) then
|
1465 |
|
|
real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)&
|
1466 |
|
|
xor_func(CA(2 downto 0), conv_std_logic_vector(i, 3));
|
1467 |
|
|
end if;
|
1468 |
|
|
end if;
|
1469 |
|
|
i := i + 1;
|
1470 |
|
|
j := j + 1;
|
1471 |
|
|
end loop;
|
1472 |
|
|
end if;
|
1473 |
|
|
j := 0;
|
1474 |
|
|
col_addr_count := col_addr_count + 1;
|
1475 |
|
|
end if;
|
1476 |
|
|
end process;
|
1477 |
|
|
|
1478 |
|
|
-----------------------------------------------------------------------------------------------------
|
1479 |
|
|
|
1480 |
|
|
MEMORY_WRITE : process (CLK_DLY2, LDQS, UDQS, CLK)
|
1481 |
|
|
|
1482 |
|
|
variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
1483 |
|
|
variable TMP_VALUE : std_logic_vector ((WORD_SIZE - 1) downto 0) := (others => '0');
|
1484 |
|
|
variable WriteDriver : SA_TYPE;
|
1485 |
|
|
variable i, j, k, l, m : integer := 0;
|
1486 |
|
|
variable CWBI : integer := 0;
|
1487 |
|
|
variable dq_buffL, dq_buffH : DATA_BUFFER_TYPE;
|
1488 |
|
|
|
1489 |
|
|
begin
|
1490 |
|
|
if (CLK'event and CLK = '1') then
|
1491 |
|
|
dq_buffL(0) := dq_bufferL(0);
|
1492 |
|
|
dq_buffL(1) := dq_bufferL(1);
|
1493 |
|
|
dq_buffL(2) := dq_bufferL(2);
|
1494 |
|
|
dq_buffL(3) := dq_bufferL(3);
|
1495 |
|
|
dq_buffH(0) := dq_bufferH(0);
|
1496 |
|
|
dq_buffH(1) := dq_bufferH(1);
|
1497 |
|
|
dq_buffH(2) := dq_bufferH(2);
|
1498 |
|
|
dq_buffH(3) := dq_bufferH(3);
|
1499 |
|
|
end if;
|
1500 |
|
|
if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then
|
1501 |
|
|
if (casp6_wt = '1' or (WriteFlag = TRUE and yburst = '1')) then
|
1502 |
|
|
if (casp6_wt = '1') then
|
1503 |
|
|
BkAdd := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1)
|
1504 |
|
|
(NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2);
|
1505 |
|
|
CWBI := 0;
|
1506 |
|
|
WriteDriver := SA_ARRAY (conv_integer(BkAdd));
|
1507 |
|
|
end if;
|
1508 |
|
|
if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then
|
1509 |
|
|
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(0))), WORD_SIZE);
|
1510 |
|
|
if (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '0') then
|
1511 |
|
|
TMP_VALUE := (dq_buffH(0)(7 downto 0) & dq_buffL(0)(7 downto 0));
|
1512 |
|
|
elsif (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '1') then
|
1513 |
|
|
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(0)(7 downto 0));
|
1514 |
|
|
elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '0') then
|
1515 |
|
|
TMP_VALUE := (dq_buffH(0)(7 downto 0) & TMP_VALUE(7 downto 0));
|
1516 |
|
|
elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '1') then
|
1517 |
|
|
TMP_VALUE := (TMP_VALUE);
|
1518 |
|
|
end if;
|
1519 |
|
|
WriteDriver (conv_integer(real_col_addr(0))) := conv_integer(TMP_VALUE);
|
1520 |
|
|
|
1521 |
|
|
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(1))), WORD_SIZE);
|
1522 |
|
|
if (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '0') then
|
1523 |
|
|
TMP_VALUE := (dq_buffH(1)(7 downto 0) & dq_buffL(1)(7 downto 0));
|
1524 |
|
|
elsif (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '1') then
|
1525 |
|
|
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(1)(7 downto 0));
|
1526 |
|
|
elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '0') then
|
1527 |
|
|
TMP_VALUE := (dq_buffH(1)(7 downto 0) & TMP_VALUE(7 downto 0));
|
1528 |
|
|
elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '1') then
|
1529 |
|
|
TMP_VALUE := (TMP_VALUE);
|
1530 |
|
|
end if;
|
1531 |
|
|
WriteDriver (conv_integer(real_col_addr(1))) := conv_integer(TMP_VALUE);
|
1532 |
|
|
|
1533 |
|
|
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(2))), WORD_SIZE);
|
1534 |
|
|
if (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '0') then
|
1535 |
|
|
TMP_VALUE := (dq_buffH(2)(7 downto 0) & dq_buffL(2)(7 downto 0));
|
1536 |
|
|
elsif (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '1') then
|
1537 |
|
|
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(2)(7 downto 0));
|
1538 |
|
|
elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '0') then
|
1539 |
|
|
TMP_VALUE := (dq_buffH(2)(7 downto 0) & TMP_VALUE(7 downto 0));
|
1540 |
|
|
elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '1') then
|
1541 |
|
|
TMP_VALUE := (TMP_VALUE);
|
1542 |
|
|
end if;
|
1543 |
|
|
WriteDriver (conv_integer(real_col_addr(2))) := conv_integer(TMP_VALUE);
|
1544 |
|
|
|
1545 |
|
|
TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(3))), WORD_SIZE);
|
1546 |
|
|
if (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '0') then
|
1547 |
|
|
TMP_VALUE := (dq_buffH(3)(7 downto 0) & dq_buffL(3)(7 downto 0));
|
1548 |
|
|
elsif (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '1') then
|
1549 |
|
|
TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(3)(7 downto 0));
|
1550 |
|
|
elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '0') then
|
1551 |
|
|
TMP_VALUE := (dq_buffH(3)(7 downto 0) & TMP_VALUE(7 downto 0));
|
1552 |
|
|
elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '1') then
|
1553 |
|
|
TMP_VALUE := (TMP_VALUE);
|
1554 |
|
|
end if;
|
1555 |
|
|
WriteDriver (conv_integer(real_col_addr(3))) := conv_integer(TMP_VALUE);
|
1556 |
|
|
if (conv_integer(BkAdd) = 0) then
|
1557 |
|
|
SA_ARRAY_W0 <= WriteDriver;
|
1558 |
|
|
tmp_w_trans0 <= '1', '0' after 2 ns;
|
1559 |
|
|
b0_last_data_in <= (now - 2 ns);
|
1560 |
|
|
elsif (conv_integer(BkAdd) = 1) then
|
1561 |
|
|
SA_ARRAY_W1 <= WriteDriver;
|
1562 |
|
|
tmp_w_trans1 <= '1', '0' after 2 ns;
|
1563 |
|
|
b1_last_data_in <= (now - 2 ns);
|
1564 |
|
|
elsif (conv_integer(BkAdd) = 2) then
|
1565 |
|
|
SA_ARRAY_W2 <= WriteDriver;
|
1566 |
|
|
tmp_w_trans2 <= '1', '0' after 2 ns;
|
1567 |
|
|
b2_last_data_in <= (now - 2 ns);
|
1568 |
|
|
elsif (conv_integer(BkAdd) = 3) then
|
1569 |
|
|
SA_ARRAY_W3 <= WriteDriver;
|
1570 |
|
|
tmp_w_trans3 <= '1', '0' after 2 ns;
|
1571 |
|
|
b3_last_data_in <= (now - 2 ns);
|
1572 |
|
|
end if;
|
1573 |
|
|
CWBI := CWBI + 4;
|
1574 |
|
|
if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then
|
1575 |
|
|
WriteFinFlag <= transport TRUE, FALSE after 2 ns;
|
1576 |
|
|
CWBI := 0;
|
1577 |
|
|
end if;
|
1578 |
|
|
else
|
1579 |
|
|
assert false report
|
1580 |
|
|
"WARNING : (MEM_WRITE_PROCESS) : Accessing deactivated bank."
|
1581 |
|
|
severity WARNING;
|
1582 |
|
|
CWBI := CWBI + 4;
|
1583 |
|
|
if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then
|
1584 |
|
|
WriteFinFlag <= transport TRUE, FALSE after 2 ns;
|
1585 |
|
|
CWBI := 0;
|
1586 |
|
|
end if;
|
1587 |
|
|
end if;
|
1588 |
|
|
end if;
|
1589 |
|
|
end if;
|
1590 |
|
|
if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
|
1591 |
|
|
dq_bufferL(2) <= transport dq_bufferL(6);
|
1592 |
|
|
dq_bufferL(1) <= transport dq_bufferL(5);
|
1593 |
|
|
dq_bufferL(0) <= transport dq_bufferL(4);
|
1594 |
|
|
dq_bufferL(3) <= transport (LDM & DQ(7 downto 0));
|
1595 |
|
|
end if;
|
1596 |
|
|
if (LDQS'EVENT and LDQS = '1' and WriteFlag = TRUE) then
|
1597 |
|
|
dq_bufferL(5) <= transport dq_bufferL(3);
|
1598 |
|
|
dq_bufferL(4) <= transport dq_bufferL(2);
|
1599 |
|
|
dq_bufferL(6) <= transport (LDM & DQ(7 downto 0));
|
1600 |
|
|
end if;
|
1601 |
|
|
if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
|
1602 |
|
|
dq_bufferH(2) <= transport dq_bufferH(6);
|
1603 |
|
|
dq_bufferH(1) <= transport dq_bufferH(5);
|
1604 |
|
|
dq_bufferH(0) <= transport dq_bufferH(4);
|
1605 |
|
|
dq_bufferH(3) <= transport (UDM & DQ(15 downto 8));
|
1606 |
|
|
end if;
|
1607 |
|
|
if (UDQS'EVENT and UDQS = '1' and WriteFlag = TRUE) then
|
1608 |
|
|
dq_bufferH(5) <= transport dq_bufferH(3);
|
1609 |
|
|
dq_bufferH(4) <= transport dq_bufferH(2);
|
1610 |
|
|
dq_bufferH(6) <= transport (UDM & DQ(15 downto 8));
|
1611 |
|
|
end if;
|
1612 |
|
|
end process;
|
1613 |
|
|
|
1614 |
|
|
-----------------------------------------------------------------------------------------------------
|
1615 |
|
|
|
1616 |
|
|
REFRESH_COUNTER : process(AutoRefFlag, SelfRefFlag, CLK)
|
1617 |
|
|
|
1618 |
|
|
variable rc : integer := 0;
|
1619 |
|
|
|
1620 |
|
|
begin
|
1621 |
|
|
if (AutoRefFlag'EVENT and AutoRefFlag = TRUE and TimingCheckFlag = TRUE) then
|
1622 |
|
|
if (rc >= 8192) then
|
1623 |
|
|
rc := rc - 8192;
|
1624 |
|
|
end if;
|
1625 |
|
|
if (now - refresh_check(0, rc) > tREF) then
|
1626 |
|
|
assert false report
|
1627 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0"
|
1628 |
|
|
severity warning;
|
1629 |
|
|
end if;
|
1630 |
|
|
if (now - refresh_check(1, rc) > tREF) then
|
1631 |
|
|
assert false report
|
1632 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1"
|
1633 |
|
|
severity warning;
|
1634 |
|
|
end if;
|
1635 |
|
|
if (now - refresh_check(2, rc) > tREF) then
|
1636 |
|
|
assert false report
|
1637 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2"
|
1638 |
|
|
severity warning;
|
1639 |
|
|
end if;
|
1640 |
|
|
if (now - refresh_check(3, rc) > tREF) then
|
1641 |
|
|
assert false report
|
1642 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3"
|
1643 |
|
|
severity warning;
|
1644 |
|
|
end if;
|
1645 |
|
|
tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD);
|
1646 |
|
|
tmp_ref_addr1_trans <= transport '1', '0' after 1 ns;
|
1647 |
|
|
rc := rc + 1;
|
1648 |
|
|
end if;
|
1649 |
|
|
if (CLK'EVENT and CLK = '1') then
|
1650 |
|
|
if (SelfRefFlag = TRUE and TimingCheckFlag = TRUE) then
|
1651 |
|
|
Ref_time <= Ref_time + clk_cycle;
|
1652 |
|
|
if (Ref_time >= 7812.5 ns/(conv_integer(ExtModeRegister2.SREF_HOT) + 1)) then
|
1653 |
|
|
Ref_time <= 0 ns;
|
1654 |
|
|
if (rc >= 8192) then
|
1655 |
|
|
rc := rc - 8192;
|
1656 |
|
|
end if;
|
1657 |
|
|
if (now - refresh_check(0, rc) > tREF) then
|
1658 |
|
|
assert false report
|
1659 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0"
|
1660 |
|
|
severity warning;
|
1661 |
|
|
end if;
|
1662 |
|
|
if (now - refresh_check(1, rc) > tREF) then
|
1663 |
|
|
assert false report
|
1664 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1"
|
1665 |
|
|
severity warning;
|
1666 |
|
|
end if;
|
1667 |
|
|
if (now - refresh_check(2, rc) > tREF) then
|
1668 |
|
|
assert false report
|
1669 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2"
|
1670 |
|
|
severity warning;
|
1671 |
|
|
end if;
|
1672 |
|
|
if (now - refresh_check(3, rc) > tREF) then
|
1673 |
|
|
assert false report
|
1674 |
|
|
"WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3"
|
1675 |
|
|
severity warning;
|
1676 |
|
|
end if;
|
1677 |
|
|
tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD);
|
1678 |
|
|
tmp_ref_addr1_trans <= transport '1', '0' after 1 ns;
|
1679 |
|
|
rc := rc + 1;
|
1680 |
|
|
end if;
|
1681 |
|
|
end if;
|
1682 |
|
|
end if;
|
1683 |
|
|
if (SelfRefFlag = FALSE) then
|
1684 |
|
|
Ref_time <= 0 ns;
|
1685 |
|
|
end if;
|
1686 |
|
|
end process;
|
1687 |
|
|
|
1688 |
|
|
-----------------------------------------------------------------------------------------------------
|
1689 |
|
|
|
1690 |
|
|
PUS_CHECK : process(CLK, PrechargeAllFlag, AutoRefFlag, ModeRegister.DLL_STATE)
|
1691 |
|
|
|
1692 |
|
|
variable ChipSelectBar : std_logic := '0';
|
1693 |
|
|
variable RowAddrStrobeBar : std_logic := '0';
|
1694 |
|
|
variable ColAddrStrobeBar : std_logic := '0';
|
1695 |
|
|
variable WriteEnableBar : std_logic := '0';
|
1696 |
|
|
variable Address10 : std_logic := '0';
|
1697 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
1698 |
|
|
variable ClockEnable : CKE_TYPE := (others => '0');
|
1699 |
|
|
variable CurrentCommand : COMMAND_TYPE := NOP;
|
1700 |
|
|
variable i, j : integer := 0;
|
1701 |
|
|
variable PUSNOP200USFlag : boolean := FALSE;
|
1702 |
|
|
variable PUSAREF2Flag : boolean := FALSE;
|
1703 |
|
|
variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0');
|
1704 |
|
|
variable pus_aref : integer := 0;
|
1705 |
|
|
variable Cur_State : STATE_TYPE := IDLE;
|
1706 |
|
|
|
1707 |
|
|
begin
|
1708 |
|
|
if (PUSCheckFinFlag /= TRUE and PUSCheckFlag = TRUE) then
|
1709 |
|
|
if (CLK'EVENT and CLK = '1') then
|
1710 |
|
|
cur_time <= transport now;
|
1711 |
|
|
-- if (cur_time < 200000 ns) then
|
1712 |
|
|
-- if (CKE /= '0') then
|
1713 |
|
|
-- assert false report
|
1714 |
|
|
-- "ERROR : (Power Up Sequence) : CKE Should Be '0' during initial 200us!"
|
1715 |
|
|
-- severity error;
|
1716 |
|
|
-- end if;
|
1717 |
|
|
-- end if;
|
1718 |
|
|
end if;
|
1719 |
|
|
if (ModeRegister.DLL_STATE'EVENT and ModeRegister.DLL_STATE = RST and PUS_DLL_RESET = FALSE) then
|
1720 |
|
|
PUS_DLL_RESET <= TRUE;
|
1721 |
|
|
end if;
|
1722 |
|
|
if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE and CurrentState = PWRUP and TimingCheckFlag = TRUE) then
|
1723 |
|
|
if (PUSPCGAFlag1 = TRUE) then
|
1724 |
|
|
assert (PUS_DLL_RESET = TRUE) report
|
1725 |
|
|
"ERROR : (Power Up Sequence) : The 2nd PCGA Command Should Be Issued after DLL Reset!"
|
1726 |
|
|
severity error;
|
1727 |
|
|
else
|
1728 |
|
|
PUSPCGAFlag1 <= TRUE;
|
1729 |
|
|
-- assert (cur_time >= tPUS - clk_cycle) report
|
1730 |
|
|
-- "WARNING : (Power Up Sequence) : PCGA Command Should Be Issued after 200us(Input Stable)!"
|
1731 |
|
|
-- severity warning;
|
1732 |
|
|
end if;
|
1733 |
|
|
end if;
|
1734 |
|
|
if (AutoRefFlag'EVENT and AutoRefFlag = TRUE) then
|
1735 |
|
|
assert (PUSPCGAFlag2 = TRUE) report
|
1736 |
|
|
"WARNING : (Power Up Sequence) : Needs Precharge All Bank Command before Auto Refresh !"
|
1737 |
|
|
severity warning;
|
1738 |
|
|
pus_aref := pus_aref + 1;
|
1739 |
|
|
if (pus_aref >= 2) then
|
1740 |
|
|
PUSAREF2Flag := TRUE;
|
1741 |
|
|
end if;
|
1742 |
|
|
if ((PUSNOP200USFlag = TRUE) and (PUSAREF2Flag = TRUE)) then
|
1743 |
|
|
PUSCheckFinFlag <= TRUE;
|
1744 |
|
|
end if;
|
1745 |
|
|
end if;
|
1746 |
|
|
ClockEnable := CKEN;
|
1747 |
|
|
if ClockEnable (-1) = '1' then
|
1748 |
|
|
ChipSelectBar := CSB;
|
1749 |
|
|
RowAddrStrobeBar := RASB;
|
1750 |
|
|
ColAddrStrobeBar := CASB;
|
1751 |
|
|
WriteEnableBar := WEB;
|
1752 |
|
|
Address10 := ADDR(10);
|
1753 |
|
|
BkAdd := (BA);
|
1754 |
|
|
BankActFlag := BankActivatedFlag;
|
1755 |
|
|
end if;
|
1756 |
|
|
COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar, WriteEnableBar,
|
1757 |
|
|
Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State);
|
1758 |
|
|
if ((PUSNOP200USFlag = FALSE) and (PUSAREF2Flag /= TRUE)) then
|
1759 |
|
|
if (CLK = '1') then
|
1760 |
|
|
i := i + 1;
|
1761 |
|
|
-- if (i * clk_cycle >= tPUS - clk_cycle) then
|
1762 |
|
|
PUSNOP200USFlag := TRUE;
|
1763 |
|
|
-- end if;
|
1764 |
|
|
end if;
|
1765 |
|
|
elsif ((CurrentCommand = PCGA) and (PUSNOP200USFlag = TRUE) and (PUSPCGAFlag1 = TRUE) and (PUSAREF2Flag /= TRUE)) then
|
1766 |
|
|
PUSPCGAFlag2 <= TRUE;
|
1767 |
|
|
end if;
|
1768 |
|
|
elsif (PUSCheckFinFlag /= TRUE and PUSCheckFlag = FALSE) then
|
1769 |
|
|
PUSCheckFinFlag <= TRUE;
|
1770 |
|
|
end if;
|
1771 |
|
|
end process;
|
1772 |
|
|
|
1773 |
|
|
-----------------------------------------------------------------------------------------------------
|
1774 |
|
|
|
1775 |
|
|
BUS_CHANGE_DETECT : process(CKE, WEB, CASB, RASB, CSB, LDM, UDM, ADDR, DQ)
|
1776 |
|
|
|
1777 |
|
|
begin
|
1778 |
|
|
if (CKE'EVENT and CKE /= CKE'LAST_VALUE) then
|
1779 |
|
|
cke_ch <= transport now after 0.1 ns; end if;
|
1780 |
|
|
if (WEB'EVENT and WEB /= WEB'LAST_VALUE) then
|
1781 |
|
|
web_ch <= transport now after 0.1 ns; end if;
|
1782 |
|
|
if (CASB'EVENT and CASB /= CASB'LAST_VALUE) then
|
1783 |
|
|
casb_ch <= transport now after 0.1 ns; end if;
|
1784 |
|
|
if (RASB'EVENT and RASB /= RASB'LAST_VALUE) then
|
1785 |
|
|
rasb_ch <= transport now after 0.1 ns; end if;
|
1786 |
|
|
if (CSB'EVENT and CSB /= CSB'LAST_VALUE) then
|
1787 |
|
|
csb_ch <= transport now after 0.1 ns; end if;
|
1788 |
|
|
if (LDM'EVENT and LDM /= LDM'LAST_VALUE) then
|
1789 |
|
|
ldm_ch <= transport now after 0.1 ns; end if;
|
1790 |
|
|
if (UDM'EVENT and UDM /= UDM'LAST_VALUE) then
|
1791 |
|
|
udm_ch <= transport now after 0.1 ns; end if;
|
1792 |
|
|
if (ADDR(0)'EVENT and ADDR(0) /= ADDR(0)'LAST_VALUE) then
|
1793 |
|
|
a0_ch <= transport now after 0.1 ns; end if;
|
1794 |
|
|
if (ADDR(1)'EVENT and ADDR(1) /= ADDR(1)'LAST_VALUE) then
|
1795 |
|
|
a1_ch <= transport now after 0.1 ns; end if;
|
1796 |
|
|
if (ADDR(2)'EVENT and ADDR(2) /= ADDR(2)'LAST_VALUE) then
|
1797 |
|
|
a2_ch <= transport now after 0.1 ns; end if;
|
1798 |
|
|
if (ADDR(3)'EVENT and ADDR(3) /= ADDR(3)'LAST_VALUE) then
|
1799 |
|
|
a3_ch <= transport now after 0.1 ns; end if;
|
1800 |
|
|
if (ADDR(4)'EVENT and ADDR(4) /= ADDR(4)'LAST_VALUE) then
|
1801 |
|
|
a4_ch <= transport now after 0.1 ns; end if;
|
1802 |
|
|
if (ADDR(5)'EVENT and ADDR(5) /= ADDR(5)'LAST_VALUE) then
|
1803 |
|
|
a5_ch <= transport now after 0.1 ns; end if;
|
1804 |
|
|
if (ADDR(6)'EVENT and ADDR(6) /= ADDR(6)'LAST_VALUE) then
|
1805 |
|
|
a6_ch <= transport now after 0.1 ns; end if;
|
1806 |
|
|
if (ADDR(7)'EVENT and ADDR(7) /= ADDR(7)'LAST_VALUE) then
|
1807 |
|
|
a7_ch <= transport now after 0.1 ns; end if;
|
1808 |
|
|
if (ADDR(8)'EVENT and ADDR(8) /= ADDR(8)'LAST_VALUE) then
|
1809 |
|
|
a8_ch <= transport now after 0.1 ns; end if;
|
1810 |
|
|
if (ADDR(9)'EVENT and ADDR(9) /= ADDR(9)'LAST_VALUE) then
|
1811 |
|
|
a9_ch <= transport now after 0.1 ns; end if;
|
1812 |
|
|
if (ADDR(10)'EVENT and ADDR(10) /= ADDR(10)'LAST_VALUE) then
|
1813 |
|
|
a10_ch <= transport now after 0.1 ns; end if;
|
1814 |
|
|
if (ADDR(11)'EVENT and ADDR(11) /= ADDR(11)'LAST_VALUE) then
|
1815 |
|
|
a11_ch <= transport now after 0.1 ns; end if;
|
1816 |
|
|
if (ADDR(12)'EVENT and ADDR(12) /= ADDR(12)'LAST_VALUE) then
|
1817 |
|
|
a12_ch <= transport now after 0.1 ns; end if;
|
1818 |
|
|
if (BA(0)'EVENT and BA(0) /= BA(0)'LAST_VALUE) then
|
1819 |
|
|
ba0_ch <= transport now after 0.1 ns; end if;
|
1820 |
|
|
if (BA(1)'EVENT and BA(1) /= BA(1)'LAST_VALUE) then
|
1821 |
|
|
ba1_ch <= transport now after 0.1 ns; end if;
|
1822 |
|
|
if (DQ(0)'EVENT and STD_LOGIC_TO_BIT (DQ(0)) /= STD_LOGIC_TO_BIT (DQ(0)'LAST_VALUE)) then
|
1823 |
|
|
dq0_ch <= transport now after 0.1 ns; end if;
|
1824 |
|
|
if (DQ(1)'EVENT and STD_LOGIC_TO_BIT (DQ(1)) /= STD_LOGIC_TO_BIT (DQ(1)'LAST_VALUE)) then
|
1825 |
|
|
dq1_ch <= transport now after 0.1 ns; end if;
|
1826 |
|
|
if (DQ(2)'EVENT and STD_LOGIC_TO_BIT (DQ(2)) /= STD_LOGIC_TO_BIT (DQ(2)'LAST_VALUE)) then
|
1827 |
|
|
dq2_ch <= transport now after 0.1 ns; end if;
|
1828 |
|
|
if (DQ(3)'EVENT and STD_LOGIC_TO_BIT (DQ(3)) /= STD_LOGIC_TO_BIT (DQ(3)'LAST_VALUE)) then
|
1829 |
|
|
dq3_ch <= transport now after 0.1 ns; end if;
|
1830 |
|
|
if (DQ(4)'EVENT and STD_LOGIC_TO_BIT (DQ(4)) /= STD_LOGIC_TO_BIT (DQ(4)'LAST_VALUE)) then
|
1831 |
|
|
dq4_ch <= transport now after 0.1 ns; end if;
|
1832 |
|
|
if (DQ(5)'EVENT and STD_LOGIC_TO_BIT (DQ(5)) /= STD_LOGIC_TO_BIT (DQ(5)'LAST_VALUE)) then
|
1833 |
|
|
dq5_ch <= transport now after 0.1 ns; end if;
|
1834 |
|
|
if (DQ(6)'EVENT and STD_LOGIC_TO_BIT (DQ(6)) /= STD_LOGIC_TO_BIT (DQ(6)'LAST_VALUE)) then
|
1835 |
|
|
dq6_ch <= transport now after 0.1 ns; end if;
|
1836 |
|
|
if (DQ(7)'EVENT and STD_LOGIC_TO_BIT (DQ(7)) /= STD_LOGIC_TO_BIT (DQ(7)'LAST_VALUE)) then
|
1837 |
|
|
dq7_ch <= transport now after 0.1 ns; end if;
|
1838 |
|
|
if (DQ(8)'EVENT and STD_LOGIC_TO_BIT (DQ(8)) /= STD_LOGIC_TO_BIT (DQ(8)'LAST_VALUE)) then
|
1839 |
|
|
dq8_ch <= transport now after 0.1 ns; end if;
|
1840 |
|
|
if (DQ(9)'EVENT and STD_LOGIC_TO_BIT (DQ(9)) /= STD_LOGIC_TO_BIT (DQ(9)'LAST_VALUE)) then
|
1841 |
|
|
dq9_ch <= transport now after 0.1 ns; end if;
|
1842 |
|
|
if (DQ(10)'EVENT and STD_LOGIC_TO_BIT (DQ(10)) /= STD_LOGIC_TO_BIT (DQ(10)'LAST_VALUE)) then
|
1843 |
|
|
dq10_ch <= transport now after 0.1 ns; end if;
|
1844 |
|
|
if (DQ(11)'EVENT and STD_LOGIC_TO_BIT (DQ(11)) /= STD_LOGIC_TO_BIT (DQ(11)'LAST_VALUE)) then
|
1845 |
|
|
dq11_ch <= transport now after 0.1 ns; end if;
|
1846 |
|
|
if (DQ(12)'EVENT and STD_LOGIC_TO_BIT (DQ(12)) /= STD_LOGIC_TO_BIT (DQ(12)'LAST_VALUE)) then
|
1847 |
|
|
dq12_ch <= transport now after 0.1 ns; end if;
|
1848 |
|
|
if (DQ(13)'EVENT and STD_LOGIC_TO_BIT (DQ(13)) /= STD_LOGIC_TO_BIT (DQ(13)'LAST_VALUE)) then
|
1849 |
|
|
dq13_ch <= transport now after 0.1 ns; end if;
|
1850 |
|
|
if (DQ(14)'EVENT and STD_LOGIC_TO_BIT (DQ(14)) /= STD_LOGIC_TO_BIT (DQ(14)'LAST_VALUE)) then
|
1851 |
|
|
dq14_ch <= transport now after 0.1 ns; end if;
|
1852 |
|
|
if (DQ(15)'EVENT and STD_LOGIC_TO_BIT (DQ(15)) /= STD_LOGIC_TO_BIT (DQ(15)'LAST_VALUE)) then
|
1853 |
|
|
dq15_ch <= transport now after 0.1 ns; end if;
|
1854 |
|
|
end process;
|
1855 |
|
|
|
1856 |
|
|
-----------------------------------------------------------------------------------------------------
|
1857 |
|
|
|
1858 |
|
|
CLK_TIMING : process (CLK)
|
1859 |
|
|
variable clk_last_cycle : time := 0 ns;
|
1860 |
|
|
variable i : integer := 0;
|
1861 |
|
|
begin
|
1862 |
|
|
if (CLK'event and CLK='1') then
|
1863 |
|
|
if (Part_Number = B400) then
|
1864 |
|
|
tRCD <= ModeRegister.CAS_LATENCY * 5 ns;
|
1865 |
|
|
tRP <= ModeRegister.CAS_LATENCY * 5 ns;
|
1866 |
|
|
if (ModeRegister.CAS_LATENCY = 3) then
|
1867 |
|
|
tRAS <= 40 ns;
|
1868 |
|
|
else
|
1869 |
|
|
tRAS <= 45 ns;
|
1870 |
|
|
end if;
|
1871 |
|
|
elsif (Part_Number = B533) then
|
1872 |
|
|
tRCD <= ModeRegister.CAS_LATENCY * 3.75 ns;
|
1873 |
|
|
tRP <= ModeRegister.CAS_LATENCY * 3.75 ns;
|
1874 |
|
|
tRAS <= 45 ns;
|
1875 |
|
|
elsif (Part_Number = B667) then
|
1876 |
|
|
tRCD <= ModeRegister.CAS_LATENCY * 3 ns;
|
1877 |
|
|
tRP <= ModeRegister.CAS_LATENCY * 3 ns;
|
1878 |
|
|
tRAS <= 45 ns;
|
1879 |
|
|
elsif (Part_Number = B800) then
|
1880 |
|
|
tRCD <= ModeRegister.CAS_LATENCY * 2.5 ns;
|
1881 |
|
|
tRP <= ModeRegister.CAS_LATENCY * 2.5 ns;
|
1882 |
|
|
tRAS <= 45 ns;
|
1883 |
|
|
end if;
|
1884 |
|
|
tRC <= tRAS + tRP;
|
1885 |
|
|
tCCD <= 2 * clk_cycle;
|
1886 |
|
|
tDQSH <= 0.35 * clk_cycle;
|
1887 |
|
|
tDQSL <= 0.35 * clk_cycle;
|
1888 |
|
|
tWPSTmin <= 0.4 * clk_cycle;
|
1889 |
|
|
tWPSTmax <= 0.6 * clk_cycle;
|
1890 |
|
|
tDQSSmin <= 0.75 * clk_cycle;
|
1891 |
|
|
tDQSSmax <= 1.25 * clk_cycle;
|
1892 |
|
|
tMRD <= 2 * clk_cycle;
|
1893 |
|
|
tWPRE <= 0.25 * clk_cycle;
|
1894 |
|
|
tCH <= 0.45 * clk_cycle;
|
1895 |
|
|
tCL <= 0.45 * clk_cycle;
|
1896 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
1897 |
|
|
assert (clk_cycle >= tCKmin (Part_Number)) report
|
1898 |
|
|
"ERROR : (CLK_TIMING) : Clock period is too small."
|
1899 |
|
|
severity error;
|
1900 |
|
|
assert (clk_cycle <= tCKmax (Part_Number)) report
|
1901 |
|
|
"ERROR : (CLK_TIMING) : Clock period is too large."
|
1902 |
|
|
severity error;
|
1903 |
|
|
end if;
|
1904 |
|
|
assert (now - clk_last_falling >= tCL) report
|
1905 |
|
|
"ERROR : (CLK_TIMING) : Clock low time is too small."
|
1906 |
|
|
severity error;
|
1907 |
|
|
clk_last_rising <= transport now;
|
1908 |
|
|
end if;
|
1909 |
|
|
if (CLK'event and CLK = '0') then
|
1910 |
|
|
clk_last_falling <= transport now;
|
1911 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
1912 |
|
|
assert (now - clk_last_rising >= tCH) report
|
1913 |
|
|
"ERROR : (CLK_TIMING) : Clock high time is too small."
|
1914 |
|
|
severity error;
|
1915 |
|
|
end if;
|
1916 |
|
|
end if;
|
1917 |
|
|
end process;
|
1918 |
|
|
|
1919 |
|
|
-----------------------------------------------------------------------------------------------------
|
1920 |
|
|
|
1921 |
|
|
DQS_TIMING : process (LDQS, UDQS, caspwt)
|
1922 |
|
|
|
1923 |
|
|
begin
|
1924 |
|
|
if (caspwt'EVENT and caspwt = '1') then
|
1925 |
|
|
wr_cmd_time <= transport now - 1 ns;
|
1926 |
|
|
udspre_enable <= '0';
|
1927 |
|
|
ldspre_enable <= '0';
|
1928 |
|
|
udsh_dsl_enable <= '0';
|
1929 |
|
|
ldsh_dsl_enable <= '0';
|
1930 |
|
|
end if;
|
1931 |
|
|
if (TimingCheckFlag = TRUE) then
|
1932 |
|
|
if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then
|
1933 |
|
|
udspre_enable <= '1';
|
1934 |
|
|
end if;
|
1935 |
|
|
if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then
|
1936 |
|
|
ldspre_enable <= '1';
|
1937 |
|
|
end if;
|
1938 |
|
|
if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
|
1939 |
|
|
udqs_last_rising <= transport now;
|
1940 |
|
|
if (udspre_enable = '1') then
|
1941 |
|
|
if ((now - clk_last_falling) < tWPRE) then
|
1942 |
|
|
assert false report
|
1943 |
|
|
"WARNING : (tWPRE_CHECK) : tWPRE time violation!"
|
1944 |
|
|
severity WARNING;
|
1945 |
|
|
end if;
|
1946 |
|
|
if ((now - wr_cmd_time) < tDQSSmin) then
|
1947 |
|
|
assert false report
|
1948 |
|
|
"WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!"
|
1949 |
|
|
severity WARNING;
|
1950 |
|
|
end if;
|
1951 |
|
|
if ((now - wr_cmd_time) > tDQSSmax) then
|
1952 |
|
|
assert false report
|
1953 |
|
|
"WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!"
|
1954 |
|
|
severity WARNING;
|
1955 |
|
|
end if;
|
1956 |
|
|
udspre_enable <= '0';
|
1957 |
|
|
udsh_dsl_enable <= '1';
|
1958 |
|
|
elsif (udsh_dsl_enable = '1') then
|
1959 |
|
|
if ((now - udqs_last_falling) < tDQSL) then
|
1960 |
|
|
assert false report
|
1961 |
|
|
"ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!"
|
1962 |
|
|
severity ERROR;
|
1963 |
|
|
end if;
|
1964 |
|
|
end if;
|
1965 |
|
|
elsif (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
|
1966 |
|
|
udqs_last_falling <= transport now;
|
1967 |
|
|
if (udsh_dsl_enable = '1') then
|
1968 |
|
|
if ((now - udqs_last_rising) < tDQSH) then
|
1969 |
|
|
assert false report
|
1970 |
|
|
"ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!"
|
1971 |
|
|
severity ERROR;
|
1972 |
|
|
end if;
|
1973 |
|
|
end if;
|
1974 |
|
|
udspre_enable <= '0';
|
1975 |
|
|
ldspre_enable <= '0';
|
1976 |
|
|
end if;
|
1977 |
|
|
if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
|
1978 |
|
|
ldqs_last_rising <= transport now;
|
1979 |
|
|
if (ldspre_enable = '1') then
|
1980 |
|
|
if ((now - clk_last_falling) < tWPRE) then
|
1981 |
|
|
assert false report
|
1982 |
|
|
"WARNING : (tWPRE_CHECK) : tWPRE time violation!"
|
1983 |
|
|
severity WARNING;
|
1984 |
|
|
end if;
|
1985 |
|
|
if ((now - wr_cmd_time) < tDQSSmin) then
|
1986 |
|
|
assert false report
|
1987 |
|
|
"WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!"
|
1988 |
|
|
severity WARNING;
|
1989 |
|
|
end if;
|
1990 |
|
|
if ((now - wr_cmd_time) > tDQSSmax) then
|
1991 |
|
|
assert false report
|
1992 |
|
|
"WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!"
|
1993 |
|
|
severity WARNING;
|
1994 |
|
|
end if;
|
1995 |
|
|
ldspre_enable <= '0';
|
1996 |
|
|
ldsh_dsl_enable <= '1';
|
1997 |
|
|
elsif (ldsh_dsl_enable = '1') then
|
1998 |
|
|
if ((now - ldqs_last_falling) < tDQSL) then
|
1999 |
|
|
assert false report
|
2000 |
|
|
"ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!"
|
2001 |
|
|
severity ERROR;
|
2002 |
|
|
end if;
|
2003 |
|
|
end if;
|
2004 |
|
|
elsif (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then
|
2005 |
|
|
ldqs_last_falling <= transport now;
|
2006 |
|
|
if (ldsh_dsl_enable = '1') then
|
2007 |
|
|
if ((now - ldqs_last_rising) < tDQSH) then
|
2008 |
|
|
assert false report
|
2009 |
|
|
"ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!"
|
2010 |
|
|
severity ERROR;
|
2011 |
|
|
end if;
|
2012 |
|
|
end if;
|
2013 |
|
|
udspre_enable <= '0';
|
2014 |
|
|
ldspre_enable <= '0';
|
2015 |
|
|
end if;
|
2016 |
|
|
if (LDQS'EVENT and LDQS = 'Z' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then
|
2017 |
|
|
if ((now - ldqs_last_falling) < tWPSTmin) then
|
2018 |
|
|
assert false report
|
2019 |
|
|
"WARNING : (tWPST_CHECK) : Minimum tWPST time violation!"
|
2020 |
|
|
severity WARNING;
|
2021 |
|
|
end if;
|
2022 |
|
|
if ((now - ldqs_last_falling) > tWPSTmax) then
|
2023 |
|
|
assert false report
|
2024 |
|
|
"WARNING : (tWPST_CHECK) : Maximum tWPST time violation!"
|
2025 |
|
|
severity WARNING;
|
2026 |
|
|
end if;
|
2027 |
|
|
ldspre_enable <= '0';
|
2028 |
|
|
ldsh_dsl_enable <= '0';
|
2029 |
|
|
end if;
|
2030 |
|
|
if (UDQS'EVENT and UDQS = 'Z' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then
|
2031 |
|
|
if ((now - udqs_last_falling) < tWPSTmin) then
|
2032 |
|
|
assert false report
|
2033 |
|
|
"WARNING : (tWPST_CHECK) : Minimum tWPST time violation!"
|
2034 |
|
|
severity WARNING;
|
2035 |
|
|
end if;
|
2036 |
|
|
if ((now - udqs_last_falling) > tWPSTmax) then
|
2037 |
|
|
assert false report
|
2038 |
|
|
"WARNING : (tWPST_CHECK) : Maximum tWPST time violation!"
|
2039 |
|
|
severity WARNING;
|
2040 |
|
|
end if;
|
2041 |
|
|
udspre_enable <= '0';
|
2042 |
|
|
udsh_dsl_enable <= '0';
|
2043 |
|
|
end if;
|
2044 |
|
|
end if;
|
2045 |
|
|
end process;
|
2046 |
|
|
|
2047 |
|
|
-----------------------------------------------------------------------------------------------------
|
2048 |
|
|
|
2049 |
|
|
SETUP_CHECK : process (CLK, UDQS, LDQS)
|
2050 |
|
|
begin
|
2051 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2052 |
|
|
if (((UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0') or (UDQS'EVENT and UDQS = '0') or
|
2053 |
|
|
(LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0') or (LDQS'EVENT and LDQS = '0')) and
|
2054 |
|
|
(WriteFlag = TRUE)) then
|
2055 |
|
|
assert (
|
2056 |
|
|
((now - dq0_ch) >= tDS (Part_Number)) and
|
2057 |
|
|
((now - dq1_ch) >= tDS (Part_Number)) and
|
2058 |
|
|
((now - dq2_ch) >= tDS (Part_Number)) and
|
2059 |
|
|
((now - dq3_ch) >= tDS (Part_Number)) and
|
2060 |
|
|
((now - dq4_ch) >= tDS (Part_Number)) and
|
2061 |
|
|
((now - dq5_ch) >= tDS (Part_Number)) and
|
2062 |
|
|
((now - dq6_ch) >= tDS (Part_Number)) and
|
2063 |
|
|
((now - dq7_ch) >= tDS (Part_Number)) and
|
2064 |
|
|
((now - dq8_ch) >= tDS (Part_Number)) and
|
2065 |
|
|
((now - dq9_ch) >= tDS (Part_Number)) and
|
2066 |
|
|
((now - dq10_ch) >= tDS (Part_Number)) and
|
2067 |
|
|
((now - dq11_ch) >= tDS (Part_Number)) and
|
2068 |
|
|
((now - dq12_ch) >= tDS (Part_Number)) and
|
2069 |
|
|
((now - dq13_ch) >= tDS (Part_Number)) and
|
2070 |
|
|
((now - dq14_ch) >= tDS (Part_Number)) and
|
2071 |
|
|
((now - dq15_ch) >= tDS (Part_Number))) report
|
2072 |
|
|
"ERROR : (SETUP_HOLD) : Data input setup/hold time violation."
|
2073 |
|
|
severity error;
|
2074 |
|
|
end if;
|
2075 |
|
|
if (CLK'EVENT and CLK = '1') then
|
2076 |
|
|
assert (
|
2077 |
|
|
((now - a0_ch) >= tIS (Part_Number)) and
|
2078 |
|
|
((now - a1_ch) >= tIS (Part_Number)) and
|
2079 |
|
|
((now - a2_ch) >= tIS (Part_Number)) and
|
2080 |
|
|
((now - a3_ch) >= tIS (Part_Number)) and
|
2081 |
|
|
((now - a4_ch) >= tIS (Part_Number)) and
|
2082 |
|
|
((now - a5_ch) >= tIS (Part_Number)) and
|
2083 |
|
|
((now - a6_ch) >= tIS (Part_Number)) and
|
2084 |
|
|
((now - a7_ch) >= tIS (Part_Number)) and
|
2085 |
|
|
((now - a8_ch) >= tIS (Part_Number)) and
|
2086 |
|
|
((now - a9_ch) >= tIS (Part_Number)) and
|
2087 |
|
|
((now - a10_ch) >= tIS (Part_Number)) and
|
2088 |
|
|
((now - a11_ch) >= tIS (Part_Number)) and
|
2089 |
|
|
((now - a12_ch) >= tIS (Part_Number)) and
|
2090 |
|
|
((now - ba0_ch) >= tIS (Part_Number)) and
|
2091 |
|
|
((now - ba1_ch) >= tIS (Part_Number))) report
|
2092 |
|
|
"ERROR : (SETUP_HOLD) : Address input setup time violation."
|
2093 |
|
|
severity error;
|
2094 |
|
|
assert (
|
2095 |
|
|
((now - csb_ch) >= tIS (Part_Number)) and
|
2096 |
|
|
((now - rasb_ch) >= tIS (Part_Number)) and
|
2097 |
|
|
((now - casb_ch) >= tIS (Part_Number)) and
|
2098 |
|
|
((now - web_ch) >= tIS (Part_Number))) report
|
2099 |
|
|
"ERROR : (SETUP_HOLD) : Command input setup time violation."
|
2100 |
|
|
severity error;
|
2101 |
|
|
assert (now - cke_ch >= tIS (Part_Number)) report
|
2102 |
|
|
"ERROR : (SETUP_HOLD) : Clock enable input setup time violation."
|
2103 |
|
|
severity error;
|
2104 |
|
|
end if;
|
2105 |
|
|
end if;
|
2106 |
|
|
end process;
|
2107 |
|
|
|
2108 |
|
|
-----------------------------------------------------------------------------------------------------
|
2109 |
|
|
|
2110 |
|
|
DM_SETUP_HOLD_CHECK : process (LDM, UDM, LDQS, UDQS)
|
2111 |
|
|
begin
|
2112 |
|
|
if (TimingCheckFlag = TRUE) then
|
2113 |
|
|
if (LDM'EVENT and LDM = '1' and WriteFlag = TRUE) then
|
2114 |
|
|
ldm_last_rising <= transport now;
|
2115 |
|
|
elsif (LDM'EVENT and LDM = '0' and WriteFlag = TRUE) then
|
2116 |
|
|
if ((now - ldqs_last_rising) < tDH (Part_Number)) then
|
2117 |
|
|
assert false report
|
2118 |
|
|
"ERROR : (tDH_CHECK) : LDM Hold Time Violation!"
|
2119 |
|
|
severity ERROR;
|
2120 |
|
|
end if;
|
2121 |
|
|
end if;
|
2122 |
|
|
if (UDM'EVENT and UDM = '1' and WriteFlag = TRUE) then
|
2123 |
|
|
udm_last_rising <= transport now;
|
2124 |
|
|
elsif (UDM'EVENT and UDM = '0' and WriteFlag = TRUE) then
|
2125 |
|
|
if ((now - udqs_last_rising) < tDH (Part_Number)) then
|
2126 |
|
|
assert false report
|
2127 |
|
|
"ERROR : (tDH_CHECK) : UDM Hold Time Violation!"
|
2128 |
|
|
severity ERROR;
|
2129 |
|
|
end if;
|
2130 |
|
|
end if;
|
2131 |
|
|
if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
|
2132 |
|
|
if ((now - ldm_last_rising) < tDS (Part_Number)) then
|
2133 |
|
|
assert false report
|
2134 |
|
|
"ERROR : (tDS_CHECK) : LDM Setup Time Violation!"
|
2135 |
|
|
severity ERROR;
|
2136 |
|
|
end if;
|
2137 |
|
|
end if;
|
2138 |
|
|
if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then
|
2139 |
|
|
if ((now - udm_last_rising) < tDS (Part_Number)) then
|
2140 |
|
|
assert false report
|
2141 |
|
|
"ERROR : (tDS_CHECK) : UDM Setup Time Violation!"
|
2142 |
|
|
severity ERROR;
|
2143 |
|
|
end if;
|
2144 |
|
|
end if;
|
2145 |
|
|
end if;
|
2146 |
|
|
end process;
|
2147 |
|
|
-----------------------------------------------------------------------------------------------------
|
2148 |
|
|
|
2149 |
|
|
A_HOLD_CHECK : process (ADDR)
|
2150 |
|
|
begin
|
2151 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2152 |
|
|
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
|
2153 |
|
|
"ERROR : (SETUP_HOLD) : Address hold time violation."
|
2154 |
|
|
severity error;
|
2155 |
|
|
end if;
|
2156 |
|
|
end process;
|
2157 |
|
|
|
2158 |
|
|
-----------------------------------------------------------------------------------------------------
|
2159 |
|
|
|
2160 |
|
|
UDQ_HOLD_CHECK : process (DQ(15 downto 8))
|
2161 |
|
|
begin
|
2162 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then
|
2163 |
|
|
assert ((now - udqs_last_rising) >= tDH (Part_Number)) report
|
2164 |
|
|
"ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data."
|
2165 |
|
|
severity error;
|
2166 |
|
|
assert ((now - udqs_last_falling) >= tDH (Part_Number)) report
|
2167 |
|
|
"ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data."
|
2168 |
|
|
severity error;
|
2169 |
|
|
end if;
|
2170 |
|
|
end process;
|
2171 |
|
|
|
2172 |
|
|
-----------------------------------------------------------------------------------------------------
|
2173 |
|
|
|
2174 |
|
|
LDQ_HOLD_CHECK : process (DQ(7 downto 0))
|
2175 |
|
|
begin
|
2176 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then
|
2177 |
|
|
assert ((now - ldqs_last_rising) >= tDH (Part_Number)) report
|
2178 |
|
|
"ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data."
|
2179 |
|
|
severity error;
|
2180 |
|
|
assert ((now - udqs_last_falling) >= tDH (Part_Number)) report
|
2181 |
|
|
"ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data."
|
2182 |
|
|
severity error;
|
2183 |
|
|
end if;
|
2184 |
|
|
end process;
|
2185 |
|
|
-----------------------------------------------------------------------------------------------------
|
2186 |
|
|
|
2187 |
|
|
CMD_HOLD_CHECK : process (CSB, WEB, RASB, CASB)
|
2188 |
|
|
begin
|
2189 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2190 |
|
|
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
|
2191 |
|
|
"ERROR : (SETUP_HOLD) : Command hold time violation."
|
2192 |
|
|
severity error;
|
2193 |
|
|
end if;
|
2194 |
|
|
end process;
|
2195 |
|
|
|
2196 |
|
|
-----------------------------------------------------------------------------------------------------
|
2197 |
|
|
|
2198 |
|
|
CKE_HOLD_CHECK : process (CKE)
|
2199 |
|
|
begin
|
2200 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2201 |
|
|
assert ((now - clk_last_rising) >= tIH (Part_Number)) report
|
2202 |
|
|
"ERROR : (SETUP_HOLD) : Clock enable hold time violation."
|
2203 |
|
|
severity error;
|
2204 |
|
|
end if;
|
2205 |
|
|
end process;
|
2206 |
|
|
|
2207 |
|
|
-----------------------------------------------------------------------------------------------------
|
2208 |
|
|
|
2209 |
|
|
tRC_CHECK : process (BankActivateFlag)
|
2210 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
2211 |
|
|
begin
|
2212 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2213 |
|
|
BkAdd := (BA);
|
2214 |
|
|
if (BkAdd = "00" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
|
2215 |
|
|
assert ((now - b0_last_activate) >= tRC) report
|
2216 |
|
|
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
|
2217 |
|
|
severity error;
|
2218 |
|
|
elsif (BkAdd = "01" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
|
2219 |
|
|
assert ((now - b1_last_activate) >= tRC) report
|
2220 |
|
|
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
|
2221 |
|
|
severity error;
|
2222 |
|
|
elsif (BkAdd = "10" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
|
2223 |
|
|
assert ((now - b2_last_activate) >= tRC) report
|
2224 |
|
|
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
|
2225 |
|
|
severity error;
|
2226 |
|
|
elsif (BkAdd = "11" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then
|
2227 |
|
|
assert ((now - b3_last_activate) >= tRC) report
|
2228 |
|
|
"ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation."
|
2229 |
|
|
severity error;
|
2230 |
|
|
end if;
|
2231 |
|
|
end if;
|
2232 |
|
|
end process;
|
2233 |
|
|
|
2234 |
|
|
-----------------------------------------------------------------------------------------------------
|
2235 |
|
|
|
2236 |
|
|
tRCD_CHECK : process (casp6_rd, casp6_wt)
|
2237 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
2238 |
|
|
begin
|
2239 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2240 |
|
|
BkAdd := (BA);
|
2241 |
|
|
if (BkAdd = "00" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
|
2242 |
|
|
assert ((now - b0_last_activate - 1.5 ns) >= tRCD) report
|
2243 |
|
|
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
|
2244 |
|
|
severity error;
|
2245 |
|
|
b0_last_column_access <= transport now after 1 ns;
|
2246 |
|
|
elsif (BkAdd = "01" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
|
2247 |
|
|
assert ((now - b1_last_activate - 1.5 ns) >= tRCD) report
|
2248 |
|
|
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
|
2249 |
|
|
severity error;
|
2250 |
|
|
b1_last_column_access <= transport now after 1 ns;
|
2251 |
|
|
elsif (BkAdd = "10" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
|
2252 |
|
|
assert ((now - b2_last_activate - 1.5 ns) >= tRCD) report
|
2253 |
|
|
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
|
2254 |
|
|
severity error;
|
2255 |
|
|
b2_last_column_access <= transport now after 1 ns;
|
2256 |
|
|
elsif (BkAdd = "11" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then
|
2257 |
|
|
assert ((now - b3_last_activate - 1.5 ns) >= tRCD) report
|
2258 |
|
|
"ERROR : (tRCD_CHECK) : Active to column Access delay time violation."
|
2259 |
|
|
severity error;
|
2260 |
|
|
b3_last_column_access <= transport now after 1 ns;
|
2261 |
|
|
end if;
|
2262 |
|
|
end if;
|
2263 |
|
|
end process;
|
2264 |
|
|
|
2265 |
|
|
-----------------------------------------------------------------------------------------------------
|
2266 |
|
|
|
2267 |
|
|
tRAS_CHECK : process (BankActivatedFlag(0), BankActivatedFlag(1), BankActivatedFlag(2), BankActivatedFlag(3))
|
2268 |
|
|
begin
|
2269 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2270 |
|
|
if (BankActivatedFlag(0)'EVENT and BankActivatedFlag(0) = '0' and BankActivatedFlag(0)'LAST_VALUE = '1') then
|
2271 |
|
|
assert ((now - b0_last_activate) >= tRAS) report
|
2272 |
|
|
"ERROR : (tRAS_CHECK) : Bank0 active time minimum violation."
|
2273 |
|
|
severity error;
|
2274 |
|
|
assert ((now - b0_last_activate) <= tRASmax (Part_Number)) report
|
2275 |
|
|
"ERROR : (tRAS_CHECK) : Bank0 active time maximum violation."
|
2276 |
|
|
severity error;
|
2277 |
|
|
end if;
|
2278 |
|
|
if (BankActivatedFlag(1)'EVENT and BankActivatedFlag(1) = '0' and BankActivatedFlag(1)'LAST_VALUE = '1') then
|
2279 |
|
|
assert ((now - b1_last_activate) >= tRAS) report
|
2280 |
|
|
"ERROR : (tRAS_CHECK) : Bank1 active time minimum violation."
|
2281 |
|
|
severity error;
|
2282 |
|
|
assert ((now - b1_last_activate) <= tRASmax (Part_Number)) report
|
2283 |
|
|
"ERROR : (tRAS_CHECK) : Bank1 active time maximum violation."
|
2284 |
|
|
severity error;
|
2285 |
|
|
end if;
|
2286 |
|
|
if (BankActivatedFlag(2)'EVENT and BankActivatedFlag(2) = '0' and BankActivatedFlag(2)'LAST_VALUE = '1') then
|
2287 |
|
|
assert ((now - b2_last_activate) >= tRAS) report
|
2288 |
|
|
"ERROR : (tRAS_CHECK) : Bank2 active time minimum violation."
|
2289 |
|
|
severity error;
|
2290 |
|
|
assert ((now - b2_last_activate) <= tRASmax (Part_Number)) report
|
2291 |
|
|
"ERROR : (tRAS_CHECK) : Bank2 active time maximum violation."
|
2292 |
|
|
severity error;
|
2293 |
|
|
end if;
|
2294 |
|
|
if (BankActivatedFlag(3)'EVENT and BankActivatedFlag(3) = '0' and BankActivatedFlag(3)'LAST_VALUE = '1') then
|
2295 |
|
|
assert ((now - b3_last_activate) >= tRAS) report
|
2296 |
|
|
"ERROR : (tRAS_CHECK) : Bank3 active time minimum violation."
|
2297 |
|
|
severity error;
|
2298 |
|
|
assert ((now - b3_last_activate) <= tRASmax (Part_Number)) report
|
2299 |
|
|
"ERROR : (tRAS_CHECK) : Bank3 active time maximum violation."
|
2300 |
|
|
severity error;
|
2301 |
|
|
end if;
|
2302 |
|
|
end if;
|
2303 |
|
|
end process;
|
2304 |
|
|
|
2305 |
|
|
-----------------------------------------------------------------------------------------------------
|
2306 |
|
|
|
2307 |
|
|
tRP_CHECK : process (BankActivateFlag)
|
2308 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
2309 |
|
|
begin
|
2310 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2311 |
|
|
BkAdd := (BA);
|
2312 |
|
|
if (BkAdd = "00" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
|
2313 |
|
|
assert ((now - b0_last_precharge) >= tRP) report
|
2314 |
|
|
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
|
2315 |
|
|
severity error;
|
2316 |
|
|
elsif (BkAdd = "01" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
|
2317 |
|
|
assert ((now - b1_last_precharge) >= tRP) report
|
2318 |
|
|
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
|
2319 |
|
|
severity error;
|
2320 |
|
|
elsif (BkAdd = "10" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
|
2321 |
|
|
assert ((now - b2_last_precharge) >= tRP) report
|
2322 |
|
|
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
|
2323 |
|
|
severity error;
|
2324 |
|
|
elsif (BkAdd = "11" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then
|
2325 |
|
|
assert ((now - b3_last_precharge) >= tRP) report
|
2326 |
|
|
"ERROR : (tRP_CHECK) : Precharge to active delay time violation."
|
2327 |
|
|
severity error;
|
2328 |
|
|
end if;
|
2329 |
|
|
end if;
|
2330 |
|
|
end process;
|
2331 |
|
|
|
2332 |
|
|
-----------------------------------------------------------------------------------------------------
|
2333 |
|
|
|
2334 |
|
|
tRRD_CHECK : process (BankActivateFlag)
|
2335 |
|
|
begin
|
2336 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2337 |
|
|
if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then
|
2338 |
|
|
assert ((now - b0_last_activate) >= tRRD) report
|
2339 |
|
|
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
|
2340 |
|
|
severity error;
|
2341 |
|
|
assert ((now - b1_last_activate) >= tRRD) report
|
2342 |
|
|
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
|
2343 |
|
|
severity error;
|
2344 |
|
|
assert ((now - b2_last_activate) >= tRRD) report
|
2345 |
|
|
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
|
2346 |
|
|
severity error;
|
2347 |
|
|
assert ((now - b3_last_activate) >= tRRD) report
|
2348 |
|
|
"ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation."
|
2349 |
|
|
severity error;
|
2350 |
|
|
end if;
|
2351 |
|
|
end if;
|
2352 |
|
|
end process;
|
2353 |
|
|
|
2354 |
|
|
-----------------------------------------------------------------------------------------------------
|
2355 |
|
|
|
2356 |
|
|
tCCD_CHECK : process (casp6_rd, casp6_wt)
|
2357 |
|
|
begin
|
2358 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2359 |
|
|
if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1')) then
|
2360 |
|
|
assert ((now - b0_last_column_access) >= tCCD) report
|
2361 |
|
|
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
|
2362 |
|
|
severity error;
|
2363 |
|
|
assert ((now - b1_last_column_access) >= tCCD) report
|
2364 |
|
|
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
|
2365 |
|
|
severity error;
|
2366 |
|
|
assert ((now - b2_last_column_access) >= tCCD) report
|
2367 |
|
|
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
|
2368 |
|
|
severity error;
|
2369 |
|
|
assert ((now - b3_last_column_access) >= tCCD) report
|
2370 |
|
|
"ERROR : (tCCD_CHECK) : Column access to column access delay time violation."
|
2371 |
|
|
severity error;
|
2372 |
|
|
end if;
|
2373 |
|
|
end if;
|
2374 |
|
|
end process;
|
2375 |
|
|
|
2376 |
|
|
-----------------------------------------------------------------------------------------------------
|
2377 |
|
|
|
2378 |
|
|
tWR_CHECK : process (PrechargeFlag, PrechargeAllFlag)
|
2379 |
|
|
variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X');
|
2380 |
|
|
begin
|
2381 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2382 |
|
|
BkAdd := (BA);
|
2383 |
|
|
if (BkAdd = "00" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
|
2384 |
|
|
assert ((now - b0_last_data_in) >= tWR(Part_Number)) report
|
2385 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2386 |
|
|
severity error;
|
2387 |
|
|
elsif (BkAdd = "01" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
|
2388 |
|
|
assert ((now - b1_last_data_in) >= tWR(Part_Number)) report
|
2389 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2390 |
|
|
severity error;
|
2391 |
|
|
elsif (BkAdd = "10" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
|
2392 |
|
|
assert ((now - b2_last_data_in) >= tWR(Part_Number)) report
|
2393 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2394 |
|
|
severity error;
|
2395 |
|
|
elsif (BkAdd = "11" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then
|
2396 |
|
|
assert ((now - b3_last_data_in) >= tWR(Part_Number)) report
|
2397 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2398 |
|
|
severity error;
|
2399 |
|
|
elsif (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then
|
2400 |
|
|
assert ((now - b0_last_data_in) >= tWR(Part_Number)) report
|
2401 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2402 |
|
|
severity error;
|
2403 |
|
|
assert ((now - b1_last_data_in) >= tWR(Part_Number)) report
|
2404 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2405 |
|
|
severity error;
|
2406 |
|
|
assert ((now - b2_last_data_in) >= tWR(Part_Number)) report
|
2407 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2408 |
|
|
severity error;
|
2409 |
|
|
assert ((now - b3_last_data_in) >= tWR(Part_Number)) report
|
2410 |
|
|
"ERROR : (tWR_CHECK) : Last data in to precharge command delay violation."
|
2411 |
|
|
severity error;
|
2412 |
|
|
end if;
|
2413 |
|
|
end if;
|
2414 |
|
|
end process;
|
2415 |
|
|
|
2416 |
|
|
-----------------------------------------------------------------------------------------------------
|
2417 |
|
|
|
2418 |
|
|
tWTR_CHECK : process (casp6_rd)
|
2419 |
|
|
begin
|
2420 |
|
|
if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then
|
2421 |
|
|
if (casp6_rd'event and casp6_rd = '1') then
|
2422 |
|
|
assert ((now - b0_last_data_in - 1 ns) >= tWTR) report
|
2423 |
|
|
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
|
2424 |
|
|
severity error;
|
2425 |
|
|
assert ((now - b1_last_data_in - 1 ns) >= tWTR) report
|
2426 |
|
|
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
|
2427 |
|
|
severity error;
|
2428 |
|
|
assert ((now - b2_last_data_in - 1 ns) >= tWTR) report
|
2429 |
|
|
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
|
2430 |
|
|
severity error;
|
2431 |
|
|
assert ((now - b3_last_data_in - 1 ns) >= tWTR) report
|
2432 |
|
|
"ERROR : (tWTR_CHECK) : Last data in to read command delay violation."
|
2433 |
|
|
severity error;
|
2434 |
|
|
end if;
|
2435 |
|
|
end if;
|
2436 |
|
|
end process;
|
2437 |
|
|
|
2438 |
|
|
-----------------------------------------------------------------------------------------------------
|
2439 |
|
|
|
2440 |
|
|
tMRD_CHECK : process (mrs_cmd_in)
|
2441 |
|
|
begin
|
2442 |
|
|
if (mrs_cmd_in'event and mrs_cmd_in = '1') then
|
2443 |
|
|
assert ((now - last_mrs_set) >= tMRD) report
|
2444 |
|
|
"ERROR : (tMRD_CHECK) : MRS to MRS delay violation."
|
2445 |
|
|
severity error;
|
2446 |
|
|
last_mrs_set <= transport now;
|
2447 |
|
|
end if;
|
2448 |
|
|
end process;
|
2449 |
|
|
|
2450 |
|
|
-----------------------------------------------------------------------------------------------------
|
2451 |
|
|
|
2452 |
|
|
OCD_DEFAULT_CHECK : process (ExtModeRegister.OCD_PGM)
|
2453 |
|
|
begin
|
2454 |
|
|
if (TimingCheckFlag = TRUE) then
|
2455 |
|
|
if (ExtModeRegister.OCD_PGM = CAL_DEFAULT and DLL_reset = '1') then
|
2456 |
|
|
assert false report
|
2457 |
|
|
"WARNING : DLL RESET to OCD Default Delay Violation."
|
2458 |
|
|
severity warning;
|
2459 |
|
|
end if;
|
2460 |
|
|
end if;
|
2461 |
|
|
end process;
|
2462 |
|
|
|
2463 |
|
|
-----------------------------------------------------------------------------------------------------
|
2464 |
|
|
|
2465 |
|
|
OCD_ADJUST_CHECK : process (ExtModeRegister.OCD_PGM)
|
2466 |
|
|
begin
|
2467 |
|
|
if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then
|
2468 |
|
|
if (TimingCheckFlag = TRUE) then
|
2469 |
|
|
assert (now - last_ocd_adjust_cmd >= (ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1 +
|
2470 |
|
|
ModeRegister.TWR) * clk_cycle) report
|
2471 |
|
|
"WARNINg : OCD ADJUST to OCD CALIBRATION EXIT Delay Violation."
|
2472 |
|
|
severity warning;
|
2473 |
|
|
end if;
|
2474 |
|
|
elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = ADJUST) then
|
2475 |
|
|
last_ocd_adjust_cmd <= transport now;
|
2476 |
|
|
end if;
|
2477 |
|
|
end process;
|
2478 |
|
|
|
2479 |
|
|
-----------------------------------------------------------------------------------------------------
|
2480 |
|
|
|
2481 |
|
|
End Behavioral_Model_HY5PS121621F;
|
2482 |
|
|
|
2483 |
|
|
-----------------------------------------------------------------------------------------------------
|