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dimamali |
/****************************************************************************************
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*
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* File Name: mobile_ddr.v
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* Version: 3.50
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* Model: BUS Functional
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*
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* Dependencies: mobile_ddr_parameters.vh
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*
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* Description: Micron MOBILE DDR SDRAM
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*
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* Limitation: - Doesn't check for 8K-cycle refresh
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*
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* Note: - Set simulator resolution to "ps" accuracy
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* - Set Debug = 0 to disable $display messages
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* - Model assume Clk and Clk# crossing at both edge
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2004 Micron Technology, Inc. All rights reserved.
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*
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* Rev Author Date Changes
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* --- ------ ---------- ---------------------------------------
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* 1.0 NMB 03/19/02 - Initial Release of Mobile DDR model
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* based off of version 5.0 of DDR model
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* 1.1 ritz 12/03/04 - New feature: 1/8th strength driver in Drive Strength (Ext Mode Reg).
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* Bugfix - ba[0] ba[1] were swapped for determening ext_mode_enable
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* thus ext_mode_reg wasnt being programmed.
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* 1.2 ritz 12/07/04 - Logging transactions in transcript for automated testing
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* 1.3 ritz 01/31/05 - updated to SMG DDR model version 5.2 (dqs edge checking errors fix)
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* 1.4 ritz 02/15/05 - Fixed display.*WRITE to use hex for "data".
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* 1.5 ritz 03/22/05 - Fixed read latency (#0.5 and 2*Read_latency-1) for MMG latency
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* 2.0 bas 07/19/06 - Added PASR support and clk_n checking
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* 3.0 bas 08/07/06 - Added tXP check, tCke check, Power-down/Deep power down enter/exit messages
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FULL_MEM fix
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* 3.11 bas 10/18/06 - Added clk spd chk, added RP support, added T48M part, added SRR functionality, changed tMRD checker to measure in tck pos edge, DPD optimization for FULL_MEM mode
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* 3.12 bas 10/19/06 - Fixed PASR in FULL_MEM mode
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* 3.20 bas 10/23/06 - changed tXP check to tPDX check for T25L, Initial release to web
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* 3.30 bas 01/15/07 - Updated T48M Parameters (updated as of 12/06)
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* 3.35 bas 02/28/07 - Model uses tAC correctly to calculate strobe/data launch
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* 3.36 bas 03/05/07 - fixed error messages for different banks interrupting
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reads/writes w/autoprecharge
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* 3.37 bas 03/21/07 - Added T47M Part to 512Mb parameter file
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* 3.40 bas 06/25/07 - Removed RP options from 1024Mb
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Updated 128Mb, 256Mb, and 512Mb parts to 05/07 datasheet
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Updated 1024Mb part to 02/07
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Added illegal Cas Latency check per speed grade
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* 3.40 jwm 08/02/07 - Support for 512Mb T47M
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****************************************************************************************/
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// DO NOT CHANGE THE TIMESCALE
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// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
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`timescale 1ns / 1ps
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module mobile_ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
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// `include "mobile_ddr_parameters.vh"
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/****************************************************************************************
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2005 Micron Technology, Inc. All rights reserved.
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*
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*
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* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed.
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* Added ROW_BITS & BA_BITS for compatibility w/our system.
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* Removed part size parameter.
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*
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****************************************************************************************/
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// Parameters current with T47M datasheet rev M (07/07)
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// Timing parameters based on Speed Grade
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`define sg5
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// SYMBOL UNITS DESCRIPTION
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// ------ ----- -----------
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`ifdef sg5 // Timing Parameters for -5 (CL = 3)
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parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 40.0; // tRAS ns Active to Precharge command time
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parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time
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parameter tRP = 15.0; // tRP ns Precharge command period
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parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time
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parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
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`else `ifdef sg6 // Timing Parameters for -6 (CL = 3)
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parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 42.0; // tRAS ns Active to Precharge command time
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parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time
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parameter tRP = 18.0; // tRP ns Precharge command period
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parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time
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parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
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`else `define sg75 // Timing Parameters for -75 (CL = 3)
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parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK#
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parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK#
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parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time
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parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time
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parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time
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parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access
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parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK#
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parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK#
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parameter tRAS = 45.0; // tRAS ns Active to Precharge command time
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parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time
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parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time
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parameter tRP = 22.5; // tRP ns Precharge command period
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parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time
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parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
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`endif `endif
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parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK#
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parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time
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parameter tRFC = 97.5; // tRFC ns Refresh to Refresh Command interval time
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parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
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parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
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parameter tWR = 15.0; // tWR ns Write recovery time
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// Size Parameters based on Part Width
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`define x16
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`ifdef x16
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parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Bank bits
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`else `define x32
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`ifdef RP
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parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Bank bits
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`else
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parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used
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parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used
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parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used
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parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used
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parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used
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parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
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parameter BA_BITS = 2; // Bank bits
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`endif
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`endif
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parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
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parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used
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parameter part_size = 512; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
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parameter tCH_MAX = 0.55; // Clk high level width
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parameter tCH_MIN = 0.45; // Clk high level width
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parameter tCL_MAX = 0.55; // Clk low level width
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parameter tCL_MIN = 0.45; // Clk low level width
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parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's)
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parameter CL_MAX = 3.0; // Maximum CAS Latency
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// Port Declarations
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inout [DQ_BITS - 1 : 0] Dq;
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inout [DQS_BITS - 1 : 0] Dqs;
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input [ADDR_BITS - 1 : 0] Addr;
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input [1 : 0] Ba;
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input Clk;
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input Clk_n;
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input Cke;
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input Cs_n;
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input Ras_n;
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input Cas_n;
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input We_n;
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input [DM_BITS - 1 : 0] Dm;
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//time variables
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realtime tXP_chk ;
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reg enter_DPD ;
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reg enter_PD ;
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reg enter_APD ;
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//integer clk checks
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// Internal Wires (fixed width)
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wire [31 : 0] Dq_in;
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wire [3 : 0] Dqs_in;
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wire [3 : 0] Dm_in;
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assign Dq_in [DQ_BITS - 1 : 0] = Dq;
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assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
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assign Dm_in [DM_BITS - 1 : 0] = Dm;
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// Data pair
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reg [31 : 0] dq_rise;
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reg [3 : 0] dm_rise;
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reg [31 : 0] dq_fall;
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reg [3 : 0] dm_fall;
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reg [7 : 0] dm_pair;
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reg [31 : 0] Dq_buf;
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// Power-down cycle counter
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reg [03:00] PD_cntr ;
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// prev cmd value
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reg prev_Cs_n ;
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reg prev_Ras_n ;
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reg prev_Cas_n ;
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reg prev_We_n ;
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reg [01:00] prev_Ba ;
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reg prev_cke ;
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wire prev_nop = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & prev_We_n ;
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wire prev_des = prev_Cs_n ;
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wire prev_bt = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & ~prev_We_n ;
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//differential clk
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reg diff_ck;
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always @(posedge Clk) diff_ck <= Clk;
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always @(posedge Clk_n) diff_ck <= ~Clk_n;
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//measure clock period
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realtime clk_period ;
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realtime pos_clk_edge ;
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integer clk_pos_edge_cnt ;
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always @(posedge diff_ck) begin
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clk_period = $realtime - pos_clk_edge ;
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pos_clk_edge = $realtime ;
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if ((Cke == 1'b1) && (clk_pos_edge_cnt < 2)) begin
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clk_pos_edge_cnt = clk_pos_edge_cnt + 1 ;
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end else if (Cke == 1'b0) begin
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clk_pos_edge_cnt = 2'b00 ;
|
282 |
|
|
end
|
283 |
|
|
end
|
284 |
|
|
|
285 |
|
|
//measure duty cycle
|
286 |
|
|
realtime neg_clk_edge ;
|
287 |
|
|
always @(negedge diff_ck) begin
|
288 |
|
|
neg_clk_edge = $realtime ;
|
289 |
|
|
end
|
290 |
|
|
realtime pos_clk_time ;
|
291 |
|
|
realtime neg_clk_time ;
|
292 |
|
|
always @(diff_ck) begin
|
293 |
|
|
if (diff_ck) begin
|
294 |
|
|
neg_clk_time = $realtime - neg_clk_edge ;
|
295 |
|
|
end
|
296 |
|
|
if (~diff_ck) begin
|
297 |
|
|
pos_clk_time = $realtime - pos_clk_edge ;
|
298 |
|
|
end
|
299 |
|
|
if (Cke) begin
|
300 |
|
|
if ((pos_clk_time/clk_period)<tCH_MIN) begin
|
301 |
|
|
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCH_MIN*clk_period - pos_clk_time);
|
302 |
|
|
end
|
303 |
|
|
if ((pos_clk_time/clk_period)>tCH_MAX) begin
|
304 |
|
|
$display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period);
|
305 |
|
|
end
|
306 |
|
|
if ((neg_clk_time/clk_period)<tCL_MIN) begin
|
307 |
|
|
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCL_MIN*clk_period - pos_clk_time);
|
308 |
|
|
end
|
309 |
|
|
if ((neg_clk_time/clk_period)>tCL_MAX) begin
|
310 |
|
|
$display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period);
|
311 |
|
|
end
|
312 |
|
|
end
|
313 |
|
|
end
|
314 |
|
|
|
315 |
|
|
// Mode Register
|
316 |
|
|
reg [ADDR_BITS - 1 : 0] Mode_reg;
|
317 |
|
|
reg [ADDR_BITS - 1 : 0] Ext_Mode_reg;
|
318 |
|
|
reg [2*DQ_BITS - 1 : 0] Srr_reg;
|
319 |
|
|
|
320 |
|
|
// SRR Registers
|
321 |
|
|
reg SRR_read;
|
322 |
|
|
|
323 |
|
|
// Internal System Clock
|
324 |
|
|
reg CkeZ, Sys_clk;
|
325 |
|
|
|
326 |
|
|
// Internal Dqs initialize
|
327 |
|
|
reg Dqs_int;
|
328 |
|
|
|
329 |
|
|
// Dqs buffer
|
330 |
|
|
reg [DQS_BITS - 1 : 0] Dqs_out;
|
331 |
|
|
reg [DQS_BITS - 1 : 0] Dqs_gen;
|
332 |
|
|
|
333 |
|
|
// Dq buffer
|
334 |
|
|
reg [DQ_BITS - 1 : 0] Dq_out;
|
335 |
|
|
|
336 |
|
|
// Read pipeline variables
|
337 |
|
|
reg Read_cmnd [0 : 6];
|
338 |
|
|
reg [1 : 0] Read_bank [0 : 6];
|
339 |
|
|
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
|
340 |
|
|
|
341 |
|
|
// Write pipeline variables
|
342 |
|
|
reg Write_cmnd [0 : 3];
|
343 |
|
|
reg [1 : 0] Write_bank [0 : 3];
|
344 |
|
|
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
|
345 |
|
|
|
346 |
|
|
// Auto precharge variables
|
347 |
|
|
reg Read_precharge [0 : 3];
|
348 |
|
|
reg Write_precharge [0 : 3];
|
349 |
|
|
integer Count_precharge [0 : 3];
|
350 |
|
|
reg SelfRefresh;
|
351 |
|
|
reg [3:0] Read_precharge_count [3:0] ;
|
352 |
|
|
reg [3:0] Write_precharge_count [3:0];
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
reg wr_ap_display_msg ;
|
356 |
|
|
reg rd_ap_display_msg ;
|
357 |
|
|
|
358 |
|
|
// Manual precharge variables
|
359 |
|
|
reg A10_precharge [0 : 6];
|
360 |
|
|
reg [1 : 0] Bank_precharge [0 : 6];
|
361 |
|
|
reg Cmnd_precharge [0 : 6];
|
362 |
|
|
|
363 |
|
|
// Burst terminate variables
|
364 |
|
|
reg Cmnd_bst [0 : 6];
|
365 |
|
|
|
366 |
|
|
// tMRD counter
|
367 |
|
|
integer MRD_cntr ;
|
368 |
|
|
integer SRR_cntr ;
|
369 |
|
|
integer SRC_cntr ;
|
370 |
|
|
|
371 |
|
|
// Memory Banks
|
372 |
|
|
`ifdef FULL_MEM
|
373 |
|
|
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<full_mem_bits)-1];
|
374 |
|
|
`else
|
375 |
|
|
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<part_mem_bits)-1];
|
376 |
|
|
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
|
377 |
|
|
reg [part_mem_bits : 0] mem_used;
|
378 |
|
|
reg [part_mem_bits : 0] memory_index;
|
379 |
|
|
initial mem_used = 0;
|
380 |
|
|
`endif
|
381 |
|
|
|
382 |
|
|
// Dqs edge checking
|
383 |
|
|
integer i;
|
384 |
|
|
reg [3:0] expect_pos_dqs;
|
385 |
|
|
reg [3:0] expect_neg_dqs;
|
386 |
|
|
|
387 |
|
|
// Burst counter
|
388 |
|
|
reg [COL_BITS - 1 : 0] Burst_counter;
|
389 |
|
|
|
390 |
|
|
// Burst counter delay
|
391 |
|
|
reg [COL_BITS - 1 : 0] Burst_counter_dly;
|
392 |
|
|
always@* begin
|
393 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
394 |
|
|
Burst_counter_dly = #tAC2_max Burst_counter;
|
395 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
396 |
|
|
Burst_counter_dly = #tAC3_max Burst_counter;
|
397 |
|
|
end
|
398 |
|
|
end
|
399 |
|
|
|
400 |
|
|
// Precharge variables
|
401 |
|
|
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
|
402 |
|
|
|
403 |
|
|
// Activate variables
|
404 |
|
|
reg Act_b0, Act_b1, Act_b2, Act_b3;
|
405 |
|
|
|
406 |
|
|
// Data IO variables
|
407 |
|
|
reg Data_in_enable;
|
408 |
|
|
reg Data_out_enable;
|
409 |
|
|
|
410 |
|
|
// Data Out Enable delay
|
411 |
|
|
reg Data_out_enable_dly;
|
412 |
|
|
always@* begin
|
413 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
414 |
|
|
Data_out_enable_dly = #tAC2_max Data_out_enable;
|
415 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
416 |
|
|
Data_out_enable_dly = #tAC3_max Data_out_enable;
|
417 |
|
|
end
|
418 |
|
|
end
|
419 |
|
|
|
420 |
|
|
// Internal address mux variables
|
421 |
|
|
reg [1 : 0] Prev_bank;
|
422 |
|
|
reg [1 : 0] Bank_addr;
|
423 |
|
|
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
|
424 |
|
|
reg [ADDR_BITS - 1 : 0] Rows_addr;
|
425 |
|
|
reg [ADDR_BITS - 1 : 0] B0_row_addr;
|
426 |
|
|
reg [ADDR_BITS - 1 : 0] B1_row_addr;
|
427 |
|
|
reg [ADDR_BITS - 1 : 0] B2_row_addr;
|
428 |
|
|
reg [ADDR_BITS - 1 : 0] B3_row_addr;
|
429 |
|
|
|
430 |
|
|
integer aref_count;
|
431 |
|
|
reg ext_mode_load_done;
|
432 |
|
|
reg mode_load_done;
|
433 |
|
|
reg power_up_done;
|
434 |
|
|
|
435 |
|
|
// Write DQS for tDSS , tDSH, tDQSH, tDQSL checks
|
436 |
|
|
wire wdqs_valid = Write_cmnd[1] || Write_cmnd[2] || Data_in_enable;
|
437 |
|
|
|
438 |
|
|
// Commands Decode
|
439 |
|
|
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
|
440 |
|
|
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & Cke;
|
441 |
|
|
wire Sref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & ~Cke;
|
442 |
|
|
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
|
443 |
|
|
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[1] & ~Ba[0];
|
444 |
|
|
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & ~Ba[0];
|
445 |
|
|
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
|
446 |
|
|
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
|
447 |
|
|
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
|
448 |
|
|
wire DPD_enable = ~Cs_n & Ras_n & Cas_n & ~We_n & ~Cke;
|
449 |
|
|
wire PD_enable = ((~Cs_n & Ras_n & Cas_n & We_n) | Cs_n) & ~Cke;
|
450 |
|
|
wire nop_enable = ~Cs_n & Ras_n & Cas_n & We_n ;
|
451 |
|
|
wire des_enable = Cs_n ;
|
452 |
|
|
wire srr_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & Ba[0] ; //& (part_size==1024) ; // ****
|
453 |
|
|
|
454 |
|
|
// Burst Length Decode
|
455 |
|
|
// reg [4:0] burst_length = 1 << (Mode_reg[2:0]);
|
456 |
|
|
reg [4:0] burst_length ;
|
457 |
|
|
reg read_precharge_truncation;
|
458 |
|
|
|
459 |
|
|
// CAS Latency Decode
|
460 |
|
|
wire [2:0] cas_latency_x2 = ((2*Mode_reg[6:4])-1);
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
|
464 |
|
|
// DQS Buffer
|
465 |
|
|
reg [DQS_BITS - 1 : 0] dqs_delayed ;
|
466 |
|
|
// always@* begin
|
467 |
|
|
// dqs_delayed <= Dqs_out ;
|
468 |
|
|
// end
|
469 |
|
|
|
470 |
|
|
assign Dqs = Dqs_out;
|
471 |
|
|
|
472 |
|
|
// DQ Buffer
|
473 |
|
|
reg [DQ_BITS - 1 : 0] dq_delayed ;
|
474 |
|
|
always@* begin
|
475 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
476 |
|
|
dq_delayed <= #tAC2_max Dq_out ;
|
477 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
478 |
|
|
dq_delayed <= #tAC3_max Dq_out ;
|
479 |
|
|
end else begin
|
480 |
|
|
dq_delayed <= #tAC3_max {DQ_BITS{1'bz}} ;
|
481 |
|
|
end
|
482 |
|
|
end
|
483 |
|
|
assign Dq = dq_delayed;
|
484 |
|
|
|
485 |
|
|
// Debug message
|
486 |
|
|
wire Debug = 1'b0;
|
487 |
|
|
|
488 |
|
|
// Timing Check
|
489 |
|
|
// realtime MRD_chk;
|
490 |
|
|
realtime RFC_chk;
|
491 |
|
|
realtime RRD_chk;
|
492 |
|
|
realtime RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
|
493 |
|
|
realtime RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
|
494 |
|
|
realtime RC_chk0, RC_chk1, RC_chk2, RC_chk3;
|
495 |
|
|
realtime RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
|
496 |
|
|
realtime RP_chk0, RP_chk1, RP_chk2, RP_chk3;
|
497 |
|
|
realtime WR_chk0, WR_chk1, WR_chk2, WR_chk3;
|
498 |
|
|
realtime SRR_chk;
|
499 |
|
|
|
500 |
|
|
//
|
501 |
|
|
reg [2:0] current_init_state ;
|
502 |
|
|
parameter [2:0] begin_init = 3'b000 ;
|
503 |
|
|
parameter [2:0] cke_init = 3'b001 ;
|
504 |
|
|
parameter [2:0] prech_init = 3'b010 ;
|
505 |
|
|
parameter [2:0] begin_mode_init = 3'b011 ;
|
506 |
|
|
parameter [2:0] mode_init = 3'b100 ;
|
507 |
|
|
parameter [2:0] ext_mode_init = 3'b101 ;
|
508 |
|
|
parameter [2:0] mode_done_init = 3'b110 ;
|
509 |
|
|
|
510 |
|
|
initial begin
|
511 |
|
|
CkeZ = 1'b0;
|
512 |
|
|
Sys_clk = 1'b0;
|
513 |
|
|
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
|
514 |
|
|
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
|
515 |
|
|
Dqs_int = 1'b0;
|
516 |
|
|
Dqs_out = {DQS_BITS{1'bz}};
|
517 |
|
|
Dqs_gen = {DQS_BITS{1'bz}};
|
518 |
|
|
Dq_out = {DQ_BITS{1'bz}};
|
519 |
|
|
Data_in_enable = 1'b0;
|
520 |
|
|
Data_out_enable = 1'b0;
|
521 |
|
|
aref_count = 0;
|
522 |
|
|
SelfRefresh = 1'b0;
|
523 |
|
|
power_up_done = 0;
|
524 |
|
|
ext_mode_load_done = 0;
|
525 |
|
|
mode_load_done = 0;
|
526 |
|
|
// MRD_chk = 0;
|
527 |
|
|
RFC_chk = 0;
|
528 |
|
|
RRD_chk = 0;
|
529 |
|
|
RAS_chk0 = 0;
|
530 |
|
|
RAS_chk1 = 0;
|
531 |
|
|
RAS_chk2 = 0;
|
532 |
|
|
RAS_chk3 = 0;
|
533 |
|
|
RAP_chk0 = 0;
|
534 |
|
|
RAP_chk1 = 0;
|
535 |
|
|
RAP_chk2 = 0;
|
536 |
|
|
RAP_chk3 = 0;
|
537 |
|
|
RC_chk0 = 0;
|
538 |
|
|
RC_chk1 = 0;
|
539 |
|
|
RC_chk2 = 0;
|
540 |
|
|
RC_chk3 = 0;
|
541 |
|
|
RCD_chk0 = 0;
|
542 |
|
|
RCD_chk1 = 0;
|
543 |
|
|
RCD_chk2 = 0;
|
544 |
|
|
RCD_chk3 = 0;
|
545 |
|
|
RP_chk0 = 0;
|
546 |
|
|
RP_chk1 = 0;
|
547 |
|
|
RP_chk2 = 0;
|
548 |
|
|
RP_chk3 = 0;
|
549 |
|
|
WR_chk0 = 0;
|
550 |
|
|
WR_chk1 = 0;
|
551 |
|
|
WR_chk2 = 0;
|
552 |
|
|
WR_chk3 = 0;
|
553 |
|
|
SRR_chk = 0;
|
554 |
|
|
$timeformat (-9, 3, " ns", 12);
|
555 |
|
|
pos_clk_time = 0;
|
556 |
|
|
neg_clk_time = 0;
|
557 |
|
|
enter_DPD = 0;
|
558 |
|
|
enter_PD = 0;
|
559 |
|
|
enter_APD = 0;
|
560 |
|
|
current_init_state = begin_init ;
|
561 |
|
|
SRR_read = 1'b0;
|
562 |
|
|
MRD_cntr = 8;
|
563 |
|
|
SRR_cntr = 8;
|
564 |
|
|
SRC_cntr = 8;
|
565 |
|
|
Read_precharge[0] = 1'b0 ;
|
566 |
|
|
Read_precharge[1] = 1'b0 ;
|
567 |
|
|
Read_precharge[2] = 1'b0 ;
|
568 |
|
|
Read_precharge[3] = 1'b0 ;
|
569 |
|
|
Write_precharge[0] = 1'b0 ;
|
570 |
|
|
Write_precharge[1] = 1'b0 ;
|
571 |
|
|
Write_precharge[2] = 1'b0 ;
|
572 |
|
|
Write_precharge[3] = 1'b0 ;
|
573 |
|
|
wr_ap_display_msg = 1'b0 ;
|
574 |
|
|
rd_ap_display_msg = 1'b0 ;
|
575 |
|
|
Read_precharge_count[0] = 4'hf;
|
576 |
|
|
Read_precharge_count[1] = 4'hf;
|
577 |
|
|
Read_precharge_count[2] = 4'hf;
|
578 |
|
|
Read_precharge_count[3] = 4'hf;
|
579 |
|
|
Write_precharge_count[0] = 4'hf;
|
580 |
|
|
Write_precharge_count[1] = 4'hf;
|
581 |
|
|
Write_precharge_count[2] = 4'hf;
|
582 |
|
|
Write_precharge_count[3] = 4'hf;
|
583 |
|
|
end
|
584 |
|
|
|
585 |
|
|
//clock Frequency Check
|
586 |
|
|
always @(posedge diff_ck) begin
|
587 |
|
|
if (clk_pos_edge_cnt > 1) begin
|
588 |
|
|
if (Mode_reg[6:4] == 3'b011) begin
|
589 |
|
|
if (clk_period < (tCK3_min-0.001)) begin
|
590 |
|
|
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime);
|
591 |
|
|
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
|
592 |
|
|
end
|
593 |
|
|
end
|
594 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
595 |
|
|
if (clk_period < (tCK2_min-0.001)) begin
|
596 |
|
|
$display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime);
|
597 |
|
|
$display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
|
598 |
|
|
end
|
599 |
|
|
end
|
600 |
|
|
end
|
601 |
|
|
end
|
602 |
|
|
|
603 |
|
|
//SRR reg settings
|
604 |
|
|
always @(posedge power_up_done) begin
|
605 |
|
|
Srr_reg = 'b0 ;
|
606 |
|
|
Srr_reg[3:0] = 4'b1111 ; //Manufacturer(Micron)
|
607 |
|
|
Srr_reg[7:4] = 4'b0000 ; //Revision ID(Default to 0 in model)
|
608 |
|
|
Srr_reg[10:8] = 3'b100 ; //Refresh Rate(based on temp sensor - will default to 1x in model)
|
609 |
|
|
Srr_reg[11] = (DQ_BITS == 32)? 1'b1 : 1'b0 ; //Part width(x32 or x16)
|
610 |
|
|
Srr_reg[12] = 1'b0 ; //Device Type (LP DDR)
|
611 |
|
|
Srr_reg[15:13] = (part_size == 1024)? 3'b011 :
|
612 |
|
|
(part_size == 512 )? 3'b010 :
|
613 |
|
|
(part_size == 256 )? 3'b001 :
|
614 |
|
|
3'b000 ; //Density(1024Mb, 512Mb, 256Mb, 128Mb)
|
615 |
|
|
end
|
616 |
|
|
|
617 |
|
|
// System Clock
|
618 |
|
|
always begin
|
619 |
|
|
@ (posedge diff_ck) begin
|
620 |
|
|
Sys_clk = CkeZ;
|
621 |
|
|
CkeZ = Cke;
|
622 |
|
|
end
|
623 |
|
|
@ (negedge diff_ck) begin
|
624 |
|
|
Sys_clk = 1'b0;
|
625 |
|
|
end
|
626 |
|
|
end
|
627 |
|
|
|
628 |
|
|
task store_prev_cmd;
|
629 |
|
|
begin
|
630 |
|
|
prev_Cs_n <= Cs_n ;
|
631 |
|
|
prev_Ras_n <= Ras_n ;
|
632 |
|
|
prev_Cas_n <= Cas_n ;
|
633 |
|
|
prev_We_n <= We_n ;
|
634 |
|
|
prev_Ba[1] <= Ba[1] ;
|
635 |
|
|
prev_Ba[0] <= Ba[0] ;
|
636 |
|
|
prev_cke <= Cke ;
|
637 |
|
|
end
|
638 |
|
|
endtask
|
639 |
|
|
|
640 |
|
|
task MRD_counter;
|
641 |
|
|
begin
|
642 |
|
|
if (Cke) begin
|
643 |
|
|
if (MRD_cntr < tMRD) begin
|
644 |
|
|
MRD_cntr = MRD_cntr + 1'b1;
|
645 |
|
|
end
|
646 |
|
|
end
|
647 |
|
|
end
|
648 |
|
|
endtask
|
649 |
|
|
|
650 |
|
|
task SRR_counter;
|
651 |
|
|
begin
|
652 |
|
|
if (Cke) begin
|
653 |
|
|
if (SRR_cntr < tSRR) begin
|
654 |
|
|
SRR_cntr = SRR_cntr + 1'b1;
|
655 |
|
|
end
|
656 |
|
|
end
|
657 |
|
|
end
|
658 |
|
|
endtask
|
659 |
|
|
|
660 |
|
|
task SRC_counter;
|
661 |
|
|
begin
|
662 |
|
|
if (Cke) begin
|
663 |
|
|
if (SRC_cntr < ((Mode_reg[6:4])+1)) begin
|
664 |
|
|
SRC_cntr = SRC_cntr + 1'b1;
|
665 |
|
|
end
|
666 |
|
|
end
|
667 |
|
|
end
|
668 |
|
|
endtask
|
669 |
|
|
|
670 |
|
|
task command_counter;
|
671 |
|
|
begin
|
672 |
|
|
if (Cke) begin
|
673 |
|
|
for (i=0; i<4;i=i+1) begin
|
674 |
|
|
if (Read_precharge_count[i] < 4'hf) begin
|
675 |
|
|
Read_precharge_count[i] = Read_precharge_count[i] + 1'b1;
|
676 |
|
|
end
|
677 |
|
|
end
|
678 |
|
|
for (i=0; i<4;i=i+1) begin
|
679 |
|
|
if (Write_precharge_count[i] < 4'hf) begin
|
680 |
|
|
Write_precharge_count[i] = Write_precharge_count[i] + 1'b1;
|
681 |
|
|
end
|
682 |
|
|
end
|
683 |
|
|
end
|
684 |
|
|
end
|
685 |
|
|
endtask
|
686 |
|
|
|
687 |
|
|
|
688 |
|
|
task PD_counter;
|
689 |
|
|
begin
|
690 |
|
|
if (~Cke) begin
|
691 |
|
|
if (PD_cntr < tCKE) begin
|
692 |
|
|
PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable);
|
693 |
|
|
end
|
694 |
|
|
end else begin
|
695 |
|
|
PD_cntr = 4'h0 ;
|
696 |
|
|
end
|
697 |
|
|
end
|
698 |
|
|
endtask
|
699 |
|
|
|
700 |
|
|
task tXP_check;
|
701 |
|
|
begin
|
702 |
|
|
if (Cke == 1'b1 && prev_cke == 1'b0) begin
|
703 |
|
|
tXP_chk = $realtime ;
|
704 |
|
|
end
|
705 |
|
|
if (Cke) begin
|
706 |
|
|
if (~nop_enable && ~des_enable) begin
|
707 |
|
|
if ($realtime-tXP_chk < tXP) begin
|
708 |
|
|
`ifdef T25L
|
709 |
|
|
$display ("%m: At time %t ERROR: tPDX violation", $realtime);
|
710 |
|
|
`else
|
711 |
|
|
$display ("%m: At time %t ERROR: tXP violation", $realtime);
|
712 |
|
|
`endif
|
713 |
|
|
end
|
714 |
|
|
end
|
715 |
|
|
end
|
716 |
|
|
end
|
717 |
|
|
endtask
|
718 |
|
|
|
719 |
|
|
// DPD pos edge clk cntr
|
720 |
|
|
always begin
|
721 |
|
|
@ (posedge diff_ck) begin
|
722 |
|
|
tXP_check ;
|
723 |
|
|
Power_down_chk ;
|
724 |
|
|
PD_counter ;
|
725 |
|
|
store_prev_cmd ;
|
726 |
|
|
end
|
727 |
|
|
end
|
728 |
|
|
|
729 |
|
|
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
|
730 |
|
|
always @(Cke) begin
|
731 |
|
|
if (Cke === 1'b1) begin
|
732 |
|
|
if (SelfRefresh === 1'b1) begin
|
733 |
|
|
SelfRefresh = 1'b0;
|
734 |
|
|
end
|
735 |
|
|
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
|
736 |
|
|
$display ("%m: At time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $realtime);
|
737 |
|
|
$display ("%m: when the Clock Enable is brought High.");
|
738 |
|
|
end
|
739 |
|
|
end
|
740 |
|
|
end
|
741 |
|
|
|
742 |
|
|
//BL Mode Reg settings
|
743 |
|
|
always@(Mode_reg[2:0] or mode_load_done) begin
|
744 |
|
|
if (mode_load_done) begin
|
745 |
|
|
case (Mode_reg[2:0])
|
746 |
|
|
3'b001 : burst_length = 5'b00010;
|
747 |
|
|
3'b010 : burst_length = 5'b00100;
|
748 |
|
|
3'b011 : burst_length = 5'b01000;
|
749 |
|
|
default : burst_length = 5'bxxxxx;
|
750 |
|
|
endcase
|
751 |
|
|
end
|
752 |
|
|
end
|
753 |
|
|
|
754 |
|
|
// Init sequence
|
755 |
|
|
always @* begin
|
756 |
|
|
if (current_init_state == begin_init) begin
|
757 |
|
|
if (Cke) begin
|
758 |
|
|
current_init_state = cke_init ;
|
759 |
|
|
power_up_done = 1'b0 ;
|
760 |
|
|
end
|
761 |
|
|
end
|
762 |
|
|
if (current_init_state == cke_init) begin
|
763 |
|
|
if (Prech_enable) begin
|
764 |
|
|
current_init_state = prech_init ;
|
765 |
|
|
aref_count = 0 ;
|
766 |
|
|
end
|
767 |
|
|
end
|
768 |
|
|
if (current_init_state == prech_init) begin
|
769 |
|
|
if (~Prech_enable) begin
|
770 |
|
|
current_init_state = begin_mode_init ;
|
771 |
|
|
end
|
772 |
|
|
end
|
773 |
|
|
if (current_init_state == begin_mode_init) begin
|
774 |
|
|
if (ext_mode_load_done) begin
|
775 |
|
|
current_init_state = ext_mode_init ;
|
776 |
|
|
end
|
777 |
|
|
if (mode_load_done) begin
|
778 |
|
|
current_init_state = mode_init ;
|
779 |
|
|
end
|
780 |
|
|
end
|
781 |
|
|
if (current_init_state == mode_init) begin
|
782 |
|
|
if (ext_mode_load_done) begin
|
783 |
|
|
current_init_state = mode_done_init ;
|
784 |
|
|
end
|
785 |
|
|
end
|
786 |
|
|
if (current_init_state == ext_mode_init) begin
|
787 |
|
|
if (mode_load_done) begin
|
788 |
|
|
current_init_state = mode_done_init ;
|
789 |
|
|
end
|
790 |
|
|
end
|
791 |
|
|
if (current_init_state == mode_done_init && aref_count >= 2) begin
|
792 |
|
|
power_up_done = 1'b1;
|
793 |
|
|
end
|
794 |
|
|
end
|
795 |
|
|
|
796 |
|
|
|
797 |
|
|
// this task will erase the contents of 0 or more banks
|
798 |
|
|
task erase_mem;
|
799 |
|
|
input [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB
|
800 |
|
|
input DPD_mode ; //erase all memory locations
|
801 |
|
|
integer i;
|
802 |
|
|
begin
|
803 |
|
|
|
804 |
|
|
if (DPD_mode) begin
|
805 |
|
|
`ifdef FULL_MEM
|
806 |
|
|
for (i=0; i<{(BA_BITS+ROW_BITS+COL_BITS){1'b1}}; i=i+1) begin
|
807 |
|
|
mem_array[i] = 'bx;
|
808 |
|
|
end
|
809 |
|
|
`else
|
810 |
|
|
memory_index = 0;
|
811 |
|
|
i = 0;
|
812 |
|
|
// remove the selected banks
|
813 |
|
|
for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
|
814 |
|
|
addr_array[i] = 'bx;
|
815 |
|
|
mem_array[i] = 'bx;
|
816 |
|
|
i = i + 1;
|
817 |
|
|
end
|
818 |
|
|
`endif
|
819 |
|
|
end else begin
|
820 |
|
|
`ifdef FULL_MEM
|
821 |
|
|
for (i={bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}}; i<={1'b0, {(BA_BITS+ROW_BITS+COL_BITS){1'b1}}}; i=i+1) begin
|
822 |
|
|
mem_array[i] = 'bx;
|
823 |
|
|
end
|
824 |
|
|
`else
|
825 |
|
|
memory_index = 0;
|
826 |
|
|
i = 0;
|
827 |
|
|
// remove the selected banks
|
828 |
|
|
for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
|
829 |
|
|
if (addr_array[memory_index]>({bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}})) begin
|
830 |
|
|
addr_array[i] = 'bx;
|
831 |
|
|
mem_array[i] = 'bx;
|
832 |
|
|
i = i + 1;
|
833 |
|
|
end else begin
|
834 |
|
|
i = i + 1;
|
835 |
|
|
end
|
836 |
|
|
end
|
837 |
|
|
`endif
|
838 |
|
|
end
|
839 |
|
|
end
|
840 |
|
|
endtask
|
841 |
|
|
|
842 |
|
|
// Write Memory
|
843 |
|
|
task write_mem;
|
844 |
|
|
input [full_mem_bits - 1 : 0] addr;
|
845 |
|
|
input [DQ_BITS - 1 : 0] data;
|
846 |
|
|
reg [part_mem_bits : 0] i;
|
847 |
|
|
begin
|
848 |
|
|
`ifdef FULL_MEM
|
849 |
|
|
mem_array[addr] = data;
|
850 |
|
|
`else
|
851 |
|
|
begin : loop
|
852 |
|
|
for (i = 0; i < mem_used; i = i + 1) begin
|
853 |
|
|
if (addr_array[i] === addr) begin
|
854 |
|
|
disable loop;
|
855 |
|
|
end
|
856 |
|
|
end
|
857 |
|
|
end
|
858 |
|
|
if (i === mem_used) begin
|
859 |
|
|
if (i === (1<<part_mem_bits)) begin
|
860 |
|
|
$display ("%m: At time %t ERROR: Memory overflow.\n Write to Address %d with Data %d will be lost.\n You must increase the part_mem_bits parameter or `define FULL_MEM.", $realtime, addr, data);
|
861 |
|
|
end else begin
|
862 |
|
|
mem_used = mem_used + 1;
|
863 |
|
|
addr_array[i] = addr;
|
864 |
|
|
end
|
865 |
|
|
end
|
866 |
|
|
mem_array[i] = data;
|
867 |
|
|
`endif
|
868 |
|
|
end
|
869 |
|
|
endtask
|
870 |
|
|
|
871 |
|
|
// Read Memory
|
872 |
|
|
task read_mem;
|
873 |
|
|
input [full_mem_bits - 1 : 0] addr;
|
874 |
|
|
output [DQ_BITS - 1 : 0] data;
|
875 |
|
|
reg [part_mem_bits : 0] i;
|
876 |
|
|
begin
|
877 |
|
|
`ifdef FULL_MEM
|
878 |
|
|
data = mem_array[addr];
|
879 |
|
|
`else
|
880 |
|
|
begin : loop
|
881 |
|
|
for (i = 0; i < mem_used; i = i + 1) begin
|
882 |
|
|
if (addr_array[i] === addr) begin
|
883 |
|
|
disable loop;
|
884 |
|
|
end
|
885 |
|
|
end
|
886 |
|
|
end
|
887 |
|
|
if (i <= mem_used) begin
|
888 |
|
|
data = mem_array[i];
|
889 |
|
|
end else begin
|
890 |
|
|
data = 'bx;
|
891 |
|
|
end
|
892 |
|
|
`endif
|
893 |
|
|
end
|
894 |
|
|
endtask
|
895 |
|
|
|
896 |
|
|
// Burst Decode
|
897 |
|
|
task Burst_Decode;
|
898 |
|
|
begin
|
899 |
|
|
|
900 |
|
|
// Advance Burst Counter
|
901 |
|
|
if (Burst_counter < burst_length) begin
|
902 |
|
|
Burst_counter = Burst_counter + 1;
|
903 |
|
|
end
|
904 |
|
|
|
905 |
|
|
// Burst Type
|
906 |
|
|
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
|
907 |
|
|
Cols_temp = Cols_addr + 1;
|
908 |
|
|
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
|
909 |
|
|
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
|
910 |
|
|
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
|
911 |
|
|
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
|
912 |
|
|
end
|
913 |
|
|
|
914 |
|
|
// Burst Length
|
915 |
|
|
if (burst_length === 2) begin
|
916 |
|
|
Cols_addr [0] = Cols_temp [0];
|
917 |
|
|
end else if (burst_length === 4) begin
|
918 |
|
|
Cols_addr [1 : 0] = Cols_temp [1 : 0];
|
919 |
|
|
end else if (burst_length === 8) begin
|
920 |
|
|
Cols_addr [2 : 0] = Cols_temp [2 : 0];
|
921 |
|
|
end else if (burst_length === 16) begin
|
922 |
|
|
Cols_addr [3 : 0] = Cols_temp [3 : 0];
|
923 |
|
|
end else begin
|
924 |
|
|
Cols_addr = Cols_temp;
|
925 |
|
|
end
|
926 |
|
|
|
927 |
|
|
// Data Counter
|
928 |
|
|
if (Burst_counter >= burst_length) begin
|
929 |
|
|
Data_in_enable = 1'b0;
|
930 |
|
|
Data_out_enable = 1'b0;
|
931 |
|
|
read_precharge_truncation = 1'b0;
|
932 |
|
|
//if (SRC_cntr == 2) begin // ****
|
933 |
|
|
if (((SRC_cntr == 2) & (Mode_reg[6:4] == 3'b010)) | ((SRC_cntr == 3) & (Mode_reg[6:4] == 3'b011))) begin
|
934 |
|
|
SRR_read = 1'b0;
|
935 |
|
|
end
|
936 |
|
|
end
|
937 |
|
|
end
|
938 |
|
|
endtask
|
939 |
|
|
|
940 |
|
|
// // Burst Decode
|
941 |
|
|
// task Burst_Decode;
|
942 |
|
|
// begin
|
943 |
|
|
//
|
944 |
|
|
// // Advance Burst Counter
|
945 |
|
|
// if (Burst_counter < burst_length) begin
|
946 |
|
|
// Burst_counter = Burst_counter + 1;
|
947 |
|
|
// end
|
948 |
|
|
//
|
949 |
|
|
// // Burst Type
|
950 |
|
|
// if (Mode_reg[3] === 1'b0) begin // Sequential Burst
|
951 |
|
|
// Cols_temp = Cols_addr + 1;
|
952 |
|
|
// end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
|
953 |
|
|
// Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
|
954 |
|
|
// Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
|
955 |
|
|
// Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
|
956 |
|
|
// end
|
957 |
|
|
//
|
958 |
|
|
// // Burst Length
|
959 |
|
|
// if (burst_length === 2) begin
|
960 |
|
|
// Cols_addr [0] = Cols_temp [0];
|
961 |
|
|
// end else if (burst_length === 4) begin
|
962 |
|
|
// Cols_addr [1 : 0] = Cols_temp [1 : 0];
|
963 |
|
|
// end else if (burst_length === 8) begin
|
964 |
|
|
// Cols_addr [2 : 0] = Cols_temp [2 : 0];
|
965 |
|
|
// end else if (burst_length === 16) begin
|
966 |
|
|
// Cols_addr [3 : 0] = Cols_temp [3 : 0];
|
967 |
|
|
// end else begin
|
968 |
|
|
// Cols_addr = Cols_temp;
|
969 |
|
|
// end
|
970 |
|
|
//
|
971 |
|
|
// // Data Counter
|
972 |
|
|
// if (Burst_counter >= burst_length) begin
|
973 |
|
|
// Data_in_enable = 1'b0;
|
974 |
|
|
// Data_out_enable = 1'b0;
|
975 |
|
|
// read_precharge_truncation = 1'b0;
|
976 |
|
|
// SRR_read = 1'b0;
|
977 |
|
|
// end
|
978 |
|
|
// end
|
979 |
|
|
// endtask
|
980 |
|
|
|
981 |
|
|
// SRC check
|
982 |
|
|
task Timing_chk_SRC;
|
983 |
|
|
begin
|
984 |
|
|
if (Active_enable || Aref_enable || Sref_enable || Burst_term ||
|
985 |
|
|
Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable ||
|
986 |
|
|
Write_enable || DPD_enable || PD_enable || srr_enable) begin
|
987 |
|
|
if (part_size == 1024) begin
|
988 |
|
|
if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin
|
989 |
|
|
$display ("%m: At time %t ERROR: tSRC Violation", $realtime);
|
990 |
|
|
end
|
991 |
|
|
end
|
992 |
|
|
end
|
993 |
|
|
end
|
994 |
|
|
endtask
|
995 |
|
|
|
996 |
|
|
// Manual Precharge Pipeline
|
997 |
|
|
task Manual_Precharge_Pipeline;
|
998 |
|
|
begin
|
999 |
|
|
// A10 Precharge Pipeline
|
1000 |
|
|
A10_precharge[0] = A10_precharge[1];
|
1001 |
|
|
A10_precharge[1] = A10_precharge[2];
|
1002 |
|
|
A10_precharge[2] = A10_precharge[3];
|
1003 |
|
|
A10_precharge[3] = A10_precharge[4];
|
1004 |
|
|
A10_precharge[4] = A10_precharge[5];
|
1005 |
|
|
A10_precharge[5] = A10_precharge[6];
|
1006 |
|
|
A10_precharge[6] = 1'b0;
|
1007 |
|
|
|
1008 |
|
|
// Bank Precharge Pipeline
|
1009 |
|
|
Bank_precharge[0] = Bank_precharge[1];
|
1010 |
|
|
Bank_precharge[1] = Bank_precharge[2];
|
1011 |
|
|
Bank_precharge[2] = Bank_precharge[3];
|
1012 |
|
|
Bank_precharge[3] = Bank_precharge[4];
|
1013 |
|
|
Bank_precharge[4] = Bank_precharge[5];
|
1014 |
|
|
Bank_precharge[5] = Bank_precharge[6];
|
1015 |
|
|
Bank_precharge[6] = 2'b0;
|
1016 |
|
|
|
1017 |
|
|
// Command Precharge Pipeline
|
1018 |
|
|
Cmnd_precharge[0] = Cmnd_precharge[1];
|
1019 |
|
|
Cmnd_precharge[1] = Cmnd_precharge[2];
|
1020 |
|
|
Cmnd_precharge[2] = Cmnd_precharge[3];
|
1021 |
|
|
Cmnd_precharge[3] = Cmnd_precharge[4];
|
1022 |
|
|
Cmnd_precharge[4] = Cmnd_precharge[5];
|
1023 |
|
|
Cmnd_precharge[5] = Cmnd_precharge[6];
|
1024 |
|
|
Cmnd_precharge[6] = 1'b0;
|
1025 |
|
|
|
1026 |
|
|
// Terminate a Read if same bank or all banks
|
1027 |
|
|
if (Cmnd_precharge[0] === 1'b1) begin
|
1028 |
|
|
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
|
1029 |
|
|
if (Data_out_enable === 1'b1) begin
|
1030 |
|
|
Data_out_enable = 1'b0;
|
1031 |
|
|
read_precharge_truncation = 1'b1;
|
1032 |
|
|
end
|
1033 |
|
|
end
|
1034 |
|
|
end
|
1035 |
|
|
end
|
1036 |
|
|
endtask
|
1037 |
|
|
|
1038 |
|
|
// Burst Terminate Pipeline
|
1039 |
|
|
task Burst_Terminate_Pipeline;
|
1040 |
|
|
begin
|
1041 |
|
|
// Command Precharge Pipeline
|
1042 |
|
|
Cmnd_bst[0] = Cmnd_bst[1];
|
1043 |
|
|
Cmnd_bst[1] = Cmnd_bst[2];
|
1044 |
|
|
Cmnd_bst[2] = Cmnd_bst[3];
|
1045 |
|
|
Cmnd_bst[3] = Cmnd_bst[4];
|
1046 |
|
|
Cmnd_bst[4] = Cmnd_bst[5];
|
1047 |
|
|
Cmnd_bst[5] = Cmnd_bst[6];
|
1048 |
|
|
Cmnd_bst[6] = 1'b0;
|
1049 |
|
|
|
1050 |
|
|
// Terminate a Read regardless of banks
|
1051 |
|
|
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
|
1052 |
|
|
Data_out_enable = 1'b0;
|
1053 |
|
|
end
|
1054 |
|
|
end
|
1055 |
|
|
endtask
|
1056 |
|
|
|
1057 |
|
|
// Dq and Dqs Drivers
|
1058 |
|
|
task Dq_Dqs_Drivers;
|
1059 |
|
|
begin
|
1060 |
|
|
// read command pipeline
|
1061 |
|
|
Read_cmnd [0] = Read_cmnd [1];
|
1062 |
|
|
Read_cmnd [1] = Read_cmnd [2];
|
1063 |
|
|
Read_cmnd [2] = Read_cmnd [3];
|
1064 |
|
|
Read_cmnd [3] = Read_cmnd [4];
|
1065 |
|
|
Read_cmnd [4] = Read_cmnd [5];
|
1066 |
|
|
Read_cmnd [5] = Read_cmnd [6];
|
1067 |
|
|
Read_cmnd [6] = 1'b0;
|
1068 |
|
|
|
1069 |
|
|
// read bank pipeline
|
1070 |
|
|
Read_bank [0] = Read_bank [1];
|
1071 |
|
|
Read_bank [1] = Read_bank [2];
|
1072 |
|
|
Read_bank [2] = Read_bank [3];
|
1073 |
|
|
Read_bank [3] = Read_bank [4];
|
1074 |
|
|
Read_bank [4] = Read_bank [5];
|
1075 |
|
|
Read_bank [5] = Read_bank [6];
|
1076 |
|
|
Read_bank [6] = 2'b0;
|
1077 |
|
|
|
1078 |
|
|
// read column pipeline
|
1079 |
|
|
Read_cols [0] = Read_cols [1];
|
1080 |
|
|
Read_cols [1] = Read_cols [2];
|
1081 |
|
|
Read_cols [2] = Read_cols [3];
|
1082 |
|
|
Read_cols [3] = Read_cols [4];
|
1083 |
|
|
Read_cols [4] = Read_cols [5];
|
1084 |
|
|
Read_cols [5] = Read_cols [6];
|
1085 |
|
|
Read_cols [6] = 0;
|
1086 |
|
|
|
1087 |
|
|
// Initialize Read command
|
1088 |
|
|
if (Read_cmnd [1] === 1'b1) begin
|
1089 |
|
|
Data_out_enable = 1'b1;
|
1090 |
|
|
Bank_addr = Read_bank [1];
|
1091 |
|
|
Cols_addr = Read_cols [1];
|
1092 |
|
|
Cols_brst = Cols_addr [2 : 0];
|
1093 |
|
|
if (SRR_read == 1'b1) begin
|
1094 |
|
|
Burst_counter = burst_length - 2;
|
1095 |
|
|
end else begin
|
1096 |
|
|
Burst_counter = 0;
|
1097 |
|
|
end
|
1098 |
|
|
|
1099 |
|
|
// Row Address Mux
|
1100 |
|
|
case (Bank_addr)
|
1101 |
|
|
2'd0 : Rows_addr = B0_row_addr;
|
1102 |
|
|
2'd1 : Rows_addr = B1_row_addr;
|
1103 |
|
|
2'd2 : Rows_addr = B2_row_addr;
|
1104 |
|
|
2'd3 : Rows_addr = B3_row_addr;
|
1105 |
|
|
default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime);
|
1106 |
|
|
endcase
|
1107 |
|
|
end
|
1108 |
|
|
|
1109 |
|
|
// Toggle Dqs during Read command
|
1110 |
|
|
if (Data_out_enable === 1'b1) begin
|
1111 |
|
|
Dqs_int = 1'b0;
|
1112 |
|
|
if (Dqs_gen === {DQS_BITS{1'b0}}) begin
|
1113 |
|
|
Dqs_gen = {DQS_BITS{1'b1}};
|
1114 |
|
|
end else if (Dqs_gen === {DQS_BITS{1'b1}}) begin
|
1115 |
|
|
Dqs_gen = {DQS_BITS{1'b0}};
|
1116 |
|
|
end else if (Dqs_gen === {DQS_BITS{1'b0}}) begin
|
1117 |
|
|
Dqs_gen = {DQS_BITS{1'b0}};
|
1118 |
|
|
end
|
1119 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1120 |
|
|
Dqs_out <= #tAC2_max Dqs_gen;
|
1121 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
1122 |
|
|
Dqs_out <= #tAC3_max Dqs_gen;
|
1123 |
|
|
end
|
1124 |
|
|
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0 && (Dqs_gen !== {DQS_BITS{1'bz}})) begin
|
1125 |
|
|
Dqs_gen = {DQS_BITS{1'bz}} ;
|
1126 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1127 |
|
|
Dqs_out <= #tHZ2_max Dqs_gen;
|
1128 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
1129 |
|
|
Dqs_out <= #tHZ3_max Dqs_gen;
|
1130 |
|
|
end
|
1131 |
|
|
end
|
1132 |
|
|
|
1133 |
|
|
// Initialize dqs for Read command
|
1134 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1135 |
|
|
if ((Read_enable === 1'b1) && (Sys_clk == 1'b1)) begin
|
1136 |
|
|
if (Data_out_enable === 1'b0) begin
|
1137 |
|
|
Dqs_int = 1'b1;
|
1138 |
|
|
Dqs_gen = {DQS_BITS{1'b0}};
|
1139 |
|
|
// Dqs_out <= #2.0 Dqs_gen; // used in place of tLZ for a one clock preamble
|
1140 |
|
|
Dqs_out <= #tAC2_max Dqs_gen; // used in place of tLZ for a one clock preamble // ****
|
1141 |
|
|
end
|
1142 |
|
|
end
|
1143 |
|
|
end else if (Mode_reg[6:4] == 3'b011) begin
|
1144 |
|
|
if (Read_cmnd [3] === 1'b1) begin
|
1145 |
|
|
if (Data_out_enable === 1'b0) begin
|
1146 |
|
|
Dqs_int = 1'b1;
|
1147 |
|
|
Dqs_gen = {DQS_BITS{1'b0}};
|
1148 |
|
|
Dqs_out <= #tAC3_max Dqs_gen; // used in place of tLZ for a one clock preamble
|
1149 |
|
|
end
|
1150 |
|
|
end
|
1151 |
|
|
end
|
1152 |
|
|
|
1153 |
|
|
// Read latch
|
1154 |
|
|
if (Data_out_enable === 1'b1) begin
|
1155 |
|
|
// output data
|
1156 |
|
|
if (SRR_read == 1'b1) begin
|
1157 |
|
|
if (Burst_counter == (burst_length-2)) begin
|
1158 |
|
|
Dq_out <= Srr_reg[DQ_BITS-1:0];
|
1159 |
|
|
end else if (Burst_counter == (burst_length-1)) begin
|
1160 |
|
|
Dq_out <= Srr_reg[2*DQ_BITS-1:DQ_BITS];
|
1161 |
|
|
end
|
1162 |
|
|
end else begin
|
1163 |
|
|
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
|
1164 |
|
|
end
|
1165 |
|
|
if (Debug) begin
|
1166 |
|
|
$display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %d", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out);
|
1167 |
|
|
end
|
1168 |
|
|
|
1169 |
|
|
end else begin
|
1170 |
|
|
Dq_out = {DQ_BITS{1'bz}};
|
1171 |
|
|
end
|
1172 |
|
|
end
|
1173 |
|
|
endtask
|
1174 |
|
|
|
1175 |
|
|
// Write FIFO and DM Mask Logic
|
1176 |
|
|
task Write_FIFO_DM_Mask_Logic;
|
1177 |
|
|
begin
|
1178 |
|
|
// Write command pipeline
|
1179 |
|
|
Write_cmnd [0] = Write_cmnd [1];
|
1180 |
|
|
Write_cmnd [1] = Write_cmnd [2];
|
1181 |
|
|
Write_cmnd [2] = Write_cmnd [3];
|
1182 |
|
|
Write_cmnd [3] = 1'b0;
|
1183 |
|
|
|
1184 |
|
|
// Write command pipeline
|
1185 |
|
|
Write_bank [0] = Write_bank [1];
|
1186 |
|
|
Write_bank [1] = Write_bank [2];
|
1187 |
|
|
Write_bank [2] = Write_bank [3];
|
1188 |
|
|
Write_bank [3] = 2'b0;
|
1189 |
|
|
|
1190 |
|
|
// Write column pipeline
|
1191 |
|
|
Write_cols [0] = Write_cols [1];
|
1192 |
|
|
Write_cols [1] = Write_cols [2];
|
1193 |
|
|
Write_cols [2] = Write_cols [3];
|
1194 |
|
|
Write_cols [3] = {COL_BITS{1'b0}};
|
1195 |
|
|
|
1196 |
|
|
// Initialize Write command
|
1197 |
|
|
if (Write_cmnd [0] === 1'b1) begin
|
1198 |
|
|
Data_in_enable = 1'b1;
|
1199 |
|
|
Bank_addr = Write_bank [0];
|
1200 |
|
|
Cols_addr = Write_cols [0];
|
1201 |
|
|
Cols_brst = Cols_addr [2 : 0];
|
1202 |
|
|
Burst_counter = 0;
|
1203 |
|
|
|
1204 |
|
|
// Row address mux
|
1205 |
|
|
case (Bank_addr)
|
1206 |
|
|
2'd0 : Rows_addr = B0_row_addr;
|
1207 |
|
|
2'd1 : Rows_addr = B1_row_addr;
|
1208 |
|
|
2'd2 : Rows_addr = B2_row_addr;
|
1209 |
|
|
2'd3 : Rows_addr = B3_row_addr;
|
1210 |
|
|
default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime);
|
1211 |
|
|
endcase
|
1212 |
|
|
end
|
1213 |
|
|
|
1214 |
|
|
// Write data
|
1215 |
|
|
if (Data_in_enable === 1'b1) begin
|
1216 |
|
|
|
1217 |
|
|
// Data Buffer
|
1218 |
|
|
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
|
1219 |
|
|
|
1220 |
|
|
// write negedge Dqs on posedge Sys_clk
|
1221 |
|
|
if (Sys_clk) begin
|
1222 |
|
|
if (!dm_fall[0]) begin
|
1223 |
|
|
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
|
1224 |
|
|
end
|
1225 |
|
|
if (!dm_fall[1]) begin
|
1226 |
|
|
Dq_buf [15 : 8] = dq_fall [15 : 8];
|
1227 |
|
|
end
|
1228 |
|
|
if (!dm_fall[2]) begin
|
1229 |
|
|
Dq_buf [23 : 16] = dq_fall [23 : 16];
|
1230 |
|
|
end
|
1231 |
|
|
if (!dm_fall[3]) begin
|
1232 |
|
|
Dq_buf [31 : 24] = dq_fall [31 : 24];
|
1233 |
|
|
end
|
1234 |
|
|
if (~&dm_fall) begin
|
1235 |
|
|
if (Debug) begin
|
1236 |
|
|
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
|
1237 |
|
|
end
|
1238 |
|
|
end
|
1239 |
|
|
// write posedge Dqs on negedge Sys_clk
|
1240 |
|
|
end else begin
|
1241 |
|
|
if (!dm_rise[0]) begin
|
1242 |
|
|
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
|
1243 |
|
|
end
|
1244 |
|
|
if (!dm_rise[1]) begin
|
1245 |
|
|
Dq_buf [15 : 8] = dq_rise [15 : 8];
|
1246 |
|
|
end
|
1247 |
|
|
if (!dm_rise[2]) begin
|
1248 |
|
|
Dq_buf [23 : 16] = dq_rise [23 : 16];
|
1249 |
|
|
end
|
1250 |
|
|
if (!dm_rise[3]) begin
|
1251 |
|
|
Dq_buf [31 : 24] = dq_rise [31 : 24];
|
1252 |
|
|
end
|
1253 |
|
|
if (~&dm_rise) begin
|
1254 |
|
|
if (Debug) begin
|
1255 |
|
|
$display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
|
1256 |
|
|
end
|
1257 |
|
|
end
|
1258 |
|
|
end
|
1259 |
|
|
|
1260 |
|
|
// Write Data
|
1261 |
|
|
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
|
1262 |
|
|
|
1263 |
|
|
// tWR start and tWTR check
|
1264 |
|
|
if (Sys_clk && &dm_pair === 1'b0) begin
|
1265 |
|
|
case (Bank_addr)
|
1266 |
|
|
2'd0 : WR_chk0 = $realtime;
|
1267 |
|
|
2'd1 : WR_chk1 = $realtime;
|
1268 |
|
|
2'd2 : WR_chk2 = $realtime;
|
1269 |
|
|
2'd3 : WR_chk3 = $realtime;
|
1270 |
|
|
default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime);
|
1271 |
|
|
endcase
|
1272 |
|
|
|
1273 |
|
|
// tWTR check
|
1274 |
|
|
if (Read_enable === 1'b1) begin
|
1275 |
|
|
$display ("%m: At time %t ERROR: tWTR violation during Read", $realtime);
|
1276 |
|
|
end
|
1277 |
|
|
end
|
1278 |
|
|
end
|
1279 |
|
|
end
|
1280 |
|
|
endtask
|
1281 |
|
|
|
1282 |
|
|
// Auto Precharge Calculation
|
1283 |
|
|
task Auto_Precharge_Calculation;
|
1284 |
|
|
begin
|
1285 |
|
|
// Precharge counter
|
1286 |
|
|
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
|
1287 |
|
|
Count_precharge [0] = Count_precharge [0] + 1;
|
1288 |
|
|
end
|
1289 |
|
|
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
|
1290 |
|
|
Count_precharge [1] = Count_precharge [1] + 1;
|
1291 |
|
|
end
|
1292 |
|
|
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
|
1293 |
|
|
Count_precharge [2] = Count_precharge [2] + 1;
|
1294 |
|
|
end
|
1295 |
|
|
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
|
1296 |
|
|
Count_precharge [3] = Count_precharge [3] + 1;
|
1297 |
|
|
end
|
1298 |
|
|
|
1299 |
|
|
// Read with AutoPrecharge Calculation
|
1300 |
|
|
// The device start internal precharge when:
|
1301 |
|
|
// 1. Meet tRAS requirement
|
1302 |
|
|
// 2. BL/2 cycles after command
|
1303 |
|
|
if ((Read_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
|
1304 |
|
|
if (Count_precharge[0] >= burst_length/2) begin
|
1305 |
|
|
Pc_b0 = 1'b1;
|
1306 |
|
|
Act_b0 = 1'b0;
|
1307 |
|
|
RP_chk0 = $realtime;
|
1308 |
|
|
Read_precharge[0] = 1'b0;
|
1309 |
|
|
end
|
1310 |
|
|
end
|
1311 |
|
|
if ((Read_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
|
1312 |
|
|
if (Count_precharge[1] >= burst_length/2) begin
|
1313 |
|
|
Pc_b1 = 1'b1;
|
1314 |
|
|
Act_b1 = 1'b0;
|
1315 |
|
|
RP_chk1 = $realtime;
|
1316 |
|
|
Read_precharge[1] = 1'b0;
|
1317 |
|
|
end
|
1318 |
|
|
end
|
1319 |
|
|
if ((Read_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
|
1320 |
|
|
if (Count_precharge[2] >= burst_length/2) begin
|
1321 |
|
|
Pc_b2 = 1'b1;
|
1322 |
|
|
Act_b2 = 1'b0;
|
1323 |
|
|
RP_chk2 = $realtime;
|
1324 |
|
|
Read_precharge[2] = 1'b0;
|
1325 |
|
|
end
|
1326 |
|
|
end
|
1327 |
|
|
if ((Read_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
|
1328 |
|
|
if (Count_precharge[3] >= burst_length/2) begin
|
1329 |
|
|
Pc_b3 = 1'b1;
|
1330 |
|
|
Act_b3 = 1'b0;
|
1331 |
|
|
RP_chk3 = $realtime;
|
1332 |
|
|
Read_precharge[3] = 1'b0;
|
1333 |
|
|
end
|
1334 |
|
|
end
|
1335 |
|
|
|
1336 |
|
|
// Write with AutoPrecharge Calculation
|
1337 |
|
|
// The device start internal precharge when:
|
1338 |
|
|
// 1. Meet tRAS requirement
|
1339 |
|
|
// 2. Two clock after last burst
|
1340 |
|
|
// Since tWR is time base, the model will compensate tRP
|
1341 |
|
|
if ((Write_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin
|
1342 |
|
|
if (Count_precharge[0] >= burst_length/2+3) begin
|
1343 |
|
|
Pc_b0 = 1'b1;
|
1344 |
|
|
Act_b0 = 1'b0;
|
1345 |
|
|
if (Mode_reg[6:4] == 3'b011) begin
|
1346 |
|
|
RP_chk0 = $realtime - ((2 * tCK3_min) - tWR);
|
1347 |
|
|
end
|
1348 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1349 |
|
|
RP_chk0 = $realtime - ((2 * tCK2_min) - tWR);
|
1350 |
|
|
end
|
1351 |
|
|
Write_precharge[0] = 1'b0;
|
1352 |
|
|
end
|
1353 |
|
|
end
|
1354 |
|
|
if ((Write_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin
|
1355 |
|
|
if (Count_precharge[1] >= burst_length/2+3) begin
|
1356 |
|
|
Pc_b1 = 1'b1;
|
1357 |
|
|
Act_b1 = 1'b0;
|
1358 |
|
|
if (Mode_reg[6:4] == 3'b011) begin
|
1359 |
|
|
RP_chk1 = $realtime - ((2 * tCK3_min) - tWR);
|
1360 |
|
|
end
|
1361 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1362 |
|
|
RP_chk1 = $realtime - ((2 * tCK2_min) - tWR);
|
1363 |
|
|
end
|
1364 |
|
|
Write_precharge[1] = 1'b0;
|
1365 |
|
|
end
|
1366 |
|
|
end
|
1367 |
|
|
if ((Write_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin
|
1368 |
|
|
if (Count_precharge[2] >= burst_length/2+3) begin
|
1369 |
|
|
Pc_b2 = 1'b1;
|
1370 |
|
|
Act_b2 = 1'b0;
|
1371 |
|
|
if (Mode_reg[6:4] == 3'b011) begin
|
1372 |
|
|
RP_chk2 = $realtime - ((2 * tCK3_min) - tWR);
|
1373 |
|
|
end
|
1374 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1375 |
|
|
RP_chk2 = $realtime - ((2 * tCK2_min) - tWR);
|
1376 |
|
|
end
|
1377 |
|
|
Write_precharge[2] = 1'b0;
|
1378 |
|
|
end
|
1379 |
|
|
end
|
1380 |
|
|
if ((Write_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin
|
1381 |
|
|
if (Count_precharge[3] >= burst_length/2+3) begin
|
1382 |
|
|
Pc_b3 = 1'b1;
|
1383 |
|
|
Act_b3 = 1'b0;
|
1384 |
|
|
if (Mode_reg[6:4] == 3'b011) begin
|
1385 |
|
|
RP_chk3 = $realtime - ((2 * tCK3_min) - tWR);
|
1386 |
|
|
end
|
1387 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1388 |
|
|
RP_chk3 = $realtime - ((2 * tCK2_min) - tWR);
|
1389 |
|
|
end
|
1390 |
|
|
Write_precharge[3] = 1'b0;
|
1391 |
|
|
end
|
1392 |
|
|
end
|
1393 |
|
|
end
|
1394 |
|
|
endtask
|
1395 |
|
|
|
1396 |
|
|
task Power_down_chk;
|
1397 |
|
|
begin
|
1398 |
|
|
if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin
|
1399 |
|
|
if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
|
1400 |
|
|
erase_mem(4'b0000, 1'b1);
|
1401 |
|
|
current_init_state = begin_init ;
|
1402 |
|
|
ext_mode_load_done = 1'b0 ;
|
1403 |
|
|
mode_load_done = 1'b0 ;
|
1404 |
|
|
enter_DPD = 1'b1;
|
1405 |
|
|
$display ("%m: at time %t Entering Deep Power-Down Mode", $realtime);
|
1406 |
|
|
end
|
1407 |
|
|
end
|
1408 |
|
|
if (enter_DPD == 1'b1) begin
|
1409 |
|
|
if (Cke == 1'b1 && prev_cke == 1'b0) begin
|
1410 |
|
|
if (PD_cntr < tCKE) begin
|
1411 |
|
|
$display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime);
|
1412 |
|
|
end
|
1413 |
|
|
$display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime);
|
1414 |
|
|
enter_DPD = 1'b0;
|
1415 |
|
|
end
|
1416 |
|
|
end
|
1417 |
|
|
if (PD_enable == 1'b1 && enter_PD == 1'b0) begin
|
1418 |
|
|
if (prev_cke) begin
|
1419 |
|
|
if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
|
1420 |
|
|
$display ("%m: at time %t Entering Power-Down Mode", $realtime);
|
1421 |
|
|
enter_PD = 1'b1;
|
1422 |
|
|
end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin
|
1423 |
|
|
$display ("%m: at time %t Entering Active Power-Down Mode", $realtime);
|
1424 |
|
|
enter_APD = 1'b1;
|
1425 |
|
|
end
|
1426 |
|
|
end
|
1427 |
|
|
end
|
1428 |
|
|
if (enter_PD == 1'b1 || enter_APD == 1'b1) begin
|
1429 |
|
|
if (Cke == 1'b1 && prev_cke == 1'b0) begin
|
1430 |
|
|
if (PD_cntr < tCKE) begin
|
1431 |
|
|
if (enter_PD == 1'b1) begin
|
1432 |
|
|
$display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime);
|
1433 |
|
|
end else if (enter_APD == 1'b1) begin
|
1434 |
|
|
$display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime);
|
1435 |
|
|
end
|
1436 |
|
|
end
|
1437 |
|
|
if (enter_PD == 1'b1) begin
|
1438 |
|
|
$display ("%m: at time %t Exiting Power-Down Mode", $realtime);
|
1439 |
|
|
enter_PD = 1'b0 ;
|
1440 |
|
|
end else if (enter_APD == 1'b1) begin
|
1441 |
|
|
$display ("%m: at time %t Exiting Active Power-Down Mode", $realtime);
|
1442 |
|
|
enter_APD = 1'b0 ;
|
1443 |
|
|
end
|
1444 |
|
|
end
|
1445 |
|
|
end
|
1446 |
|
|
|
1447 |
|
|
end
|
1448 |
|
|
endtask
|
1449 |
|
|
|
1450 |
|
|
// Control Logic
|
1451 |
|
|
task Control_Logic;
|
1452 |
|
|
begin
|
1453 |
|
|
|
1454 |
|
|
// Self Refresh
|
1455 |
|
|
if (Sref_enable === 1'b1) begin
|
1456 |
|
|
// Partial Array Self Refresh
|
1457 |
|
|
if (part_size == 128) begin
|
1458 |
|
|
case (Ext_Mode_reg[2:0])
|
1459 |
|
|
3'b000 : ;//keep Bank 0-7
|
1460 |
|
|
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
|
1461 |
|
|
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
|
1462 |
|
|
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1463 |
|
|
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1464 |
|
|
3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1465 |
|
|
3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1466 |
|
|
endcase
|
1467 |
|
|
end else begin
|
1468 |
|
|
case (Ext_Mode_reg[2:0])
|
1469 |
|
|
3'b000 : ;//keep Bank 0-7
|
1470 |
|
|
3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end
|
1471 |
|
|
3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end
|
1472 |
|
|
3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1473 |
|
|
3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end
|
1474 |
|
|
3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end
|
1475 |
|
|
3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end
|
1476 |
|
|
endcase
|
1477 |
|
|
end
|
1478 |
|
|
SelfRefresh = 1'b1;
|
1479 |
|
|
end
|
1480 |
|
|
if (Aref_enable === 1'b1) begin
|
1481 |
|
|
if (Debug) begin
|
1482 |
|
|
$display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime);
|
1483 |
|
|
end
|
1484 |
|
|
// aref_count is to make sure we have met part of the initialization sequence
|
1485 |
|
|
if (~power_up_done) begin
|
1486 |
|
|
aref_count = aref_count + 1;
|
1487 |
|
|
end
|
1488 |
|
|
|
1489 |
|
|
// Auto Refresh to Auto Refresh
|
1490 |
|
|
if ($realtime - RFC_chk < tRFC) begin
|
1491 |
|
|
$display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime);
|
1492 |
|
|
end
|
1493 |
|
|
|
1494 |
|
|
// Precharge to Auto Refresh
|
1495 |
|
|
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
|
1496 |
|
|
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
|
1497 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime);
|
1498 |
|
|
end
|
1499 |
|
|
|
1500 |
|
|
// Precharge to Auto Refresh
|
1501 |
|
|
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
|
1502 |
|
|
$display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime);
|
1503 |
|
|
end
|
1504 |
|
|
|
1505 |
|
|
// Record Current tRFC time
|
1506 |
|
|
RFC_chk = $realtime;
|
1507 |
|
|
end
|
1508 |
|
|
|
1509 |
|
|
// SRR Register
|
1510 |
|
|
if (srr_enable == 1'b1) begin
|
1511 |
|
|
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 &&
|
1512 |
|
|
Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin
|
1513 |
|
|
SRR_read = 1'b1;
|
1514 |
|
|
SRR_chk = $realtime;
|
1515 |
|
|
SRR_cntr = 0;
|
1516 |
|
|
end
|
1517 |
|
|
end
|
1518 |
|
|
|
1519 |
|
|
|
1520 |
|
|
// Extended Mode Register
|
1521 |
|
|
if (Ext_mode_enable == 1'b1) begin
|
1522 |
|
|
if (Debug) begin
|
1523 |
|
|
$display ("Debug: At time %t %m:EMR : Extended Mode Register", $realtime);
|
1524 |
|
|
end
|
1525 |
|
|
|
1526 |
|
|
// Register Mode
|
1527 |
|
|
Ext_Mode_reg = Addr;
|
1528 |
|
|
|
1529 |
|
|
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
|
1530 |
|
|
// ensure that power sequence is met properly
|
1531 |
|
|
if (~power_up_done) begin
|
1532 |
|
|
ext_mode_load_done = 1'b1;
|
1533 |
|
|
end
|
1534 |
|
|
$display ("At time %t %m:ELMR : Extended Load Mode Register", $realtime);
|
1535 |
|
|
if (part_size == 128) begin
|
1536 |
|
|
// Self Refresh Coverage
|
1537 |
|
|
case (Addr[2 : 0])
|
1538 |
|
|
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
|
1539 |
|
|
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
|
1540 |
|
|
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
|
1541 |
|
|
3'b101 : $display ("%m : PASR = Reserved");
|
1542 |
|
|
3'b110 : $display ("%m : PASR = Reserved");
|
1543 |
|
|
default : $display ("%m : PASR = Reserved");
|
1544 |
|
|
endcase
|
1545 |
|
|
end else begin
|
1546 |
|
|
// Self Refresh Coverage
|
1547 |
|
|
case (Addr[2 : 0])
|
1548 |
|
|
3'b000 : $display ("%m : Self Refresh Cov = 4 banks");
|
1549 |
|
|
3'b001 : $display ("%m : Self Refresh Cov = 2 banks");
|
1550 |
|
|
3'b010 : $display ("%m : Self Refresh Cov = 1 bank");
|
1551 |
|
|
3'b101 : $display ("%m : Self Refresh Cov = 1/2 bank");
|
1552 |
|
|
3'b110 : $display ("%m : Self Refresh Cov = 1/4 bank");
|
1553 |
|
|
default : $display ("%m : PASR = Reserved");
|
1554 |
|
|
endcase
|
1555 |
|
|
end
|
1556 |
|
|
// Maximum Case Temp
|
1557 |
|
|
case (Addr[4 : 3])
|
1558 |
|
|
2'b11 : $display ("%m : Maximum Case Temp = 85C");
|
1559 |
|
|
2'b00 : $display ("%m : Maximum Case Temp = 70C");
|
1560 |
|
|
2'b01 : $display ("%m : Maximum Case Temp = 45C");
|
1561 |
|
|
2'b10 : $display ("%m : Maximum Case Temp = 15C");
|
1562 |
|
|
endcase
|
1563 |
|
|
|
1564 |
|
|
// Drive Strength
|
1565 |
|
|
case (Addr[6 : 5])
|
1566 |
|
|
2'b00 : $display ("%m : Drive Strength = Full Strength");
|
1567 |
|
|
2'b01 : $display ("%m : Drive Strength = Half Strength");
|
1568 |
|
|
2'b10 : $display ("%m : Drive Strength = Quarter Strength");
|
1569 |
|
|
2'b11 : $display ("%m : Drive Strength = One Eight Strength");
|
1570 |
|
|
endcase
|
1571 |
|
|
|
1572 |
|
|
end else begin
|
1573 |
|
|
$display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime);
|
1574 |
|
|
end
|
1575 |
|
|
|
1576 |
|
|
// Precharge to EMR
|
1577 |
|
|
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
|
1578 |
|
|
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
|
1579 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime);
|
1580 |
|
|
end
|
1581 |
|
|
|
1582 |
|
|
// LMR/EMR to LMR/EMR
|
1583 |
|
|
// if ($realtime - MRD_chk < tMRD) begin
|
1584 |
|
|
// $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
|
1585 |
|
|
// end
|
1586 |
|
|
|
1587 |
|
|
if (MRD_cntr < tMRD) begin
|
1588 |
|
|
$display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
|
1589 |
|
|
end
|
1590 |
|
|
|
1591 |
|
|
// Record current tMRD time
|
1592 |
|
|
// MRD_chk = $realtime;
|
1593 |
|
|
MRD_cntr = 0;
|
1594 |
|
|
end
|
1595 |
|
|
|
1596 |
|
|
// Load Mode Register
|
1597 |
|
|
if (Mode_reg_enable === 1'b1) begin
|
1598 |
|
|
if (Debug) begin
|
1599 |
|
|
$display ("Debug: At time %t %m:LMR : Load Mode Register", $realtime);
|
1600 |
|
|
end
|
1601 |
|
|
|
1602 |
|
|
// Register Mode
|
1603 |
|
|
Mode_reg = Addr;
|
1604 |
|
|
|
1605 |
|
|
if (Mode_reg[6:4] == 3'b010) begin
|
1606 |
|
|
if (tCK2_min == 0) begin
|
1607 |
|
|
$display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime);
|
1608 |
|
|
end
|
1609 |
|
|
end
|
1610 |
|
|
|
1611 |
|
|
// Precharge to LMR
|
1612 |
|
|
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
|
1613 |
|
|
$display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime);
|
1614 |
|
|
end
|
1615 |
|
|
|
1616 |
|
|
// Precharge to LMR
|
1617 |
|
|
if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) ||
|
1618 |
|
|
($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin
|
1619 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime);
|
1620 |
|
|
end
|
1621 |
|
|
|
1622 |
|
|
// LMR/EMR to LMR/EMR
|
1623 |
|
|
// if ($realtime - MRD_chk < tMRD) begin
|
1624 |
|
|
// $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
|
1625 |
|
|
// end
|
1626 |
|
|
if (MRD_cntr < tMRD) begin
|
1627 |
|
|
$display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
|
1628 |
|
|
end
|
1629 |
|
|
|
1630 |
|
|
if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
|
1631 |
|
|
// ensure that power sequence is met properly
|
1632 |
|
|
if (~power_up_done) begin
|
1633 |
|
|
mode_load_done = 1'b1;
|
1634 |
|
|
end
|
1635 |
|
|
// Burst Length
|
1636 |
|
|
case (Addr [2 : 0])
|
1637 |
|
|
3'b001 : $display ("At time %t %m:LMR : Burst Length = 2", $realtime);
|
1638 |
|
|
3'b010 : $display ("At time %t %m:LMR : Burst Length = 4", $realtime);
|
1639 |
|
|
3'b011 : $display ("At time %t %m:LMR : Burst Length = 8", $realtime);
|
1640 |
|
|
default :
|
1641 |
|
|
begin
|
1642 |
|
|
$display ("%m: At time %t ERROR: Undefined burst length selection", $realtime);
|
1643 |
|
|
$stop;
|
1644 |
|
|
end
|
1645 |
|
|
endcase
|
1646 |
|
|
|
1647 |
|
|
// CAS Latency
|
1648 |
|
|
case (Addr [6 : 4])
|
1649 |
|
|
3'b010 : $display ("At time %t %m:LMR : CAS Latency = 2", $realtime);
|
1650 |
|
|
3'b011 : $display ("At time %t %m:LMR : CAS Latency = 3", $realtime);
|
1651 |
|
|
default : begin
|
1652 |
|
|
$display ("%m: At time %t ERROR: CAS Latency not supported", $realtime);
|
1653 |
|
|
$stop;
|
1654 |
|
|
end
|
1655 |
|
|
endcase
|
1656 |
|
|
|
1657 |
|
|
end
|
1658 |
|
|
// Record current tMRD time
|
1659 |
|
|
// MRD_chk = $realtime;
|
1660 |
|
|
MRD_cntr = 0;
|
1661 |
|
|
end
|
1662 |
|
|
|
1663 |
|
|
// Activate Block
|
1664 |
|
|
if (Active_enable === 1'b1) begin
|
1665 |
|
|
if (!(power_up_done)) begin
|
1666 |
|
|
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime);
|
1667 |
|
|
end
|
1668 |
|
|
// Display Debug Message
|
1669 |
|
|
if (Debug) begin
|
1670 |
|
|
$display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr);
|
1671 |
|
|
end
|
1672 |
|
|
|
1673 |
|
|
// Activating an open bank can cause corruption.
|
1674 |
|
|
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
|
1675 |
|
|
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
|
1676 |
|
|
$display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba);
|
1677 |
|
|
end
|
1678 |
|
|
|
1679 |
|
|
// Activate Bank 0
|
1680 |
|
|
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
|
1681 |
|
|
// Activate to Activate (same bank)
|
1682 |
|
|
if ($realtime - RC_chk0 < tRC) begin
|
1683 |
|
|
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
|
1684 |
|
|
end
|
1685 |
|
|
|
1686 |
|
|
// Precharge to Activate
|
1687 |
|
|
if ($realtime - RP_chk0 < tRP) begin
|
1688 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
|
1689 |
|
|
end
|
1690 |
|
|
|
1691 |
|
|
// Record variables for checking violation
|
1692 |
|
|
Act_b0 = 1'b1;
|
1693 |
|
|
Pc_b0 = 1'b0;
|
1694 |
|
|
B0_row_addr = Addr;
|
1695 |
|
|
RC_chk0 = $realtime;
|
1696 |
|
|
RCD_chk0 = $realtime;
|
1697 |
|
|
RAS_chk0 = $realtime;
|
1698 |
|
|
RAP_chk0 = $realtime;
|
1699 |
|
|
end
|
1700 |
|
|
|
1701 |
|
|
// Activate Bank 1
|
1702 |
|
|
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
|
1703 |
|
|
// Activate to Activate (same bank)
|
1704 |
|
|
if ($realtime - RC_chk1 < tRC) begin
|
1705 |
|
|
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
|
1706 |
|
|
end
|
1707 |
|
|
|
1708 |
|
|
// Precharge to Activate
|
1709 |
|
|
if ($realtime - RP_chk1 < tRP) begin
|
1710 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
|
1711 |
|
|
end
|
1712 |
|
|
|
1713 |
|
|
// Record variables for checking violation
|
1714 |
|
|
Act_b1 = 1'b1;
|
1715 |
|
|
Pc_b1 = 1'b0;
|
1716 |
|
|
B1_row_addr = Addr;
|
1717 |
|
|
RC_chk1 = $realtime;
|
1718 |
|
|
RCD_chk1 = $realtime;
|
1719 |
|
|
RAS_chk1 = $realtime;
|
1720 |
|
|
RAP_chk1 = $realtime;
|
1721 |
|
|
end
|
1722 |
|
|
|
1723 |
|
|
// Activate Bank 2
|
1724 |
|
|
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
|
1725 |
|
|
// Activate to Activate (same bank)
|
1726 |
|
|
if ($realtime - RC_chk2 < tRC) begin
|
1727 |
|
|
$display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
|
1728 |
|
|
end
|
1729 |
|
|
|
1730 |
|
|
// Precharge to Activate
|
1731 |
|
|
if ($realtime - RP_chk2 < tRP) begin
|
1732 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
|
1733 |
|
|
end
|
1734 |
|
|
|
1735 |
|
|
// Record variables for checking violation
|
1736 |
|
|
Act_b2 = 1'b1;
|
1737 |
|
|
Pc_b2 = 1'b0;
|
1738 |
|
|
B2_row_addr = Addr;
|
1739 |
|
|
RC_chk2 = $realtime;
|
1740 |
|
|
RCD_chk2 = $realtime;
|
1741 |
|
|
RAS_chk2 = $realtime;
|
1742 |
|
|
RAP_chk2 = $realtime;
|
1743 |
|
|
end
|
1744 |
|
|
|
1745 |
|
|
// Activate Bank 3
|
1746 |
|
|
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
|
1747 |
|
|
// Activate to Activate (same bank)
|
1748 |
|
|
if ($realtime - RC_chk3 < tRC) begin
|
1749 |
|
|
$display ("%m: t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
|
1750 |
|
|
end
|
1751 |
|
|
|
1752 |
|
|
// Precharge to Activate
|
1753 |
|
|
if ($realtime - RP_chk3 < tRP) begin
|
1754 |
|
|
$display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
|
1755 |
|
|
end
|
1756 |
|
|
|
1757 |
|
|
// Record variables for checking violation
|
1758 |
|
|
Act_b3 = 1'b1;
|
1759 |
|
|
Pc_b3 = 1'b0;
|
1760 |
|
|
B3_row_addr = Addr;
|
1761 |
|
|
RC_chk3 = $realtime;
|
1762 |
|
|
RCD_chk3 = $realtime;
|
1763 |
|
|
RAS_chk3 = $realtime;
|
1764 |
|
|
RAP_chk3 = $realtime;
|
1765 |
|
|
end
|
1766 |
|
|
|
1767 |
|
|
// Activate to Activate (different bank)
|
1768 |
|
|
if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD)) begin
|
1769 |
|
|
$display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba);
|
1770 |
|
|
end
|
1771 |
|
|
|
1772 |
|
|
// AutoRefresh to Activate
|
1773 |
|
|
if ($realtime - RFC_chk < tRFC) begin
|
1774 |
|
|
$display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba);
|
1775 |
|
|
end
|
1776 |
|
|
|
1777 |
|
|
// Record variable for checking violation
|
1778 |
|
|
RRD_chk = $realtime;
|
1779 |
|
|
Prev_bank = Ba;
|
1780 |
|
|
end
|
1781 |
|
|
|
1782 |
|
|
// Precharge Block - consider NOP if bank already precharged or in process of precharging
|
1783 |
|
|
if (Prech_enable === 1'b1) begin
|
1784 |
|
|
// Display Debug Message
|
1785 |
|
|
if (Debug) begin
|
1786 |
|
|
$display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
|
1787 |
|
|
end
|
1788 |
|
|
|
1789 |
|
|
// EMR or LMR to Precharge
|
1790 |
|
|
// if ($realtime - MRD_chk < tMRD) begin
|
1791 |
|
|
// $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
|
1792 |
|
|
// end
|
1793 |
|
|
if (MRD_cntr < tMRD) begin
|
1794 |
|
|
$display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
|
1795 |
|
|
end
|
1796 |
|
|
|
1797 |
|
|
// Precharge bank 0
|
1798 |
|
|
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
|
1799 |
|
|
Act_b0 = 1'b0;
|
1800 |
|
|
Pc_b0 = 1'b1;
|
1801 |
|
|
RP_chk0 = $realtime;
|
1802 |
|
|
|
1803 |
|
|
// Activate to Precharge Bank
|
1804 |
|
|
if ($realtime - RAS_chk0 < tRAS) begin
|
1805 |
|
|
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
|
1806 |
|
|
end
|
1807 |
|
|
|
1808 |
|
|
// tWR violation check for Write
|
1809 |
|
|
if ($realtime - WR_chk0 < tWR) begin
|
1810 |
|
|
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
|
1811 |
|
|
end
|
1812 |
|
|
end
|
1813 |
|
|
|
1814 |
|
|
// Precharge bank 1
|
1815 |
|
|
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
|
1816 |
|
|
Act_b1 = 1'b0;
|
1817 |
|
|
Pc_b1 = 1'b1;
|
1818 |
|
|
RP_chk1 = $realtime;
|
1819 |
|
|
|
1820 |
|
|
// Activate to Precharge Bank 1
|
1821 |
|
|
if ($realtime - RAS_chk1 < tRAS) begin
|
1822 |
|
|
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
|
1823 |
|
|
end
|
1824 |
|
|
|
1825 |
|
|
// tWR violation check for Write
|
1826 |
|
|
if ($realtime - WR_chk1 < tWR) begin
|
1827 |
|
|
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
|
1828 |
|
|
end
|
1829 |
|
|
end
|
1830 |
|
|
|
1831 |
|
|
// Precharge bank 2
|
1832 |
|
|
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
|
1833 |
|
|
Act_b2 = 1'b0;
|
1834 |
|
|
Pc_b2 = 1'b1;
|
1835 |
|
|
RP_chk2 = $realtime;
|
1836 |
|
|
|
1837 |
|
|
// Activate to Precharge Bank 2
|
1838 |
|
|
if ($realtime - RAS_chk2 < tRAS) begin
|
1839 |
|
|
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
|
1840 |
|
|
end
|
1841 |
|
|
|
1842 |
|
|
// tWR violation check for Write
|
1843 |
|
|
if ($realtime - WR_chk2 < tWR) begin
|
1844 |
|
|
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
|
1845 |
|
|
end
|
1846 |
|
|
end
|
1847 |
|
|
|
1848 |
|
|
// Precharge bank 3
|
1849 |
|
|
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
|
1850 |
|
|
Act_b3 = 1'b0;
|
1851 |
|
|
Pc_b3 = 1'b1;
|
1852 |
|
|
RP_chk3 = $realtime;
|
1853 |
|
|
|
1854 |
|
|
// Activate to Precharge Bank 3
|
1855 |
|
|
if ($realtime - RAS_chk3 < tRAS) begin
|
1856 |
|
|
$display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
|
1857 |
|
|
end
|
1858 |
|
|
|
1859 |
|
|
// tWR violation check for Write
|
1860 |
|
|
if ($realtime - WR_chk3 < tWR) begin
|
1861 |
|
|
$display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
|
1862 |
|
|
end
|
1863 |
|
|
end
|
1864 |
|
|
|
1865 |
|
|
// Pipeline for READ
|
1866 |
|
|
A10_precharge [cas_latency_x2] = Addr[10];
|
1867 |
|
|
Bank_precharge[cas_latency_x2] = Ba;
|
1868 |
|
|
Cmnd_precharge[cas_latency_x2] = 1'b1;
|
1869 |
|
|
end
|
1870 |
|
|
|
1871 |
|
|
// Burst terminate
|
1872 |
|
|
if (Burst_term === 1'b1) begin
|
1873 |
|
|
// Display Debug Message
|
1874 |
|
|
if (Debug) begin
|
1875 |
|
|
$display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime);
|
1876 |
|
|
end
|
1877 |
|
|
|
1878 |
|
|
// Burst Terminate Command Pipeline for Read
|
1879 |
|
|
Cmnd_bst[cas_latency_x2-1] = 1'b1;
|
1880 |
|
|
|
1881 |
|
|
// Illegal to burst terminate a Write
|
1882 |
|
|
if (Data_in_enable === 1'b1) begin
|
1883 |
|
|
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime);
|
1884 |
|
|
end
|
1885 |
|
|
|
1886 |
|
|
// Illegal to burst terminate a Read with Auto Precharge
|
1887 |
|
|
if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
|
1888 |
|
|
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
|
1889 |
|
|
$display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime);
|
1890 |
|
|
end
|
1891 |
|
|
end
|
1892 |
|
|
|
1893 |
|
|
// Read Command
|
1894 |
|
|
if (Read_enable === 1'b1) begin
|
1895 |
|
|
if (!(power_up_done)) begin
|
1896 |
|
|
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime);
|
1897 |
|
|
end
|
1898 |
|
|
// Display Debug Message
|
1899 |
|
|
if (Debug) begin
|
1900 |
|
|
$display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]});
|
1901 |
|
|
end
|
1902 |
|
|
if (part_size == 1024) begin
|
1903 |
|
|
if (SRR_read == 1'b1) begin
|
1904 |
|
|
if (SRR_cntr < tSRR) begin
|
1905 |
|
|
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
|
1906 |
|
|
end
|
1907 |
|
|
SRC_cntr = 0 ;
|
1908 |
|
|
end
|
1909 |
|
|
end else begin
|
1910 |
|
|
if (SRR_read == 1'b1) begin
|
1911 |
|
|
if ($realtime - SRR_chk < tSRR-0.01) begin
|
1912 |
|
|
$display ("%m: At time %t ERROR: tSRR Violation", $realtime);
|
1913 |
|
|
end
|
1914 |
|
|
SRC_cntr = 0;
|
1915 |
|
|
end
|
1916 |
|
|
end
|
1917 |
|
|
// CAS Latency pipeline
|
1918 |
|
|
Read_cmnd[cas_latency_x2] = 1'b1;
|
1919 |
|
|
Read_bank[cas_latency_x2] = Ba;
|
1920 |
|
|
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
|
1921 |
|
|
|
1922 |
|
|
// Terminate a Write
|
1923 |
|
|
if (Data_in_enable === 1'b1) begin
|
1924 |
|
|
Data_in_enable = 1'b0;
|
1925 |
|
|
end
|
1926 |
|
|
|
1927 |
|
|
// Interrupt a Read with Auto Precharge
|
1928 |
|
|
if (Read_precharge [Ba] === 1'b1) begin
|
1929 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
|
1930 |
|
|
end else if ((Read_precharge [0] === 1'b1) |
|
1931 |
|
|
(Read_precharge [1] === 1'b1) |
|
1932 |
|
|
(Read_precharge [2] === 1'b1) |
|
1933 |
|
|
(Read_precharge [3] === 1'b1) ) begin
|
1934 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime);
|
1935 |
|
|
end
|
1936 |
|
|
|
1937 |
|
|
// Interrupt a Write with Auto Precharge
|
1938 |
|
|
if (Write_precharge [Ba] === 1'b1) begin
|
1939 |
|
|
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime);
|
1940 |
|
|
end else if ((Write_precharge_count [0] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
|
1941 |
|
|
(Write_precharge_count [1] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
|
1942 |
|
|
(Write_precharge_count [2] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
|
1943 |
|
|
(Write_precharge_count [3] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) |
|
1944 |
|
|
(Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
|
1945 |
|
|
(Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
|
1946 |
|
|
(Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
|
1947 |
|
|
(Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin
|
1948 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime);
|
1949 |
|
|
end
|
1950 |
|
|
|
1951 |
|
|
// Activate to Read
|
1952 |
|
|
if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
|
1953 |
|
|
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) &&
|
1954 |
|
|
(SRR_read == 1'b0)) begin
|
1955 |
|
|
$display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime);
|
1956 |
|
|
end
|
1957 |
|
|
|
1958 |
|
|
// Activate to Read without Auto Precharge
|
1959 |
|
|
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
|
1960 |
|
|
(Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
|
1961 |
|
|
(Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
|
1962 |
|
|
(Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
|
1963 |
|
|
$display("%m: At time %t ERROR: tRCD violation during Read", $realtime);
|
1964 |
|
|
end
|
1965 |
|
|
|
1966 |
|
|
// Auto Precharge
|
1967 |
|
|
if (Addr[10] === 1'b1) begin
|
1968 |
|
|
Read_precharge [Ba]= 1'b1;
|
1969 |
|
|
Count_precharge [Ba]= 0;
|
1970 |
|
|
Read_precharge_count[Ba] = 4'h0;
|
1971 |
|
|
end
|
1972 |
|
|
end
|
1973 |
|
|
|
1974 |
|
|
// Write Command
|
1975 |
|
|
if (Write_enable === 1'b1) begin
|
1976 |
|
|
if (!(power_up_done)) begin
|
1977 |
|
|
$display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime);
|
1978 |
|
|
end
|
1979 |
|
|
// display debug message
|
1980 |
|
|
if (Debug) begin
|
1981 |
|
|
$display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
|
1982 |
|
|
end
|
1983 |
|
|
|
1984 |
|
|
// Pipeline for Write
|
1985 |
|
|
Write_cmnd [3] = 1'b1;
|
1986 |
|
|
Write_bank [3] = Ba;
|
1987 |
|
|
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
|
1988 |
|
|
|
1989 |
|
|
// Interrupt a Write with Auto Precharge (same bank only)
|
1990 |
|
|
if (Write_precharge [Ba] === 1'b1) begin
|
1991 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime);
|
1992 |
|
|
end
|
1993 |
|
|
|
1994 |
|
|
// Activate to Write
|
1995 |
|
|
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
|
1996 |
|
|
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
|
1997 |
|
|
$display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime);
|
1998 |
|
|
end
|
1999 |
|
|
|
2000 |
|
|
// Activate to Write
|
2001 |
|
|
if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) ||
|
2002 |
|
|
(Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) ||
|
2003 |
|
|
(Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) ||
|
2004 |
|
|
(Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin
|
2005 |
|
|
$display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba);
|
2006 |
|
|
end
|
2007 |
|
|
|
2008 |
|
|
// Read to Write
|
2009 |
|
|
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
|
2010 |
|
|
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter_dly < burst_length)) begin
|
2011 |
|
|
if (Data_out_enable_dly || read_precharge_truncation) begin
|
2012 |
|
|
$display("%m: At time %t ERROR: Read to Write violation", $realtime);
|
2013 |
|
|
end
|
2014 |
|
|
end
|
2015 |
|
|
|
2016 |
|
|
// Interrupt a Write with Auto Precharge
|
2017 |
|
|
if (Write_precharge [Ba] === 1'b1) begin
|
2018 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime);
|
2019 |
|
|
end else if (((Write_precharge [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) |
|
2020 |
|
|
((Write_precharge [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) |
|
2021 |
|
|
((Write_precharge [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) |
|
2022 |
|
|
((Write_precharge [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin
|
2023 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime);
|
2024 |
|
|
end
|
2025 |
|
|
|
2026 |
|
|
// Interrupt a Read with Auto Precharge
|
2027 |
|
|
if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
|
2028 |
|
|
((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
|
2029 |
|
|
// $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
|
2030 |
|
|
end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
|
2031 |
|
|
((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
|
2032 |
|
|
((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
|
2033 |
|
|
((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
|
2034 |
|
|
((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
|
2035 |
|
|
((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
|
2036 |
|
|
((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
|
2037 |
|
|
((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
|
2038 |
|
|
$display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime);
|
2039 |
|
|
end
|
2040 |
|
|
|
2041 |
|
|
// Auto Precharge
|
2042 |
|
|
if (Addr[10] === 1'b1) begin
|
2043 |
|
|
Write_precharge [Ba]= 1'b1;
|
2044 |
|
|
Count_precharge [Ba]= 0;
|
2045 |
|
|
Write_precharge_count[Ba] = 4'h0;
|
2046 |
|
|
end
|
2047 |
|
|
end
|
2048 |
|
|
|
2049 |
|
|
end
|
2050 |
|
|
endtask
|
2051 |
|
|
|
2052 |
|
|
// Main Logic
|
2053 |
|
|
always @ (posedge Sys_clk) begin
|
2054 |
|
|
Manual_Precharge_Pipeline;
|
2055 |
|
|
Burst_Terminate_Pipeline;
|
2056 |
|
|
Dq_Dqs_Drivers;
|
2057 |
|
|
Write_FIFO_DM_Mask_Logic;
|
2058 |
|
|
Burst_Decode;
|
2059 |
|
|
Auto_Precharge_Calculation;
|
2060 |
|
|
Timing_chk_SRC;
|
2061 |
|
|
Control_Logic;
|
2062 |
|
|
MRD_counter;
|
2063 |
|
|
SRR_counter;
|
2064 |
|
|
SRC_counter;
|
2065 |
|
|
command_counter;
|
2066 |
|
|
end
|
2067 |
|
|
|
2068 |
|
|
always @ (negedge Sys_clk) begin
|
2069 |
|
|
Manual_Precharge_Pipeline;
|
2070 |
|
|
Burst_Terminate_Pipeline;
|
2071 |
|
|
Dq_Dqs_Drivers;
|
2072 |
|
|
Write_FIFO_DM_Mask_Logic;
|
2073 |
|
|
Burst_Decode;
|
2074 |
|
|
end
|
2075 |
|
|
|
2076 |
|
|
// Dqs Receiver
|
2077 |
|
|
always @ (posedge Dqs_in[0]) begin
|
2078 |
|
|
// Latch data at posedge Dqs
|
2079 |
|
|
dq_rise[7 : 0] = Dq_in[7 : 0];
|
2080 |
|
|
dm_rise[0] = Dm_in[0];
|
2081 |
|
|
expect_pos_dqs[0] = 0;
|
2082 |
|
|
end
|
2083 |
|
|
|
2084 |
|
|
always @ (posedge Dqs_in[1]) begin
|
2085 |
|
|
// Latch data at posedge Dqs
|
2086 |
|
|
dq_rise[15 : 8] = Dq_in[15 : 8];
|
2087 |
|
|
dm_rise[1] = Dm_in [1];
|
2088 |
|
|
expect_pos_dqs[1] = 0;
|
2089 |
|
|
end
|
2090 |
|
|
|
2091 |
|
|
`ifdef x32
|
2092 |
|
|
always @ (posedge Dqs_in[2]) begin
|
2093 |
|
|
// Latch data at posedge Dqs
|
2094 |
|
|
dq_rise[23 : 16] = Dq_in[23 : 16];
|
2095 |
|
|
dm_rise[2] = Dm_in [2];
|
2096 |
|
|
expect_pos_dqs[2] = 0;
|
2097 |
|
|
end
|
2098 |
|
|
|
2099 |
|
|
always @ (posedge Dqs_in[3]) begin
|
2100 |
|
|
// Latch data at posedge Dqs
|
2101 |
|
|
dq_rise[31 : 24] = Dq_in[31 : 24];
|
2102 |
|
|
dm_rise[3] = Dm_in [3];
|
2103 |
|
|
expect_pos_dqs[3] = 0;
|
2104 |
|
|
end
|
2105 |
|
|
`endif
|
2106 |
|
|
|
2107 |
|
|
always @ (negedge Dqs_in[0]) begin
|
2108 |
|
|
// Latch data at negedge Dqs
|
2109 |
|
|
dq_fall[7 : 0] = Dq_in[7 : 0];
|
2110 |
|
|
dm_fall[0] = Dm_in[0];
|
2111 |
|
|
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
|
2112 |
|
|
expect_neg_dqs[0] = 0;
|
2113 |
|
|
end
|
2114 |
|
|
|
2115 |
|
|
always @ (negedge Dqs_in[1]) begin
|
2116 |
|
|
// Latch data at negedge Dqs
|
2117 |
|
|
dq_fall[15: 8] = Dq_in[15 : 8];
|
2118 |
|
|
dm_fall[1] = Dm_in[1];
|
2119 |
|
|
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
|
2120 |
|
|
expect_neg_dqs[1] = 0;
|
2121 |
|
|
end
|
2122 |
|
|
|
2123 |
|
|
`ifdef x32
|
2124 |
|
|
always @ (negedge Dqs_in[2]) begin
|
2125 |
|
|
// Latch data at negedge Dqs
|
2126 |
|
|
dq_fall[23: 16] = Dq_in[23 : 16];
|
2127 |
|
|
dm_fall[2] = Dm_in[2];
|
2128 |
|
|
dm_pair[5:4] = {dm_rise[2], dm_fall[2]};
|
2129 |
|
|
expect_neg_dqs[2] = 0;
|
2130 |
|
|
end
|
2131 |
|
|
|
2132 |
|
|
always @ (negedge Dqs_in[3]) begin
|
2133 |
|
|
// Latch data at negedge Dqs
|
2134 |
|
|
dq_fall[31: 24] = Dq_in[31 : 24];
|
2135 |
|
|
dm_fall[3] = Dm_in[3];
|
2136 |
|
|
dm_pair[7:6] = {dm_rise[3], dm_fall[3]};
|
2137 |
|
|
expect_neg_dqs[3] = 0;
|
2138 |
|
|
end
|
2139 |
|
|
`endif
|
2140 |
|
|
|
2141 |
|
|
// Dqs edge checking
|
2142 |
|
|
always @ (posedge Sys_clk) begin
|
2143 |
|
|
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
|
2144 |
|
|
for (i=0; i<DQS_BITS; i=i+1) begin
|
2145 |
|
|
if (expect_neg_dqs[i]) begin
|
2146 |
|
|
$display ("%m: At time %t ERROR: Negative DQS[%1d] transition required.", $realtime, i);
|
2147 |
|
|
end
|
2148 |
|
|
expect_neg_dqs[i] = 1'b1;
|
2149 |
|
|
end
|
2150 |
|
|
end else begin
|
2151 |
|
|
expect_neg_dqs = 0;
|
2152 |
|
|
expect_pos_dqs = 0;
|
2153 |
|
|
end
|
2154 |
|
|
end
|
2155 |
|
|
|
2156 |
|
|
always @ (negedge Sys_clk) begin
|
2157 |
|
|
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
|
2158 |
|
|
for (i=0; i<DQS_BITS; i=i+1) begin
|
2159 |
|
|
if (expect_pos_dqs[i]) begin
|
2160 |
|
|
$display ("%m: At time %t ERROR: Positive DQS[%1d] transition required.", $realtime, i);
|
2161 |
|
|
end
|
2162 |
|
|
expect_pos_dqs[i] = 1'b1;
|
2163 |
|
|
end
|
2164 |
|
|
end else begin
|
2165 |
|
|
expect_neg_dqs = 0;
|
2166 |
|
|
expect_pos_dqs = 0;
|
2167 |
|
|
end
|
2168 |
|
|
end
|
2169 |
|
|
|
2170 |
|
|
specify
|
2171 |
|
|
// SYMBOL UNITS DESCRIPTION
|
2172 |
|
|
// ------ ----- -----------
|
2173 |
|
|
`ifdef sg5 // specparams for -6 (CL = 3)
|
2174 |
|
|
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
|
2175 |
|
|
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2176 |
|
|
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2177 |
|
|
specparam tIH = 1.0 ; // tIH ns Input Hold Time (fast)
|
2178 |
|
|
specparam tIS = 1.0 ; // tIS ns Input Setup Time (fast)
|
2179 |
|
|
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width
|
2180 |
|
|
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width
|
2181 |
|
|
`else `ifdef sg6 // specparams for -6 (CL = 3)
|
2182 |
|
|
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
|
2183 |
|
|
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2184 |
|
|
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2185 |
|
|
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
|
2186 |
|
|
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
|
2187 |
|
|
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
|
2188 |
|
|
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
|
2189 |
|
|
`else `ifdef sg75 // specparams for -75 (CL = 3)
|
2190 |
|
|
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
|
2191 |
|
|
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2192 |
|
|
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2193 |
|
|
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
|
2194 |
|
|
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
|
2195 |
|
|
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
|
2196 |
|
|
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
|
2197 |
|
|
`else`ifdef sg5v18 // specparams for -6 (CL = 3)
|
2198 |
|
|
specparam tCLK_MIN = 5.0 ; // tCLK ns minimum clk cycle time
|
2199 |
|
|
specparam tDSS = 1.0 ; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2200 |
|
|
specparam tDSH = 1.0 ; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2201 |
|
|
specparam tIH = 0.9 ; // tIH ns Input Hold Time (fast)
|
2202 |
|
|
specparam tIS = 0.9 ; // tIS ns Input Setup Time (fast)
|
2203 |
|
|
specparam tDQSH = 2.0 ; // tDQSH ns DQS input High Pulse Width
|
2204 |
|
|
specparam tDQSL = 2.0 ; // tDQSL ns DQS input Low Pulse Width
|
2205 |
|
|
`else `ifdef sg6v18 // specparams for -6 (CL = 3)
|
2206 |
|
|
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
|
2207 |
|
|
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2208 |
|
|
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2209 |
|
|
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
|
2210 |
|
|
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
|
2211 |
|
|
specparam tDQSH = 2.4; // tDQSH ns DQS input High Pulse Width
|
2212 |
|
|
specparam tDQSL = 2.4; // tDQSL ns DQS input Low Pulse Width
|
2213 |
|
|
`else `ifdef sg75v18 // specparams for -75 (CL = 3)
|
2214 |
|
|
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
|
2215 |
|
|
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2216 |
|
|
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2217 |
|
|
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
|
2218 |
|
|
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
|
2219 |
|
|
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
|
2220 |
|
|
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
|
2221 |
|
|
`else `ifdef sg6v12 // specparams for -6 (CL = 3)
|
2222 |
|
|
specparam tCLK_MIN = 6.0; // tCLK ns minimum clk cycle time
|
2223 |
|
|
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2224 |
|
|
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2225 |
|
|
specparam tIH = 1.1; // tIH ns Input Hold Time (fast)
|
2226 |
|
|
specparam tIS = 1.1; // tIS ns Input Setup Time (fast)
|
2227 |
|
|
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width
|
2228 |
|
|
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width
|
2229 |
|
|
`else `ifdef sg75v12 // specparams for -75 (CL = 3)
|
2230 |
|
|
specparam tCLK_MIN = 7.5; // tCLK ns minimum clk cycle time
|
2231 |
|
|
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2232 |
|
|
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2233 |
|
|
specparam tIH = 1.3; // tIH ns Input Hold Time (fast)
|
2234 |
|
|
specparam tIS = 1.3; // tIS ns Input Setup Time (fast)
|
2235 |
|
|
specparam tDQSH = 3.0; // tDQSH ns DQS input High Pulse Width
|
2236 |
|
|
specparam tDQSL = 3.0; // tDQSL ns DQS input Low Pulse Width
|
2237 |
|
|
`else `ifdef sg10v12 // specparams for -10 (CL = 3)
|
2238 |
|
|
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
|
2239 |
|
|
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2240 |
|
|
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2241 |
|
|
specparam tIH = 1.7; // tIH ns Input Hold Time (fast)
|
2242 |
|
|
specparam tIS = 1.7; // tIS ns Input Setup Time (fast)
|
2243 |
|
|
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
|
2244 |
|
|
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
|
2245 |
|
|
`else `ifdef sg10 // specparams for -10 (CL = 3)
|
2246 |
|
|
specparam tCLK_MIN = 9.6; // tCLK ns minimum clk cycle time
|
2247 |
|
|
specparam tDSS = 1.92; // tDSS ns DQS falling edge to CLK rising (setup time)
|
2248 |
|
|
specparam tDSH = 1.92; // tDSH ns DQS falling edge from CLK rising (hold time)
|
2249 |
|
|
specparam tIH = 1.5; // tIH ns Input Hold Time (fast)
|
2250 |
|
|
specparam tIS = 1.5; // tIS ns Input Setup Time (fast)
|
2251 |
|
|
specparam tDQSH = 3.84; // tDQSH ns DQS input High Pulse Width
|
2252 |
|
|
specparam tDQSL = 3.84; // tDQSL ns DQS input Low Pulse Width
|
2253 |
|
|
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
|
2254 |
|
|
$period (posedge Clk, tCLK_MIN);
|
2255 |
|
|
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
|
2256 |
|
|
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
|
2257 |
|
|
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
|
2258 |
|
|
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
|
2259 |
|
|
$setuphold(posedge Clk, Cke, tIS, tIH);
|
2260 |
|
|
$setuphold(posedge Clk, Cs_n, tIS, tIH);
|
2261 |
|
|
$setuphold(posedge Clk, Cas_n, tIS, tIH);
|
2262 |
|
|
$setuphold(posedge Clk, Ras_n, tIS, tIH);
|
2263 |
|
|
$setuphold(posedge Clk, We_n, tIS, tIH);
|
2264 |
|
|
$setuphold(posedge Clk, Addr, tIS, tIH);
|
2265 |
|
|
$setuphold(posedge Clk, Ba, tIS, tIH);
|
2266 |
|
|
$setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS , tDSH);
|
2267 |
|
|
endspecify
|
2268 |
|
|
|
2269 |
|
|
endmodule
|