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dimamali |
-----------------------------------------------------------------------------------------
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--
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-- File Name: MT46V16M16.VHD
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-- Version: 3.1
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-- Date: January 14th, 2002
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-- Model: Behavioral
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-- Simulator: NCDesktop - http://www.cadence.com
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-- ModelSim PE - http://www.model.com
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--
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-- Dependencies: None
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--
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-- Email: modelsupport@micron.com
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-- Company: Micron Technology, Inc.
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-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
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--
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-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
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--
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-- Limitation: Doesn't model internal refresh counter
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--
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-- Note:
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--
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-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
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-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
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-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
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-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
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--
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-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
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-- All rights researved
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--
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-- Rev Author Date Changes
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-- --- ---------------------------- ---------- -------------------------------------
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-- 2.1 SH 01/14/2002 - Fix Burst_counter
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-- Micron Technology, Inc.
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--
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-- 2.0 SH 11/08/2001 - Second release
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-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
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-- 3.1 Craig Hanson cahanson 05/28/2003 - update all models to release version 3.1
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-- @micron.com (no changes to this model)
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-----------------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY WORK;
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USE WORK.MTI_PKG.ALL;
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use std.textio.all;
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library grlib;
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use grlib.stdlib.all;
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library gaisler;
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use gaisler.sim.all;
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ENTITY MT46V16M16 IS
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GENERIC ( -- Timing for -75Z CL2
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tCK : TIME := 7.500 ns;
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tCH : TIME := 3.375 ns; -- 0.45*tCK
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tCL : TIME := 3.375 ns; -- 0.45*tCK
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tDH : TIME := 0.500 ns;
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tDS : TIME := 0.500 ns;
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tIH : TIME := 0.900 ns;
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tIS : TIME := 0.900 ns;
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tMRD : TIME := 15.000 ns;
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tRAS : TIME := 40.000 ns;
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tRAP : TIME := 20.000 ns;
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tRC : TIME := 65.000 ns;
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tRFC : TIME := 75.000 ns;
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tRCD : TIME := 20.000 ns;
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tRP : TIME := 20.000 ns;
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tRRD : TIME := 15.000 ns;
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tWR : TIME := 15.000 ns;
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addr_bits : INTEGER := 13;
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data_bits : INTEGER := 16;
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cols_bits : INTEGER := 9;
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index : INTEGER := 0;
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fname : string := "sdram.srec"; -- File to read from
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bbits : INTEGER := 16
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);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
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Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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Clk : IN STD_LOGIC;
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Clk_n : IN STD_LOGIC;
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Cke : IN STD_LOGIC;
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Cs_n : IN STD_LOGIC;
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Ras_n : IN STD_LOGIC;
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Cas_n : IN STD_LOGIC;
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We_n : IN STD_LOGIC;
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Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
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);
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END MT46V16M16;
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ARCHITECTURE behave OF MT46V16M16 IS
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-- Array for Read pipeline
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TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
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TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
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TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
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-- Array for Write pipeline
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TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
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TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
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TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
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-- Array for Auto Precharge
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TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
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TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
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TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
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-- Array for Manual Precharge
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TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
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TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
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TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
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-- Array for Burst Terminate
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TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
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-- Array for Memory Access
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TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
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TYPE Array_ram_pntr IS ACCESS Array_ram_type;
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TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
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-- Data pair
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SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
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SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
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-- Mode Register
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SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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-- Command Decode Variables
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SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
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SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
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-- Burst Length Decode Variables
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SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
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-- Cas Latency Decode Variables
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SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
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-- Internal Control Signals
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SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
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-- System Clock
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SIGNAL Sys_clk : STD_LOGIC := '0';
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-- Dqs buffer
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SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
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BEGIN
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-- Strip the strength
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Cs_in <= To_X01 (Cs_n);
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Ras_in <= To_X01 (Ras_n);
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Cas_in <= To_X01 (Cas_n);
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We_in <= To_X01 (We_n);
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-- Commands Decode
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Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
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Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
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Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
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Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
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Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
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Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
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Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
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Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
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-- Burst Length Decode
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Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
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Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
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Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
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Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
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-- CAS Latency Decode
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Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
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Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
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Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
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Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
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Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
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-- Dqs buffer
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Dqs <= Dqs_out;
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--
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-- System Clock
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--
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int_clk : PROCESS (Clk, Clk_n)
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VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
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begin
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IF Clk = '1' AND Clk_n = '0' THEN
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ClkZ := '1';
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CkeZ := Cke;
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ELSIF Clk = '0' AND Clk_n = '1' THEN
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ClkZ := '0';
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END IF;
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Sys_clk <= CkeZ AND ClkZ;
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END PROCESS;
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--
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-- Main Process
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--
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state_register : PROCESS
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-- Precharge Variables
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VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
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-- Activate Variables
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VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
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-- Data IO variables
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VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
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-- Internal address mux variables
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VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
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VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
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VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
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VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
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VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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-- DLL Reset variables
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VARIABLE DLL_enable : STD_LOGIC := '0';
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VARIABLE DLL_reset : STD_LOGIC := '0';
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VARIABLE DLL_done : STD_LOGIC := '0';
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VARIABLE DLL_count : INTEGER := 0;
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-- Timing Check
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VARIABLE MRD_chk : TIME := 0 ns;
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VARIABLE RFC_chk : TIME := 0 ns;
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VARIABLE RRD_chk : TIME := 0 ns;
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VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
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VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
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VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
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VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
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VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
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VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
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-- Read pipeline variables
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VARIABLE Read_cmnd : Array_Read_cmnd;
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VARIABLE Read_bank : Array_Read_bank;
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VARIABLE Read_cols : Array_Read_cols;
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-- Write pipeline variables
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VARIABLE Write_cmnd : Array_Write_cmnd;
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VARIABLE Write_bank : Array_Write_bank;
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VARIABLE Write_cols : Array_Write_cols;
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-- Auto Precharge variables
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VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
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VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
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VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
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-- Manual Precharge variables
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VARIABLE A10_precharge : Array_A10_precharge;
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VARIABLE Bank_precharge : Array_Bank_precharge;
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VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
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-- Burst Terminate variable
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VARIABLE Cmnd_bst : Array_Cmnd_bst;
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-- Memory Banks
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VARIABLE Bank0 : Array_ram_stor;
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VARIABLE Bank1 : Array_ram_stor;
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VARIABLE Bank2 : Array_ram_stor;
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VARIABLE Bank3 : Array_ram_stor;
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-- Burst Counter
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VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
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-- Internal Dqs initialize
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VARIABLE Dqs_int : STD_LOGIC := '0';
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-- Data buffer for DM Mask
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VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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-- Load and Dumb variables
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FILE file_load : TEXT open read_mode is fname; -- Data load
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FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
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VARIABLE Bank_Load : std_logic_vector ( 1 DOWNTO 0);
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VARIABLE rows_load : std_logic_vector (12 DOWNTO 0);
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VARIABLE cols_load : std_logic_vector ( 8 DOWNTO 0);
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VARIABLE data_load : std_logic_vector (15 DOWNTO 0);
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VARIABLE i, j : INTEGER;
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VARIABLE good_load : BOOLEAN;
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VARIABLE l : LINE;
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variable file_loaded : boolean := false;
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variable dump : std_logic := '0';
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variable ch : character;
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variable rectype : std_logic_vector(3 downto 0);
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variable recaddr : std_logic_vector(31 downto 0);
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variable reclen : std_logic_vector(7 downto 0);
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variable recdata : std_logic_vector(0 to 16*8-1);
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--
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295 |
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-- Initialize empty rows
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--
|
297 |
|
|
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
|
298 |
|
|
VARIABLE i, j : INTEGER := 0;
|
299 |
|
|
BEGIN
|
300 |
|
|
IF Bank = "00" THEN
|
301 |
|
|
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
|
302 |
|
|
Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
|
303 |
|
|
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
|
304 |
|
|
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
|
305 |
|
|
Bank0 (Row_index) (i) (j) := '0';
|
306 |
|
|
END LOOP;
|
307 |
|
|
END LOOP;
|
308 |
|
|
END IF;
|
309 |
|
|
ELSIF Bank = "01" THEN
|
310 |
|
|
IF Bank1 (Row_index) = NULL THEN
|
311 |
|
|
Bank1 (Row_index) := NEW Array_ram_type;
|
312 |
|
|
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
|
313 |
|
|
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
|
314 |
|
|
Bank1 (Row_index) (i) (j) := '0';
|
315 |
|
|
END LOOP;
|
316 |
|
|
END LOOP;
|
317 |
|
|
END IF;
|
318 |
|
|
ELSIF Bank = "10" THEN
|
319 |
|
|
IF Bank2 (Row_index) = NULL THEN
|
320 |
|
|
Bank2 (Row_index) := NEW Array_ram_type;
|
321 |
|
|
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
|
322 |
|
|
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
|
323 |
|
|
Bank2 (Row_index) (i) (j) := '0';
|
324 |
|
|
END LOOP;
|
325 |
|
|
END LOOP;
|
326 |
|
|
END IF;
|
327 |
|
|
ELSIF Bank = "11" THEN
|
328 |
|
|
IF Bank3 (Row_index) = NULL THEN
|
329 |
|
|
Bank3 (Row_index) := NEW Array_ram_type;
|
330 |
|
|
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
|
331 |
|
|
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
|
332 |
|
|
Bank3 (Row_index) (i) (j) := '0';
|
333 |
|
|
END LOOP;
|
334 |
|
|
END LOOP;
|
335 |
|
|
END IF;
|
336 |
|
|
END IF;
|
337 |
|
|
END;
|
338 |
|
|
|
339 |
|
|
--
|
340 |
|
|
-- Burst Counter
|
341 |
|
|
--
|
342 |
|
|
PROCEDURE Burst_decode IS
|
343 |
|
|
VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
|
344 |
|
|
BEGIN
|
345 |
|
|
-- Advance burst counter
|
346 |
|
|
Burst_counter := Burst_counter + 1;
|
347 |
|
|
|
348 |
|
|
-- Burst Type
|
349 |
|
|
IF Mode_reg (3) = '0' THEN
|
350 |
|
|
Cols_temp := Cols_addr + 1;
|
351 |
|
|
ELSIF Mode_reg (3) = '1' THEN
|
352 |
|
|
Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
|
353 |
|
|
Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
|
354 |
|
|
Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
|
355 |
|
|
END IF;
|
356 |
|
|
|
357 |
|
|
-- Burst Length
|
358 |
|
|
IF Burst_length_2 = '1' THEN
|
359 |
|
|
Cols_addr (0) := Cols_temp (0);
|
360 |
|
|
ELSIF Burst_length_4 = '1' THEN
|
361 |
|
|
Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0);
|
362 |
|
|
ELSIF Burst_length_8 = '1' THEN
|
363 |
|
|
Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0);
|
364 |
|
|
ELSE
|
365 |
|
|
Cols_addr := Cols_temp;
|
366 |
|
|
END IF;
|
367 |
|
|
|
368 |
|
|
-- Data counter
|
369 |
|
|
IF Burst_length_2 = '1' THEN
|
370 |
|
|
IF conv_integer(Burst_counter) >= 2 THEN
|
371 |
|
|
IF Data_in_enable = '1' THEN
|
372 |
|
|
Data_in_enable := '0';
|
373 |
|
|
ELSIF Data_out_enable = '1' THEN
|
374 |
|
|
Data_out_enable := '0';
|
375 |
|
|
END IF;
|
376 |
|
|
END IF;
|
377 |
|
|
ELSIF Burst_length_4 = '1' THEN
|
378 |
|
|
IF conv_integer(Burst_counter) >= 4 THEN
|
379 |
|
|
IF Data_in_enable = '1' THEN
|
380 |
|
|
Data_in_enable := '0';
|
381 |
|
|
ELSIF Data_out_enable = '1' THEN
|
382 |
|
|
Data_out_enable := '0';
|
383 |
|
|
END IF;
|
384 |
|
|
END IF;
|
385 |
|
|
ELSIF Burst_length_8 = '1' THEN
|
386 |
|
|
IF conv_integer(Burst_counter) >= 8 THEN
|
387 |
|
|
IF Data_in_enable = '1' THEN
|
388 |
|
|
Data_in_enable := '0';
|
389 |
|
|
ELSIF Data_out_enable = '1' THEN
|
390 |
|
|
Data_out_enable := '0';
|
391 |
|
|
END IF;
|
392 |
|
|
END IF;
|
393 |
|
|
END IF;
|
394 |
|
|
END;
|
395 |
|
|
|
396 |
|
|
BEGIN
|
397 |
|
|
WAIT ON Sys_clk;
|
398 |
|
|
|
399 |
|
|
--
|
400 |
|
|
-- Manual Precharge Pipeline
|
401 |
|
|
--
|
402 |
|
|
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
|
403 |
|
|
-- A10 Precharge Pipeline
|
404 |
|
|
A10_precharge(0) := A10_precharge(1);
|
405 |
|
|
A10_precharge(1) := A10_precharge(2);
|
406 |
|
|
A10_precharge(2) := A10_precharge(3);
|
407 |
|
|
A10_precharge(3) := A10_precharge(4);
|
408 |
|
|
A10_precharge(4) := A10_precharge(5);
|
409 |
|
|
A10_precharge(5) := A10_precharge(6);
|
410 |
|
|
A10_precharge(6) := A10_precharge(7);
|
411 |
|
|
A10_precharge(7) := A10_precharge(8);
|
412 |
|
|
A10_precharge(8) := '0';
|
413 |
|
|
|
414 |
|
|
-- Bank Precharge Pipeline
|
415 |
|
|
Bank_precharge(0) := Bank_precharge(1);
|
416 |
|
|
Bank_precharge(1) := Bank_precharge(2);
|
417 |
|
|
Bank_precharge(2) := Bank_precharge(3);
|
418 |
|
|
Bank_precharge(3) := Bank_precharge(4);
|
419 |
|
|
Bank_precharge(4) := Bank_precharge(5);
|
420 |
|
|
Bank_precharge(5) := Bank_precharge(6);
|
421 |
|
|
Bank_precharge(6) := Bank_precharge(7);
|
422 |
|
|
Bank_precharge(7) := Bank_precharge(8);
|
423 |
|
|
Bank_precharge(8) := "00";
|
424 |
|
|
|
425 |
|
|
-- Command Precharge Pipeline
|
426 |
|
|
Cmnd_precharge(0) := Cmnd_precharge(1);
|
427 |
|
|
Cmnd_precharge(1) := Cmnd_precharge(2);
|
428 |
|
|
Cmnd_precharge(2) := Cmnd_precharge(3);
|
429 |
|
|
Cmnd_precharge(3) := Cmnd_precharge(4);
|
430 |
|
|
Cmnd_precharge(4) := Cmnd_precharge(5);
|
431 |
|
|
Cmnd_precharge(5) := Cmnd_precharge(6);
|
432 |
|
|
Cmnd_precharge(6) := Cmnd_precharge(7);
|
433 |
|
|
Cmnd_precharge(7) := Cmnd_precharge(8);
|
434 |
|
|
Cmnd_precharge(8) := '0';
|
435 |
|
|
|
436 |
|
|
-- Terminate Read if same bank or all banks
|
437 |
|
|
IF ((Cmnd_precharge (0) = '1') AND
|
438 |
|
|
(Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND
|
439 |
|
|
(Data_out_enable = '1')) THEN
|
440 |
|
|
Data_out_enable := '0';
|
441 |
|
|
END IF;
|
442 |
|
|
END IF;
|
443 |
|
|
|
444 |
|
|
--
|
445 |
|
|
-- Burst Terminate Pipeline
|
446 |
|
|
--
|
447 |
|
|
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
|
448 |
|
|
-- Burst Terminate pipeline
|
449 |
|
|
Cmnd_bst (0) := Cmnd_bst (1);
|
450 |
|
|
Cmnd_bst (1) := Cmnd_bst (2);
|
451 |
|
|
Cmnd_bst (2) := Cmnd_bst (3);
|
452 |
|
|
Cmnd_bst (3) := Cmnd_bst (4);
|
453 |
|
|
Cmnd_bst (4) := Cmnd_bst (5);
|
454 |
|
|
Cmnd_bst (5) := Cmnd_bst (6);
|
455 |
|
|
Cmnd_bst (6) := Cmnd_bst (7);
|
456 |
|
|
Cmnd_bst (7) := Cmnd_bst (8);
|
457 |
|
|
Cmnd_bst (8) := '0';
|
458 |
|
|
|
459 |
|
|
-- Terminate current Read
|
460 |
|
|
IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN
|
461 |
|
|
Data_out_enable := '0';
|
462 |
|
|
END IF;
|
463 |
|
|
END IF;
|
464 |
|
|
|
465 |
|
|
--
|
466 |
|
|
-- Dq and Dqs Drivers
|
467 |
|
|
--
|
468 |
|
|
IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN
|
469 |
|
|
-- Read Command Pipeline
|
470 |
|
|
Read_cmnd (0) := Read_cmnd (1);
|
471 |
|
|
Read_cmnd (1) := Read_cmnd (2);
|
472 |
|
|
Read_cmnd (2) := Read_cmnd (3);
|
473 |
|
|
Read_cmnd (3) := Read_cmnd (4);
|
474 |
|
|
Read_cmnd (4) := Read_cmnd (5);
|
475 |
|
|
Read_cmnd (5) := Read_cmnd (6);
|
476 |
|
|
Read_cmnd (6) := Read_cmnd (7);
|
477 |
|
|
Read_cmnd (7) := Read_cmnd (8);
|
478 |
|
|
Read_cmnd (8) := '0';
|
479 |
|
|
|
480 |
|
|
-- Read Bank Pipeline
|
481 |
|
|
Read_bank (0) := Read_bank (1);
|
482 |
|
|
Read_bank (1) := Read_bank (2);
|
483 |
|
|
Read_bank (2) := Read_bank (3);
|
484 |
|
|
Read_bank (3) := Read_bank (4);
|
485 |
|
|
Read_bank (4) := Read_bank (5);
|
486 |
|
|
Read_bank (5) := Read_bank (6);
|
487 |
|
|
Read_bank (6) := Read_bank (7);
|
488 |
|
|
Read_bank (7) := Read_bank (8);
|
489 |
|
|
Read_bank (8) := "00";
|
490 |
|
|
|
491 |
|
|
-- Read Column Pipeline
|
492 |
|
|
Read_cols (0) := Read_cols (1);
|
493 |
|
|
Read_cols (1) := Read_cols (2);
|
494 |
|
|
Read_cols (2) := Read_cols (3);
|
495 |
|
|
Read_cols (3) := Read_cols (4);
|
496 |
|
|
Read_cols (4) := Read_cols (5);
|
497 |
|
|
Read_cols (5) := Read_cols (6);
|
498 |
|
|
Read_cols (6) := Read_cols (7);
|
499 |
|
|
Read_cols (7) := Read_cols (8);
|
500 |
|
|
Read_cols (8) := (OTHERS => '0');
|
501 |
|
|
|
502 |
|
|
-- Initialize Read command
|
503 |
|
|
IF Read_cmnd (0) = '1' THEN
|
504 |
|
|
Data_out_enable := '1';
|
505 |
|
|
Bank_addr := Read_bank (0);
|
506 |
|
|
Cols_addr := Read_cols (0);
|
507 |
|
|
Cols_brst := Cols_addr (2 DOWNTO 0);
|
508 |
|
|
Burst_counter := (OTHERS => '0');
|
509 |
|
|
|
510 |
|
|
-- Row address mux
|
511 |
|
|
CASE Bank_addr IS
|
512 |
|
|
WHEN "00" => Rows_addr := B0_row_addr;
|
513 |
|
|
WHEN "01" => Rows_addr := B1_row_addr;
|
514 |
|
|
WHEN "10" => Rows_addr := B2_row_addr;
|
515 |
|
|
WHEN OTHERS => Rows_addr := B3_row_addr;
|
516 |
|
|
END CASE;
|
517 |
|
|
END IF;
|
518 |
|
|
|
519 |
|
|
-- Toggle Dqs during Read command
|
520 |
|
|
IF Data_out_enable = '1' THEN
|
521 |
|
|
Dqs_int := '0';
|
522 |
|
|
IF Dqs_out = "00" THEN
|
523 |
|
|
Dqs_out <= "11";
|
524 |
|
|
ELSIF Dqs_out = "11" THEN
|
525 |
|
|
Dqs_out <= "00";
|
526 |
|
|
ELSE
|
527 |
|
|
Dqs_out <= "00";
|
528 |
|
|
END IF;
|
529 |
|
|
ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN
|
530 |
|
|
Dqs_out <= "ZZ";
|
531 |
|
|
END IF;
|
532 |
|
|
|
533 |
|
|
-- Initialize Dqs for Read command
|
534 |
|
|
IF Read_cmnd (2) = '1' THEN
|
535 |
|
|
IF Data_out_enable = '0' THEN
|
536 |
|
|
Dqs_int := '1';
|
537 |
|
|
Dqs_out <= "00";
|
538 |
|
|
END IF;
|
539 |
|
|
END IF;
|
540 |
|
|
|
541 |
|
|
-- Read Latch
|
542 |
|
|
IF Data_out_enable = '1' THEN
|
543 |
|
|
-- Initialize Memory
|
544 |
|
|
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
|
545 |
|
|
|
546 |
|
|
-- Output Data
|
547 |
|
|
CASE Bank_addr IS
|
548 |
|
|
WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
549 |
|
|
WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
550 |
|
|
WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
551 |
|
|
WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
552 |
|
|
END CASE;
|
553 |
|
|
|
554 |
|
|
-- Increase Burst Counter
|
555 |
|
|
Burst_decode;
|
556 |
|
|
ELSE
|
557 |
|
|
Dq <= (OTHERS => 'Z');
|
558 |
|
|
END IF;
|
559 |
|
|
END IF;
|
560 |
|
|
|
561 |
|
|
--
|
562 |
|
|
-- Write FIFO and DM Mask Logic
|
563 |
|
|
--
|
564 |
|
|
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
|
565 |
|
|
-- Write command pipeline
|
566 |
|
|
Write_cmnd (0) := Write_cmnd (1);
|
567 |
|
|
Write_cmnd (1) := Write_cmnd (2);
|
568 |
|
|
Write_cmnd (2) := '0';
|
569 |
|
|
|
570 |
|
|
-- Write command pipeline
|
571 |
|
|
Write_bank (0) := Write_bank (1);
|
572 |
|
|
Write_bank (1) := Write_bank (2);
|
573 |
|
|
Write_bank (2) := "00";
|
574 |
|
|
|
575 |
|
|
-- Write column pipeline
|
576 |
|
|
Write_cols (0) := Write_cols (1);
|
577 |
|
|
Write_cols (1) := Write_cols (2);
|
578 |
|
|
Write_cols (2) := (OTHERS => '0');
|
579 |
|
|
|
580 |
|
|
-- Initialize Write command
|
581 |
|
|
IF Write_cmnd (0) = '1' THEN
|
582 |
|
|
Data_in_enable := '1';
|
583 |
|
|
Bank_addr := Write_bank (0);
|
584 |
|
|
Cols_addr := Write_cols (0);
|
585 |
|
|
Cols_brst := Cols_addr (2 DOWNTO 0);
|
586 |
|
|
Burst_counter := (OTHERS => '0');
|
587 |
|
|
|
588 |
|
|
-- Row address mux
|
589 |
|
|
CASE Bank_addr IS
|
590 |
|
|
WHEN "00" => Rows_addr := B0_row_addr;
|
591 |
|
|
WHEN "01" => Rows_addr := B1_row_addr;
|
592 |
|
|
WHEN "10" => Rows_addr := B2_row_addr;
|
593 |
|
|
WHEN OTHERS => Rows_addr := B3_row_addr;
|
594 |
|
|
END CASE;
|
595 |
|
|
END IF;
|
596 |
|
|
|
597 |
|
|
-- Write data
|
598 |
|
|
IF Data_in_enable = '1' THEN
|
599 |
|
|
-- Initialize memory
|
600 |
|
|
Init_mem (Bank_addr, CONV_INTEGER(Rows_addr));
|
601 |
|
|
|
602 |
|
|
-- Write first data
|
603 |
|
|
IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN
|
604 |
|
|
-- Data Buffer
|
605 |
|
|
CASE Bank_addr IS
|
606 |
|
|
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
607 |
|
|
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
608 |
|
|
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
609 |
|
|
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
610 |
|
|
END CASE;
|
611 |
|
|
|
612 |
|
|
-- Perform DM Mask
|
613 |
|
|
IF Dm_pair (0) = '0' THEN
|
614 |
|
|
Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0);
|
615 |
|
|
END IF;
|
616 |
|
|
IF Dm_pair (1) = '0' THEN
|
617 |
|
|
Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8);
|
618 |
|
|
END IF;
|
619 |
|
|
|
620 |
|
|
-- Write Data
|
621 |
|
|
CASE Bank_addr IS
|
622 |
|
|
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
623 |
|
|
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
624 |
|
|
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
625 |
|
|
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
626 |
|
|
END CASE;
|
627 |
|
|
END IF;
|
628 |
|
|
|
629 |
|
|
-- Increase Burst Counter
|
630 |
|
|
Burst_decode;
|
631 |
|
|
|
632 |
|
|
-- Write second data
|
633 |
|
|
IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN
|
634 |
|
|
-- Data Buffer
|
635 |
|
|
CASE Bank_addr IS
|
636 |
|
|
WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
637 |
|
|
WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
638 |
|
|
WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
639 |
|
|
WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr));
|
640 |
|
|
END CASE;
|
641 |
|
|
|
642 |
|
|
-- Perform DM Mask
|
643 |
|
|
IF Dm_pair (2) = '0' THEN
|
644 |
|
|
Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16);
|
645 |
|
|
END IF;
|
646 |
|
|
IF Dm_pair (3) = '0' THEN
|
647 |
|
|
Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24);
|
648 |
|
|
END IF;
|
649 |
|
|
|
650 |
|
|
-- Write Data
|
651 |
|
|
CASE Bank_addr IS
|
652 |
|
|
WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
653 |
|
|
WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
654 |
|
|
WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
655 |
|
|
WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf;
|
656 |
|
|
END CASE;
|
657 |
|
|
END IF;
|
658 |
|
|
|
659 |
|
|
-- Increase Burst Counter
|
660 |
|
|
Burst_decode;
|
661 |
|
|
|
662 |
|
|
-- tWR start and tWTR check
|
663 |
|
|
IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN
|
664 |
|
|
CASE Bank_addr IS
|
665 |
|
|
WHEN "00" => WR_chk0 := NOW;
|
666 |
|
|
WHEN "01" => WR_chk1 := NOW;
|
667 |
|
|
WHEN "10" => WR_chk2 := NOW;
|
668 |
|
|
WHEN OTHERS => WR_chk3 := NOW;
|
669 |
|
|
END CASE;
|
670 |
|
|
|
671 |
|
|
-- tWTR check
|
672 |
|
|
ASSERT (Read_enable = '0')
|
673 |
|
|
REPORT "tWTR violation during Read"
|
674 |
|
|
SEVERITY WARNING;
|
675 |
|
|
END IF;
|
676 |
|
|
END IF;
|
677 |
|
|
END IF;
|
678 |
|
|
|
679 |
|
|
--
|
680 |
|
|
-- Auto Precharge Calculation
|
681 |
|
|
--
|
682 |
|
|
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
|
683 |
|
|
-- Precharge counter
|
684 |
|
|
IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN
|
685 |
|
|
Count_precharge (0) := Count_precharge (0) + 1;
|
686 |
|
|
END IF;
|
687 |
|
|
IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN
|
688 |
|
|
Count_precharge (1) := Count_precharge (1) + 1;
|
689 |
|
|
END IF;
|
690 |
|
|
IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN
|
691 |
|
|
Count_precharge (2) := Count_precharge (2) + 1;
|
692 |
|
|
END IF;
|
693 |
|
|
IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN
|
694 |
|
|
Count_precharge (3) := Count_precharge (3) + 1;
|
695 |
|
|
END IF;
|
696 |
|
|
|
697 |
|
|
-- Read with AutoPrecharge Calculation
|
698 |
|
|
-- The device start internal precharge when:
|
699 |
|
|
-- 1. Meet tRAS requirement
|
700 |
|
|
-- 2. BL/2 cycles after command
|
701 |
|
|
IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
|
702 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR
|
703 |
|
|
(Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR
|
704 |
|
|
(Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN
|
705 |
|
|
Pc_b0 := '1';
|
706 |
|
|
Act_b0 := '0';
|
707 |
|
|
RP_chk0 := NOW;
|
708 |
|
|
Read_precharge(0) := '0';
|
709 |
|
|
END IF;
|
710 |
|
|
END IF;
|
711 |
|
|
IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
|
712 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR
|
713 |
|
|
(Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR
|
714 |
|
|
(Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN
|
715 |
|
|
Pc_b1 := '1';
|
716 |
|
|
Act_b1 := '0';
|
717 |
|
|
RP_chk1 := NOW;
|
718 |
|
|
Read_precharge(1) := '0';
|
719 |
|
|
END IF;
|
720 |
|
|
END IF;
|
721 |
|
|
IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
|
722 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR
|
723 |
|
|
(Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR
|
724 |
|
|
(Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN
|
725 |
|
|
Pc_b2 := '1';
|
726 |
|
|
Act_b2 := '0';
|
727 |
|
|
RP_chk2 := NOW;
|
728 |
|
|
Read_precharge(2) := '0';
|
729 |
|
|
END IF;
|
730 |
|
|
END IF;
|
731 |
|
|
IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
|
732 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR
|
733 |
|
|
(Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR
|
734 |
|
|
(Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN
|
735 |
|
|
Pc_b3 := '1';
|
736 |
|
|
Act_b3 := '0';
|
737 |
|
|
RP_chk3 := NOW;
|
738 |
|
|
Read_precharge(3) := '0';
|
739 |
|
|
END IF;
|
740 |
|
|
END IF;
|
741 |
|
|
|
742 |
|
|
-- Write with AutoPrecharge Calculation
|
743 |
|
|
-- The device start internal precharge when:
|
744 |
|
|
-- 1. Meet tRAS requirement
|
745 |
|
|
-- 2. Two clock after last burst
|
746 |
|
|
-- Since tWR is time base, the model will compensate tRP
|
747 |
|
|
IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN
|
748 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR
|
749 |
|
|
(Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR
|
750 |
|
|
(Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN
|
751 |
|
|
Pc_b0 := '1';
|
752 |
|
|
Act_b0 := '0';
|
753 |
|
|
RP_chk0 := NOW - ((2 * tCK) - tWR);
|
754 |
|
|
Write_precharge(0) := '0';
|
755 |
|
|
END IF;
|
756 |
|
|
END IF;
|
757 |
|
|
IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN
|
758 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR
|
759 |
|
|
(Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR
|
760 |
|
|
(Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN
|
761 |
|
|
Pc_b1 := '1';
|
762 |
|
|
Act_b1 := '0';
|
763 |
|
|
RP_chk1 := NOW - ((2 * tCK) - tWR);
|
764 |
|
|
Write_precharge(1) := '0';
|
765 |
|
|
END IF;
|
766 |
|
|
END IF;
|
767 |
|
|
IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN
|
768 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR
|
769 |
|
|
(Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR
|
770 |
|
|
(Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN
|
771 |
|
|
Pc_b2 := '1';
|
772 |
|
|
Act_b2 := '0';
|
773 |
|
|
RP_chk2 := NOW - ((2 * tCK) - tWR);
|
774 |
|
|
Write_precharge(2) := '0';
|
775 |
|
|
END IF;
|
776 |
|
|
END IF;
|
777 |
|
|
IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN
|
778 |
|
|
IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR
|
779 |
|
|
(Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR
|
780 |
|
|
(Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN
|
781 |
|
|
Pc_b3 := '1';
|
782 |
|
|
Act_b3 := '0';
|
783 |
|
|
RP_chk3 := NOW - ((2 * tCK) - tWR);
|
784 |
|
|
Write_precharge(3) := '0';
|
785 |
|
|
END IF;
|
786 |
|
|
END IF;
|
787 |
|
|
END IF;
|
788 |
|
|
|
789 |
|
|
--
|
790 |
|
|
-- DLL Counter
|
791 |
|
|
--
|
792 |
|
|
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
|
793 |
|
|
IF (DLL_Reset = '1' AND DLL_done = '0') THEN
|
794 |
|
|
DLL_count := DLL_count + 1;
|
795 |
|
|
IF (DLL_count >= 200) THEN
|
796 |
|
|
DLL_done := '1';
|
797 |
|
|
END IF;
|
798 |
|
|
END IF;
|
799 |
|
|
END IF;
|
800 |
|
|
|
801 |
|
|
--
|
802 |
|
|
-- Control Logic
|
803 |
|
|
--
|
804 |
|
|
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
|
805 |
|
|
-- Auto Refresh
|
806 |
|
|
IF Aref_enable = '1' THEN
|
807 |
|
|
-- Auto Refresh to Auto Refresh
|
808 |
|
|
ASSERT (NOW - RFC_chk >= tRFC)
|
809 |
|
|
REPORT "tRFC violation during Auto Refresh"
|
810 |
|
|
SEVERITY WARNING;
|
811 |
|
|
|
812 |
|
|
-- Precharge to Auto Refresh
|
813 |
|
|
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
|
814 |
|
|
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
|
815 |
|
|
REPORT "tRP violation during Auto Refresh"
|
816 |
|
|
SEVERITY WARNING;
|
817 |
|
|
|
818 |
|
|
-- Precharge to Auto Refresh
|
819 |
|
|
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
|
820 |
|
|
REPORT "All banks must be Precharge before Auto Refresh"
|
821 |
|
|
SEVERITY WARNING;
|
822 |
|
|
|
823 |
|
|
-- Record current tRFC time
|
824 |
|
|
RFC_chk := NOW;
|
825 |
|
|
END IF;
|
826 |
|
|
|
827 |
|
|
-- Extended Load Mode Register
|
828 |
|
|
IF Ext_mode_enable = '1' THEN
|
829 |
|
|
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
|
830 |
|
|
IF (Addr (0) = '0') THEN
|
831 |
|
|
DLL_enable := '1';
|
832 |
|
|
ELSE
|
833 |
|
|
DLL_enable := '0';
|
834 |
|
|
END IF;
|
835 |
|
|
END IF;
|
836 |
|
|
|
837 |
|
|
-- Precharge to EMR
|
838 |
|
|
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
|
839 |
|
|
REPORT "All bank must be Precharged before Extended Mode Register"
|
840 |
|
|
SEVERITY WARNING;
|
841 |
|
|
|
842 |
|
|
-- Precharge to EMR
|
843 |
|
|
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
|
844 |
|
|
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
|
845 |
|
|
REPORT "tRP violation during Extended Load Register"
|
846 |
|
|
SEVERITY WARNING;
|
847 |
|
|
|
848 |
|
|
-- LMR/EMR to EMR
|
849 |
|
|
ASSERT (NOW - MRD_chk >= tMRD)
|
850 |
|
|
REPORT "tMRD violation during Extended Mode Register"
|
851 |
|
|
SEVERITY WARNING;
|
852 |
|
|
|
853 |
|
|
-- Record current tMRD time
|
854 |
|
|
MRD_chk := NOW;
|
855 |
|
|
END IF;
|
856 |
|
|
|
857 |
|
|
-- Load Mode Register
|
858 |
|
|
IF Mode_reg_enable = '1' THEN
|
859 |
|
|
-- Register mode
|
860 |
|
|
Mode_reg <= Addr;
|
861 |
|
|
|
862 |
|
|
-- DLL Reset
|
863 |
|
|
IF (DLL_enable = '1' AND Addr (8) = '1') THEN
|
864 |
|
|
DLL_reset := '1';
|
865 |
|
|
DLL_done := '0';
|
866 |
|
|
DLL_count := 0;
|
867 |
|
|
ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN
|
868 |
|
|
ASSERT (FALSE)
|
869 |
|
|
REPORT "DLL is ENABLE: DLL RESET is require"
|
870 |
|
|
SEVERITY WARNING;
|
871 |
|
|
ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN
|
872 |
|
|
ASSERT (FALSE)
|
873 |
|
|
REPORT "DLL is DISABLE: DLL RESET will be ignored"
|
874 |
|
|
SEVERITY WARNING;
|
875 |
|
|
END IF;
|
876 |
|
|
|
877 |
|
|
-- Precharge to LMR
|
878 |
|
|
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
|
879 |
|
|
REPORT "All bank must be Precharged before Load Mode Register"
|
880 |
|
|
SEVERITY WARNING;
|
881 |
|
|
|
882 |
|
|
-- Precharge to EMR
|
883 |
|
|
ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND
|
884 |
|
|
(NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP))
|
885 |
|
|
REPORT "tRP violation during Load Mode Register"
|
886 |
|
|
SEVERITY WARNING;
|
887 |
|
|
|
888 |
|
|
-- LMR/ELMR to LMR
|
889 |
|
|
ASSERT (NOW - MRD_chk >= tMRD)
|
890 |
|
|
REPORT "tMRD violation during Load Mode Register"
|
891 |
|
|
SEVERITY WARNING;
|
892 |
|
|
|
893 |
|
|
-- Check for invalid Burst Length
|
894 |
|
|
ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2
|
895 |
|
|
(Addr (2 DOWNTO 0) = "010") OR -- BL = 4
|
896 |
|
|
(Addr (2 DOWNTO 0) = "011")) -- BL = 8
|
897 |
|
|
REPORT "Invalid Burst Length during Load Mode Register"
|
898 |
|
|
SEVERITY WARNING;
|
899 |
|
|
|
900 |
|
|
-- Check for invalid CAS Latency
|
901 |
|
|
ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0
|
902 |
|
|
(Addr (6 DOWNTO 4) = "110")) -- CL = 2.5
|
903 |
|
|
REPORT "Invalid CAS Latency during Load Mode Register"
|
904 |
|
|
SEVERITY WARNING;
|
905 |
|
|
|
906 |
|
|
-- Record current tMRD time
|
907 |
|
|
MRD_chk := NOW;
|
908 |
|
|
END IF;
|
909 |
|
|
|
910 |
|
|
-- Active Block (latch Bank and Row Address)
|
911 |
|
|
IF Active_enable = '1' THEN
|
912 |
|
|
-- Activate an OPEN bank can corrupt data
|
913 |
|
|
ASSERT ((Ba = "00" AND Act_b0 = '0') OR
|
914 |
|
|
(Ba = "01" AND Act_b1 = '0') OR
|
915 |
|
|
(Ba = "10" AND Act_b2 = '0') OR
|
916 |
|
|
(Ba = "11" AND Act_b3 = '0'))
|
917 |
|
|
REPORT "Bank is already activated - data can be corrupted"
|
918 |
|
|
SEVERITY WARNING;
|
919 |
|
|
|
920 |
|
|
-- Activate Bank 0
|
921 |
|
|
IF Ba = "00" AND Pc_b0 = '1' THEN
|
922 |
|
|
-- Activate to Activate (same bank)
|
923 |
|
|
ASSERT (NOW - RC_chk0 >= tRC)
|
924 |
|
|
REPORT "tRC violation during Activate Bank 0"
|
925 |
|
|
SEVERITY WARNING;
|
926 |
|
|
|
927 |
|
|
-- Precharge to Active
|
928 |
|
|
ASSERT (NOW - RP_chk0 >= tRP)
|
929 |
|
|
REPORT "tRP violation during Activate Bank 0"
|
930 |
|
|
SEVERITY WARNING;
|
931 |
|
|
|
932 |
|
|
-- Record Variables for checking violation
|
933 |
|
|
Act_b0 := '1';
|
934 |
|
|
Pc_b0 := '0';
|
935 |
|
|
B0_row_addr := Addr;
|
936 |
|
|
RC_chk0 := NOW;
|
937 |
|
|
RCD_chk0 := NOW;
|
938 |
|
|
RAS_chk0 := NOW;
|
939 |
|
|
RAP_chk0 := NOW;
|
940 |
|
|
END IF;
|
941 |
|
|
|
942 |
|
|
-- Activate Bank 1
|
943 |
|
|
IF Ba = "01" AND Pc_b1 = '1' THEN
|
944 |
|
|
-- Activate to Activate (same bank)
|
945 |
|
|
ASSERT (NOW - RC_chk1 >= tRC)
|
946 |
|
|
REPORT "tRC violation during Activate Bank 1"
|
947 |
|
|
SEVERITY WARNING;
|
948 |
|
|
|
949 |
|
|
-- Precharge to Active
|
950 |
|
|
ASSERT (NOW - RP_chk1 >= tRP)
|
951 |
|
|
REPORT "tRP violation during Activate Bank 1"
|
952 |
|
|
SEVERITY WARNING;
|
953 |
|
|
|
954 |
|
|
-- Record Variables for checking violation
|
955 |
|
|
Act_b1 := '1';
|
956 |
|
|
Pc_b1 := '0';
|
957 |
|
|
B1_row_addr := Addr;
|
958 |
|
|
RC_chk1 := NOW;
|
959 |
|
|
RCD_chk1 := NOW;
|
960 |
|
|
RAS_chk1 := NOW;
|
961 |
|
|
RAP_chk1 := NOW;
|
962 |
|
|
END IF;
|
963 |
|
|
|
964 |
|
|
-- Activate Bank 2
|
965 |
|
|
IF Ba = "10" AND Pc_b2 = '1' THEN
|
966 |
|
|
-- Activate to Activate (same bank)
|
967 |
|
|
ASSERT (NOW - RC_chk2 >= tRC)
|
968 |
|
|
REPORT "tRC violation during Activate Bank 2"
|
969 |
|
|
SEVERITY WARNING;
|
970 |
|
|
|
971 |
|
|
-- Precharge to Active
|
972 |
|
|
ASSERT (NOW - RP_chk2 >= tRP)
|
973 |
|
|
REPORT "tRP violation during Activate Bank 2"
|
974 |
|
|
SEVERITY WARNING;
|
975 |
|
|
|
976 |
|
|
-- Record Variables for checking violation
|
977 |
|
|
Act_b2 := '1';
|
978 |
|
|
Pc_b2 := '0';
|
979 |
|
|
B2_row_addr := Addr;
|
980 |
|
|
RC_chk2 := NOW;
|
981 |
|
|
RCD_chk2 := NOW;
|
982 |
|
|
RAS_chk2 := NOW;
|
983 |
|
|
RAP_chk2 := NOW;
|
984 |
|
|
END IF;
|
985 |
|
|
|
986 |
|
|
-- Activate Bank 3
|
987 |
|
|
IF Ba = "11" AND Pc_b3 = '1' THEN
|
988 |
|
|
-- Activate to Activate (same bank)
|
989 |
|
|
ASSERT (NOW - RC_chk3 >= tRC)
|
990 |
|
|
REPORT "tRC violation during Activate Bank 3"
|
991 |
|
|
SEVERITY WARNING;
|
992 |
|
|
|
993 |
|
|
-- Precharge to Active
|
994 |
|
|
ASSERT (NOW - RP_chk3 >= tRP)
|
995 |
|
|
REPORT "tRP violation during Activate Bank 3"
|
996 |
|
|
SEVERITY WARNING;
|
997 |
|
|
|
998 |
|
|
-- Record Variables for checking violation
|
999 |
|
|
Act_b3 := '1';
|
1000 |
|
|
Pc_b3 := '0';
|
1001 |
|
|
B3_row_addr := Addr;
|
1002 |
|
|
RC_chk3 := NOW;
|
1003 |
|
|
RCD_chk3 := NOW;
|
1004 |
|
|
RAS_chk3 := NOW;
|
1005 |
|
|
RAP_chk3 := NOW;
|
1006 |
|
|
END IF;
|
1007 |
|
|
|
1008 |
|
|
-- Activate Bank A to Activate Bank B
|
1009 |
|
|
IF (Prev_bank /= Ba) THEN
|
1010 |
|
|
ASSERT (NOW - RRD_chk >= tRRD)
|
1011 |
|
|
REPORT "tRRD violation during Activate"
|
1012 |
|
|
SEVERITY WARNING;
|
1013 |
|
|
END IF;
|
1014 |
|
|
|
1015 |
|
|
-- AutoRefresh to Activate
|
1016 |
|
|
ASSERT (NOW - RFC_chk >= tRFC)
|
1017 |
|
|
REPORT "tRFC violation during Activate"
|
1018 |
|
|
SEVERITY WARNING;
|
1019 |
|
|
|
1020 |
|
|
-- Record Variables for Checking Violation
|
1021 |
|
|
RRD_chk := NOW;
|
1022 |
|
|
Prev_bank := Ba;
|
1023 |
|
|
END IF;
|
1024 |
|
|
|
1025 |
|
|
-- Precharge Block - Consider NOP if bank already precharged or in process of precharging
|
1026 |
|
|
IF Prech_enable = '1' THEN
|
1027 |
|
|
-- EMR or LMR to Precharge
|
1028 |
|
|
ASSERT (NOW - MRD_chk >= tMRD)
|
1029 |
|
|
REPORT "tMRD violation during Precharge"
|
1030 |
|
|
SEVERITY WARNING;
|
1031 |
|
|
|
1032 |
|
|
-- Precharge Bank 0
|
1033 |
|
|
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN
|
1034 |
|
|
Act_b0 := '0';
|
1035 |
|
|
Pc_b0 := '1';
|
1036 |
|
|
RP_chk0 := NOW;
|
1037 |
|
|
|
1038 |
|
|
-- Activate to Precharge bank 0
|
1039 |
|
|
ASSERT (NOW - RAS_chk0 >= tRAS)
|
1040 |
|
|
REPORT "tRAS violation during Precharge"
|
1041 |
|
|
SEVERITY WARNING;
|
1042 |
|
|
|
1043 |
|
|
-- tWR violation check for Write
|
1044 |
|
|
ASSERT (NOW - WR_chk0 >= tWR)
|
1045 |
|
|
REPORT "tWR violation during Precharge"
|
1046 |
|
|
SEVERITY WARNING;
|
1047 |
|
|
END IF;
|
1048 |
|
|
|
1049 |
|
|
-- Precharge Bank 1
|
1050 |
|
|
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN
|
1051 |
|
|
Act_b1 := '0';
|
1052 |
|
|
Pc_b1 := '1';
|
1053 |
|
|
RP_chk1 := NOW;
|
1054 |
|
|
|
1055 |
|
|
-- Activate to Precharge
|
1056 |
|
|
ASSERT (NOW - RAS_chk1 >= tRAS)
|
1057 |
|
|
REPORT "tRAS violation during Precharge"
|
1058 |
|
|
SEVERITY WARNING;
|
1059 |
|
|
|
1060 |
|
|
-- tWR violation check for Write
|
1061 |
|
|
ASSERT (NOW - WR_chk1 >= tWR)
|
1062 |
|
|
REPORT "tWR violation during Precharge"
|
1063 |
|
|
SEVERITY WARNING;
|
1064 |
|
|
END IF;
|
1065 |
|
|
|
1066 |
|
|
-- Precharge Bank 2
|
1067 |
|
|
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN
|
1068 |
|
|
Act_b2 := '0';
|
1069 |
|
|
Pc_b2 := '1';
|
1070 |
|
|
RP_chk2 := NOW;
|
1071 |
|
|
|
1072 |
|
|
-- Activate to Precharge
|
1073 |
|
|
ASSERT (NOW - RAS_chk2 >= tRAS)
|
1074 |
|
|
REPORT "tRAS violation during Precharge"
|
1075 |
|
|
SEVERITY WARNING;
|
1076 |
|
|
|
1077 |
|
|
-- tWR violation check for Write
|
1078 |
|
|
ASSERT (NOW - WR_chk2 >= tWR)
|
1079 |
|
|
REPORT "tWR violation during Precharge"
|
1080 |
|
|
SEVERITY WARNING;
|
1081 |
|
|
END IF;
|
1082 |
|
|
|
1083 |
|
|
-- Precharge Bank 3
|
1084 |
|
|
IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN
|
1085 |
|
|
Act_b3 := '0';
|
1086 |
|
|
Pc_b3 := '1';
|
1087 |
|
|
RP_chk3 := NOW;
|
1088 |
|
|
|
1089 |
|
|
-- Activate to Precharge
|
1090 |
|
|
ASSERT (NOW - RAS_chk3 >= tRAS)
|
1091 |
|
|
REPORT "tRAS violation during Precharge"
|
1092 |
|
|
SEVERITY WARNING;
|
1093 |
|
|
|
1094 |
|
|
-- tWR violation check for Write
|
1095 |
|
|
ASSERT (NOW - WR_chk3 >= tWR)
|
1096 |
|
|
REPORT "tWR violation during Precharge"
|
1097 |
|
|
SEVERITY WARNING;
|
1098 |
|
|
END IF;
|
1099 |
|
|
|
1100 |
|
|
-- Pipeline for READ
|
1101 |
|
|
IF CAS_latency_15 = '1' THEN
|
1102 |
|
|
A10_precharge (3) := Addr(10);
|
1103 |
|
|
Bank_precharge (3) := Ba;
|
1104 |
|
|
Cmnd_precharge (3) := '1';
|
1105 |
|
|
ELSIF CAS_latency_2 = '1' THEN
|
1106 |
|
|
A10_precharge (4) := Addr(10);
|
1107 |
|
|
Bank_precharge (4) := Ba;
|
1108 |
|
|
Cmnd_precharge (4) := '1';
|
1109 |
|
|
ELSIF CAS_latency_25 = '1' THEN
|
1110 |
|
|
A10_precharge (5) := Addr(10);
|
1111 |
|
|
Bank_precharge (5) := Ba;
|
1112 |
|
|
Cmnd_precharge (5) := '1';
|
1113 |
|
|
ELSIF CAS_latency_3 = '1' THEN
|
1114 |
|
|
A10_precharge (6) := Addr(10);
|
1115 |
|
|
Bank_precharge (6) := Ba;
|
1116 |
|
|
Cmnd_precharge (6) := '1';
|
1117 |
|
|
ELSIF CAS_latency_4 = '1' THEN
|
1118 |
|
|
A10_precharge (8) := Addr(10);
|
1119 |
|
|
Bank_precharge (8) := Ba;
|
1120 |
|
|
Cmnd_precharge (8) := '1';
|
1121 |
|
|
END IF;
|
1122 |
|
|
END IF;
|
1123 |
|
|
|
1124 |
|
|
-- Burst Terminate
|
1125 |
|
|
IF Burst_term = '1' THEN
|
1126 |
|
|
-- Pipeline for Read
|
1127 |
|
|
IF CAS_latency_15 = '1' THEN
|
1128 |
|
|
Cmnd_bst (3) := '1';
|
1129 |
|
|
ELSIF CAS_latency_2 = '1' THEN
|
1130 |
|
|
Cmnd_bst (4) := '1';
|
1131 |
|
|
ELSIF CAS_latency_25 = '1' THEN
|
1132 |
|
|
Cmnd_bst (5) := '1';
|
1133 |
|
|
ELSIF CAS_latency_3 = '1' THEN
|
1134 |
|
|
Cmnd_bst (6) := '1';
|
1135 |
|
|
ELSIF CAS_latency_4 = '1' THEN
|
1136 |
|
|
Cmnd_bst (8) := '1';
|
1137 |
|
|
END IF;
|
1138 |
|
|
|
1139 |
|
|
-- Terminate Write
|
1140 |
|
|
ASSERT (Data_in_enable = '0')
|
1141 |
|
|
REPORT "It's illegal to Burst Terminate a Write"
|
1142 |
|
|
SEVERITY WARNING;
|
1143 |
|
|
|
1144 |
|
|
-- Terminate Read with Auto Precharge
|
1145 |
|
|
ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND
|
1146 |
|
|
Read_precharge (2) = '0' AND Read_precharge (3) = '0')
|
1147 |
|
|
REPORT "It's illegal to Burst Terminate a Read with Auto Precharge"
|
1148 |
|
|
SEVERITY WARNING;
|
1149 |
|
|
END IF;
|
1150 |
|
|
|
1151 |
|
|
-- Read Command
|
1152 |
|
|
IF Read_enable = '1' THEN
|
1153 |
|
|
-- CAS Latency Pipeline
|
1154 |
|
|
IF Cas_latency_15 = '1' THEN
|
1155 |
|
|
Read_cmnd (3) := '1';
|
1156 |
|
|
Read_bank (3) := Ba;
|
1157 |
|
|
Read_cols (3) := Addr (8 DOWNTO 0);
|
1158 |
|
|
ELSIF Cas_latency_2 = '1' THEN
|
1159 |
|
|
Read_cmnd (4) := '1';
|
1160 |
|
|
Read_bank (4) := Ba;
|
1161 |
|
|
Read_cols (4) := Addr (8 DOWNTO 0);
|
1162 |
|
|
ELSIF Cas_latency_25 = '1' THEN
|
1163 |
|
|
Read_cmnd (5) := '1';
|
1164 |
|
|
Read_bank (5) := Ba;
|
1165 |
|
|
Read_cols (5) := Addr (8 DOWNTO 0);
|
1166 |
|
|
ELSIF Cas_latency_3 = '1' THEN
|
1167 |
|
|
Read_cmnd (6) := '1';
|
1168 |
|
|
Read_bank (6) := Ba;
|
1169 |
|
|
Read_cols (6) := Addr (8 DOWNTO 0);
|
1170 |
|
|
ELSIF Cas_latency_4 = '1' THEN
|
1171 |
|
|
Read_cmnd (8) := '1';
|
1172 |
|
|
Read_bank (8) := Ba;
|
1173 |
|
|
Read_cols (8) := Addr (8 DOWNTO 0);
|
1174 |
|
|
END IF;
|
1175 |
|
|
|
1176 |
|
|
-- Write to Read: Terminate Write Immediately
|
1177 |
|
|
IF Data_in_enable = '1' THEN
|
1178 |
|
|
Data_in_enable := '0';
|
1179 |
|
|
END IF;
|
1180 |
|
|
|
1181 |
|
|
-- Interrupting a Read with Auto Precharge (same bank only)
|
1182 |
|
|
ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0')
|
1183 |
|
|
REPORT "It's illegal to interrupt a Read with Auto Precharge"
|
1184 |
|
|
SEVERITY WARNING;
|
1185 |
|
|
|
1186 |
|
|
-- Activate to Read
|
1187 |
|
|
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
|
1188 |
|
|
(Ba = "01" AND Act_b1 = '1') OR
|
1189 |
|
|
(Ba = "10" AND Act_b2 = '1') OR
|
1190 |
|
|
(Ba = "11" AND Act_b3 = '1'))
|
1191 |
|
|
REPORT "Bank is not Activated for Read"
|
1192 |
|
|
SEVERITY WARNING;
|
1193 |
|
|
|
1194 |
|
|
-- Activate to Read without Auto Precharge
|
1195 |
|
|
IF Addr (10) = '0' THEN
|
1196 |
|
|
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
|
1197 |
|
|
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
|
1198 |
|
|
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
|
1199 |
|
|
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
|
1200 |
|
|
REPORT "tRCD violation during Read"
|
1201 |
|
|
SEVERITY WARNING;
|
1202 |
|
|
END IF;
|
1203 |
|
|
|
1204 |
|
|
-- Activate to Read with Auto Precharge
|
1205 |
|
|
IF Addr (10) = '1' THEN
|
1206 |
|
|
ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR
|
1207 |
|
|
(Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR
|
1208 |
|
|
(Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR
|
1209 |
|
|
(Ba = "11" AND NOW - RAP_chk3 >= tRAP))
|
1210 |
|
|
REPORT "tRAP violation during Read"
|
1211 |
|
|
SEVERITY WARNING;
|
1212 |
|
|
END IF;
|
1213 |
|
|
|
1214 |
|
|
-- Auto precharge
|
1215 |
|
|
IF Addr (10) = '1' THEN
|
1216 |
|
|
Read_precharge (Conv_INTEGER(Ba)) := '1';
|
1217 |
|
|
Count_precharge (Conv_INTEGER(Ba)) := 0;
|
1218 |
|
|
END IF;
|
1219 |
|
|
|
1220 |
|
|
-- DLL Check
|
1221 |
|
|
IF (DLL_reset = '1') THEN
|
1222 |
|
|
ASSERT (DLL_done = '1')
|
1223 |
|
|
REPORT "DLL RESET not complete"
|
1224 |
|
|
SEVERITY WARNING;
|
1225 |
|
|
END IF;
|
1226 |
|
|
END IF;
|
1227 |
|
|
|
1228 |
|
|
-- Write Command
|
1229 |
|
|
IF Write_enable = '1' THEN
|
1230 |
|
|
-- Pipeline for Write
|
1231 |
|
|
Write_cmnd (2) := '1';
|
1232 |
|
|
Write_bank (2) := Ba;
|
1233 |
|
|
Write_cols (2) := Addr (8 DOWNTO 0);
|
1234 |
|
|
|
1235 |
|
|
-- Interrupting a Write with Auto Precharge (same bank only)
|
1236 |
|
|
ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0')
|
1237 |
|
|
REPORT "It's illegal to interrupt a Write with Auto Precharge"
|
1238 |
|
|
SEVERITY WARNING;
|
1239 |
|
|
|
1240 |
|
|
-- Activate to Write
|
1241 |
|
|
ASSERT ((Ba = "00" AND Act_b0 = '1') OR
|
1242 |
|
|
(Ba = "01" AND Act_b1 = '1') OR
|
1243 |
|
|
(Ba = "10" AND Act_b2 = '1') OR
|
1244 |
|
|
(Ba = "11" AND Act_b3 = '1'))
|
1245 |
|
|
REPORT "Bank is not Activated for Write"
|
1246 |
|
|
SEVERITY WARNING;
|
1247 |
|
|
|
1248 |
|
|
-- Activate to Write
|
1249 |
|
|
ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR
|
1250 |
|
|
(Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR
|
1251 |
|
|
(Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR
|
1252 |
|
|
(Ba = "11" AND NOW - RCD_chk3 >= tRCD))
|
1253 |
|
|
REPORT "tRCD violation during Write"
|
1254 |
|
|
SEVERITY WARNING;
|
1255 |
|
|
|
1256 |
|
|
-- Auto precharge
|
1257 |
|
|
IF Addr (10) = '1' THEN
|
1258 |
|
|
Write_precharge (Conv_INTEGER(Ba)) := '1';
|
1259 |
|
|
Count_precharge (Conv_INTEGER(Ba)) := 0;
|
1260 |
|
|
END IF;
|
1261 |
|
|
END IF;
|
1262 |
|
|
END IF;
|
1263 |
|
|
|
1264 |
|
|
IF not file_loaded THEN --'
|
1265 |
|
|
file_loaded := true;
|
1266 |
|
|
WHILE NOT endfile(file_load) LOOP
|
1267 |
|
|
readline(file_load, l);
|
1268 |
|
|
read(l, ch);
|
1269 |
|
|
if (ch /= 'S') or (ch /= 's') then
|
1270 |
|
|
hexread(l, rectype);
|
1271 |
|
|
hexread(l, reclen);
|
1272 |
|
|
recaddr := (others => '0');
|
1273 |
|
|
case rectype is
|
1274 |
|
|
when "0001" =>
|
1275 |
|
|
hexread(l, recaddr(15 downto 0));
|
1276 |
|
|
when "0010" =>
|
1277 |
|
|
hexread(l, recaddr(23 downto 0));
|
1278 |
|
|
when "0011" =>
|
1279 |
|
|
hexread(l, recaddr);
|
1280 |
|
|
when "0111" =>
|
1281 |
|
|
hexread(l, recaddr);
|
1282 |
|
|
-- if (index = 0) then print("Start address : " & tost(recaddr)); end if;
|
1283 |
|
|
next;
|
1284 |
|
|
when others => next;
|
1285 |
|
|
end case;
|
1286 |
|
|
case bbits is
|
1287 |
|
|
when 64 => -- 64-bit bank with four 16-bit DDRs
|
1288 |
|
|
recaddr(31 downto 27) := (others => '0');
|
1289 |
|
|
hexread(l, recdata);
|
1290 |
|
|
Bank_Load := recaddr(26 downto 25);
|
1291 |
|
|
Rows_Load := recaddr(24 downto 12);
|
1292 |
|
|
Cols_Load := recaddr(11 downto 3);
|
1293 |
|
|
Init_mem (Bank_Load, To_Integer(Rows_Load));
|
1294 |
|
|
IF Bank_Load = "00" THEN
|
1295 |
|
|
for i in 0 to 1 loop
|
1296 |
|
|
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
|
1297 |
|
|
end loop;
|
1298 |
|
|
ELSIF Bank_Load = "01" THEN
|
1299 |
|
|
for i in 0 to 3 loop
|
1300 |
|
|
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
|
1301 |
|
|
end loop;
|
1302 |
|
|
ELSIF Bank_Load = "10" THEN
|
1303 |
|
|
for i in 0 to 3 loop
|
1304 |
|
|
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
|
1305 |
|
|
end loop;
|
1306 |
|
|
ELSIF Bank_Load = "11" THEN
|
1307 |
|
|
for i in 0 to 3 loop
|
1308 |
|
|
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15));
|
1309 |
|
|
end loop;
|
1310 |
|
|
END IF;
|
1311 |
|
|
|
1312 |
|
|
when 32 => -- 32-bit bank with two 16-bit DDRs
|
1313 |
|
|
recaddr(31 downto 26) := (others => '0');
|
1314 |
|
|
hexread(l, recdata);
|
1315 |
|
|
Bank_Load := recaddr(25 downto 24);
|
1316 |
|
|
Rows_Load := recaddr(23 downto 11);
|
1317 |
|
|
Cols_Load := recaddr(10 downto 2);
|
1318 |
|
|
Init_mem (Bank_Load, To_Integer(Rows_Load));
|
1319 |
|
|
|
1320 |
|
|
IF Bank_Load = "00" THEN
|
1321 |
|
|
for i in 0 to 3 loop
|
1322 |
|
|
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
|
1323 |
|
|
end loop;
|
1324 |
|
|
ELSIF Bank_Load = "01" THEN
|
1325 |
|
|
for i in 0 to 3 loop
|
1326 |
|
|
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
|
1327 |
|
|
end loop;
|
1328 |
|
|
ELSIF Bank_Load = "10" THEN
|
1329 |
|
|
for i in 0 to 3 loop
|
1330 |
|
|
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
|
1331 |
|
|
end loop;
|
1332 |
|
|
ELSIF Bank_Load = "11" THEN
|
1333 |
|
|
for i in 0 to 3 loop
|
1334 |
|
|
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15));
|
1335 |
|
|
end loop;
|
1336 |
|
|
END IF;
|
1337 |
|
|
|
1338 |
|
|
when others => -- 16-bit bank with one 16-bit DDR
|
1339 |
|
|
hexread(l, recdata);
|
1340 |
|
|
recaddr(31 downto 25) := (others => '0');
|
1341 |
|
|
Bank_Load := recaddr(24 downto 23);
|
1342 |
|
|
Rows_Load := recaddr(22 downto 10);
|
1343 |
|
|
Cols_Load := recaddr(9 downto 1);
|
1344 |
|
|
Init_mem (Bank_Load, To_Integer(Rows_Load));
|
1345 |
|
|
|
1346 |
|
|
IF Bank_Load = "00" THEN
|
1347 |
|
|
for i in 0 to 3 loop
|
1348 |
|
|
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
|
1349 |
|
|
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
|
1350 |
|
|
end loop;
|
1351 |
|
|
ELSIF Bank_Load = "01" THEN
|
1352 |
|
|
for i in 0 to 3 loop
|
1353 |
|
|
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
|
1354 |
|
|
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
|
1355 |
|
|
end loop;
|
1356 |
|
|
ELSIF Bank_Load = "10" THEN
|
1357 |
|
|
for i in 0 to 3 loop
|
1358 |
|
|
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
|
1359 |
|
|
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
|
1360 |
|
|
end loop;
|
1361 |
|
|
ELSIF Bank_Load = "11" THEN
|
1362 |
|
|
for i in 0 to 3 loop
|
1363 |
|
|
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15));
|
1364 |
|
|
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15));
|
1365 |
|
|
end loop;
|
1366 |
|
|
END IF;
|
1367 |
|
|
|
1368 |
|
|
END case;
|
1369 |
|
|
END IF;
|
1370 |
|
|
END LOOP;
|
1371 |
|
|
END IF;
|
1372 |
|
|
|
1373 |
|
|
END PROCESS;
|
1374 |
|
|
|
1375 |
|
|
--
|
1376 |
|
|
-- Dqs Receiver
|
1377 |
|
|
--
|
1378 |
|
|
dqs_rcvrs : PROCESS
|
1379 |
|
|
VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
1380 |
|
|
VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
|
1381 |
|
|
BEGIN
|
1382 |
|
|
WAIT ON Dqs;
|
1383 |
|
|
-- Latch data at posedge Dqs
|
1384 |
|
|
IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN
|
1385 |
|
|
Dq_temp := Dq;
|
1386 |
|
|
Dm_temp := Dm;
|
1387 |
|
|
END IF;
|
1388 |
|
|
-- Latch data at negedge Dqs
|
1389 |
|
|
IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN
|
1390 |
|
|
Dq_pair <= (Dq & Dq_temp);
|
1391 |
|
|
Dm_pair <= (Dm & Dm_temp);
|
1392 |
|
|
END IF;
|
1393 |
|
|
END PROCESS;
|
1394 |
|
|
|
1395 |
|
|
--
|
1396 |
|
|
-- Setup timing checks
|
1397 |
|
|
--
|
1398 |
|
|
Setup_check : PROCESS
|
1399 |
|
|
BEGIN
|
1400 |
|
|
WAIT ON Sys_clk;
|
1401 |
|
|
IF Sys_clk'EVENT AND Sys_clk = '1' THEN
|
1402 |
|
|
ASSERT(Cke'LAST_EVENT >= tIS)
|
1403 |
|
|
REPORT "CKE Setup time violation -- tIS"
|
1404 |
|
|
SEVERITY WARNING;
|
1405 |
|
|
ASSERT(Cs_n'LAST_EVENT >= tIS)
|
1406 |
|
|
REPORT "CS# Setup time violation -- tIS"
|
1407 |
|
|
SEVERITY WARNING;
|
1408 |
|
|
ASSERT(Cas_n'LAST_EVENT >= tIS)
|
1409 |
|
|
REPORT "CAS# Setup time violation -- tIS"
|
1410 |
|
|
SEVERITY WARNING;
|
1411 |
|
|
ASSERT(Ras_n'LAST_EVENT >= tIS)
|
1412 |
|
|
REPORT "RAS# Setup time violation -- tIS"
|
1413 |
|
|
SEVERITY WARNING;
|
1414 |
|
|
ASSERT(We_n'LAST_EVENT >= tIS)
|
1415 |
|
|
REPORT "WE# Setup time violation -- tIS"
|
1416 |
|
|
SEVERITY WARNING;
|
1417 |
|
|
ASSERT(Addr'LAST_EVENT >= tIS)
|
1418 |
|
|
REPORT "ADDR Setup time violation -- tIS"
|
1419 |
|
|
SEVERITY WARNING;
|
1420 |
|
|
ASSERT(Ba'LAST_EVENT >= tIS)
|
1421 |
|
|
REPORT "BA Setup time violation -- tIS"
|
1422 |
|
|
SEVERITY WARNING;
|
1423 |
|
|
END IF;
|
1424 |
|
|
END PROCESS;
|
1425 |
|
|
|
1426 |
|
|
--
|
1427 |
|
|
-- Hold timing checks
|
1428 |
|
|
--
|
1429 |
|
|
Hold_check : PROCESS
|
1430 |
|
|
BEGIN
|
1431 |
|
|
WAIT ON Sys_clk'DELAYED (tIH);
|
1432 |
|
|
IF Sys_clk'DELAYED (tIH) = '1' THEN
|
1433 |
|
|
ASSERT(Cke'LAST_EVENT >= tIH)
|
1434 |
|
|
REPORT "CKE Hold time violation -- tIH"
|
1435 |
|
|
SEVERITY WARNING;
|
1436 |
|
|
ASSERT(Cs_n'LAST_EVENT >= tIH)
|
1437 |
|
|
REPORT "CS# Hold time violation -- tIH"
|
1438 |
|
|
SEVERITY WARNING;
|
1439 |
|
|
ASSERT(Cas_n'LAST_EVENT >= tIH)
|
1440 |
|
|
REPORT "CAS# Hold time violation -- tIH"
|
1441 |
|
|
SEVERITY WARNING;
|
1442 |
|
|
ASSERT(Ras_n'LAST_EVENT >= tIH)
|
1443 |
|
|
REPORT "RAS# Hold time violation -- tIH"
|
1444 |
|
|
SEVERITY WARNING;
|
1445 |
|
|
ASSERT(We_n'LAST_EVENT >= tIH)
|
1446 |
|
|
REPORT "WE# Hold time violation -- tIH"
|
1447 |
|
|
SEVERITY WARNING;
|
1448 |
|
|
ASSERT(Addr'LAST_EVENT >= tIH)
|
1449 |
|
|
REPORT "ADDR Hold time violation -- tIH"
|
1450 |
|
|
SEVERITY WARNING;
|
1451 |
|
|
ASSERT(Ba'LAST_EVENT >= tIH)
|
1452 |
|
|
REPORT "BA Hold time violation -- tIH"
|
1453 |
|
|
SEVERITY WARNING;
|
1454 |
|
|
END IF;
|
1455 |
|
|
END PROCESS;
|
1456 |
|
|
|
1457 |
|
|
END behave;
|