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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [micron/] [sdram/] [components.vhd] - Blame information for rev 2

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1 2 dimamali 
----------------------------------------------------------------------------
2 
--  This file is a part of the GRLIB VHDL IP LIBRARY
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--  Copyright (C) 2004 GAISLER RESEARCH
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--
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--  This program is free software; you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation; either version 2 of the License, or
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--  (at your option) any later version.
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--
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--  See the file COPYING for the full details of the license.
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--
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-----------------------------------------------------------------------------
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-- Package:     components
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-- File:        components.vhd
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-- Author:      Jiri Gaisler, Gaisler Research
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-- Description: Component declaration of Micron SDRAM
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------------------------------------------------------------------------------
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-- pragma translate_off
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21 
library ieee;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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package components is
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  component mt48lc16m16a2
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    GENERIC (
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        -- Timing Parameters for -75 (PC133) and CAS Latency = 2
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        tAC       : TIME    :=  6.0 ns;
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        tHZ       : TIME    :=  7.0 ns;
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        tOH       : TIME    :=  2.7 ns;
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        tMRD      : INTEGER :=  2;          -- 2 Clk Cycles
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        tRAS      : TIME    := 44.0 ns;
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        tRC       : TIME    := 66.0 ns;
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        tRCD      : TIME    := 20.0 ns;
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        tRP       : TIME    := 20.0 ns;
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        tRRD      : TIME    := 15.0 ns;
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        tWRa      : TIME    :=  7.5 ns;     -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
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        tWRp      : TIME    := 15.0 ns;     -- A2 Version - Precharge mode only (15 ns)
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        tAH       : TIME    :=  0.8 ns;
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        tAS       : TIME    :=  1.5 ns;
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        tCH       : TIME    :=  2.5 ns;
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        tCL       : TIME    :=  2.5 ns;
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        tCK       : TIME    := 10.0 ns;
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        tDH       : TIME    :=  0.8 ns;
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        tDS       : TIME    :=  1.5 ns;
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        tCKH      : TIME    :=  0.8 ns;
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        tCKS      : TIME    :=  1.5 ns;
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        tCMH      : TIME    :=  0.8 ns;
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        tCMS      : TIME    :=  1.5 ns;
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        addr_bits : INTEGER := 13;
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        data_bits : INTEGER := 16;
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        col_bits  : INTEGER :=  9;
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        index     : INTEGER :=  0;
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        fname     : string := "sdram.srec"      -- File to read from
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    );
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    PORT (
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        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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        Ba    : IN    STD_LOGIC_VECTOR := "00";
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        Clk   : IN    STD_LOGIC := '0';
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        Cke   : IN    STD_LOGIC := '1';
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        Cs_n  : IN    STD_LOGIC := '1';
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        Ras_n : IN    STD_LOGIC := '1';
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        Cas_n : IN    STD_LOGIC := '1';
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        We_n  : IN    STD_LOGIC := '1';
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        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
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    );
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  end component;
73 
 
74 
  component mt46v16m16
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    GENERIC (                                   -- Timing for -75Z CL2
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        tCK       : TIME    :=  7.500 ns;
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        tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
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        tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
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        tDH       : TIME    :=  0.500 ns;
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        tDS       : TIME    :=  0.500 ns;
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        tIH       : TIME    :=  0.900 ns;
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        tIS       : TIME    :=  0.900 ns;
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        tMRD      : TIME    := 15.000 ns;
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        tRAS      : TIME    := 40.000 ns;
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        tRAP      : TIME    := 20.000 ns;
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        tRC       : TIME    := 65.000 ns;
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        tRFC      : TIME    := 75.000 ns;
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        tRCD      : TIME    := 20.000 ns;
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        tRP       : TIME    := 20.000 ns;
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        tRRD      : TIME    := 15.000 ns;
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        tWR       : TIME    := 15.000 ns;
92 
        addr_bits : INTEGER := 13;
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        data_bits : INTEGER := 16;
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        cols_bits : INTEGER :=  9;
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        index     : INTEGER :=  0;
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        fname     : string := "sdram.srec";     -- File to read from
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        bbits     : INTEGER :=  16
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    );
99 
    PORT (
100 
        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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        Dqs   : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
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        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
103 
        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
104 
        Clk   : IN    STD_LOGIC;
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        Clk_n : IN    STD_LOGIC;
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        Cke   : IN    STD_LOGIC;
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        Cs_n  : IN    STD_LOGIC;
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        Ras_n : IN    STD_LOGIC;
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        Cas_n : IN    STD_LOGIC;
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        We_n  : IN    STD_LOGIC;
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        Dm    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0)
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    );
113 
  END component;
114 
 
115 
  component ftmt48lc16m16a2
116 
    GENERIC (
117 
        -- Timing Parameters for -75 (PC133) and CAS Latency = 2
118 
        tAC       : TIME    :=  6.0 ns;
119 
        tHZ       : TIME    :=  7.0 ns;
120 
        tOH       : TIME    :=  2.7 ns;
121 
        tMRD      : INTEGER :=  2;          -- 2 Clk Cycles
122 
        tRAS      : TIME    := 44.0 ns;
123 
        tRC       : TIME    := 66.0 ns;
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        tRCD      : TIME    := 20.0 ns;
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        tRP       : TIME    := 20.0 ns;
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        tRRD      : TIME    := 15.0 ns;
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        tWRa      : TIME    :=  7.5 ns;     -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
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        tWRp      : TIME    := 15.0 ns;     -- A2 Version - Precharge mode only (15 ns)
129 
 
130 
        tAH       : TIME    :=  0.8 ns;
131 
        tAS       : TIME    :=  1.5 ns;
132 
        tCH       : TIME    :=  2.5 ns;
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        tCL       : TIME    :=  2.5 ns;
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        tCK       : TIME    := 10.0 ns;
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        tDH       : TIME    :=  0.8 ns;
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        tDS       : TIME    :=  1.5 ns;
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        tCKH      : TIME    :=  0.8 ns;
138 
        tCKS      : TIME    :=  1.5 ns;
139 
        tCMH      : TIME    :=  0.8 ns;
140 
        tCMS      : TIME    :=  1.5 ns;
141 
 
142 
        addr_bits : INTEGER := 13;
143 
        data_bits : INTEGER := 16;
144 
        col_bits  : INTEGER :=  9;
145 
        index     : INTEGER :=  0;
146 
        fname     : string := "sdram.srec"      -- File to read from
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    );
148 
    PORT (
149 
        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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        Ba    : IN    STD_LOGIC_VECTOR := "00";
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        Clk   : IN    STD_LOGIC := '0';
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        Cke   : IN    STD_LOGIC := '1';
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        Cs_n  : IN    STD_LOGIC := '1';
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        Ras_n : IN    STD_LOGIC := '1';
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        Cas_n : IN    STD_LOGIC := '1';
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        We_n  : IN    STD_LOGIC := '1';
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        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
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    );
160 
  end component;
161 
 
162 
  component ddr2 is
163 
  generic(
164 
    DM_BITS : integer := 2;
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    ADDR_BITS : integer := 13;
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    ROW_BITS : integer := 13;
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    COL_BITS : integer := 9;
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    DQ_BITS : integer := 16;
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    DQS_BITS : integer := 2;
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    TRRD : integer := 10000;
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    TFAW : integer := 50000;
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    DEBUG   : integer := 1
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  );
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  port (
175 
    ck      : in std_ulogic;
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    ck_n    : in std_ulogic;
177 
    cke     : in std_ulogic;
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    cs_n    : in std_ulogic;
179 
    ras_n   : in std_ulogic;
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    cas_n   : in std_ulogic;
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    we_n    : in std_ulogic;
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    dm_rdqs : inout std_logic_vector(DQS_BITS-1 downto 0);
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    ba      : in std_logic_vector(1 downto 0);
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    addr    : in std_logic_vector(ADDR_BITS-1 downto 0);
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    dq      : inout std_logic_vector(DQ_BITS-1 downto 0);
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    dqs     : inout std_logic_vector(DQS_BITS-1 downto 0);
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    dqs_n   : inout std_logic_vector(DQS_BITS-1 downto 0);
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    rdqs_n  : out std_logic_vector(DQS_BITS-1 downto 0);
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    odt     : in std_ulogic
190 
  );
191 
  end component;
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193 
  component mobile_ddr
194 
    GENERIC (                                   -- Timing for -75Z CL2
195 
    --    tCK       : TIME    :=  7.500 ns;
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    --    tCH       : TIME    :=  3.375 ns;       -- 0.45*tCK
197 
    --    tCL       : TIME    :=  3.375 ns;       -- 0.45*tCK
198 
    --    tDH       : TIME    :=  0.500 ns;
199 
    --    tDS       : TIME    :=  0.500 ns;
200 
    --    tIH       : TIME    :=  0.900 ns;
201 
    --    tIS       : TIME    :=  0.900 ns;
202 
    --    tMRD      : TIME    := 15.000 ns;
203 
    --    tRAS      : TIME    := 40.000 ns;
204 
    --    tRAP      : TIME    := 20.000 ns;
205 
    --    tRC       : TIME    := 65.000 ns;
206 
    --    tRFC      : TIME    := 75.000 ns;
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    --    tRCD      : TIME    := 20.000 ns;
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    --    tRP       : TIME    := 20.000 ns;
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    --    tRRD      : TIME    := 15.000 ns;
210 
    --    tWR       : TIME    := 15.000 ns;
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        addr_bits : INTEGER := 13;
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        data_bits : INTEGER := 16;
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    --    cols_bits : INTEGER :=  9;
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    --    index     : INTEGER :=  0;
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          --    fname     : string := "sdram.srec";     -- File to read from
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        bbits     : INTEGER :=  32
217 
    );
218 
    PORT (
219 
        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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        Dqs   : INOUT STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0) := "ZZZZ";
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        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
222 
        Ba    : IN    STD_LOGIC_VECTOR (1 DOWNTO 0);
223 
        Clk   : IN    STD_LOGIC;
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        Clk_n : IN    STD_LOGIC;
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        Cke   : IN    STD_LOGIC;
226 
        Cs_n  : IN    STD_LOGIC;
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        Ras_n : IN    STD_LOGIC;
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        Cas_n : IN    STD_LOGIC;
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        We_n  : IN    STD_LOGIC;
230 
        Dm    : IN    STD_LOGIC_VECTOR (data_bits/8 - 1 DOWNTO 0)
231 
    );
232 
  END component;
233 
 
234 
  component mobile_sdr
235 
    GENERIC (
236 
        DEBUG     : INTEGER := 1;
237 
        addr_bits : INTEGER := 13;
238 
        data_bits : INTEGER := 16
239 
    );
240 
    PORT (
241 
        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
242 
        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
243 
        Ba    : IN    STD_LOGIC_VECTOR := "00";
244 
        Clk   : IN    STD_LOGIC := '0';
245 
        Cke   : IN    STD_LOGIC := '1';
246 
        Cs_n  : IN    STD_LOGIC := '1';
247 
        Ras_n : IN    STD_LOGIC := '1';
248 
        Cas_n : IN    STD_LOGIC := '1';
249 
        We_n  : IN    STD_LOGIC := '1';
250 
        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
251 
    );
252 
  end component;
253 
 
254 
end;
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-- pragma translate_on

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