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/**************************************************************************

*

*    File Name:  model.v

*      Version:  4.0

*         Date:  Jul 12 2006

*        Model:  BUS Functional

*    Simulator:  Model Technology

*

* Dependencies:  None

*

*        Email:  modelsupport@micron.com

*      Company:  Micron Technology, Inc.

*        Model:  Mobile SDR

*

*  Description:  Micron Mobile SDRAM Verilog model

*

*   Limitation:  - Doesn't check for 4096 cycle refresh

*

*         Note:  - Set simulator resolution to "ps" accuracy

*                - Set Debug = 0 to disable $display messages

*

*  [Disclaimer]

*  This software code and all associated documentation, comments

*  or other information (collectively "Software") is provided

*  "AS IS" without warranty of any kind. MICRON TECHNOLOGY, INC.

*  ("MTI") EXPRESSLY DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED,

*  INCLUDING BUT NOT LIMITED TO, NONINFRINGEMENT OF THIRD PARTY

*  RIGHTS, AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS

*  FOR ANY PARTICULAR PURPOSE. MTI DOES NOT WARRANT THAT THE

*  SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF

*  THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. FURTHERMORE,

*  MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR THE

*  RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,

*  ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT

*  OF USE OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO

*  EVENT SHALL MTI, ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE

*  LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR

*  SPECIAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS

*  OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION)

*  ARISING OUT OF YOUR USE OF OR INABILITY TO USE THE SOFTWARE,

*  EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

*  Because some jurisdictions prohibit the exclusion or limitation

*  of liability for consequential or incidental damages, the above

*  limitation may not apply to you.

*

*  Copyright © 2001-2006 Micron Technology, Inc. All rights reserved.

*

*

* Rev  Author          Date        Changes

* ---  --------------------------  ---------------------------------------

* 4.20 bas             10/11/2006  - Changed tRRD check to use tCK min based on CL

* 4.17 bas             10/10/2006  - fixed read problem during CL3 BL1 related to read w/autoprecharge followed by activate to the same bank causing read from incorrect row, updated parameter sheets

* 4.16 bas             09/27/2006  - fixed tRRD check for parts spec using # of clks instead of ns delay

* 4.15 bas             09/26/2006  - Wrote WRap & RDap code to use #delay due to non-freerunning clock operation, fixed tRP, fixed WRap/RDap interrupt operation

* 4.12 bas             09/08/2006  - Removed realtime array instantiations of variables for NCVerilog

* 4.11 bas             09/07/2006  - tHZ issue, read DQM issue, write/read to precharged bank error(data was still being written), tRP during WRaP issue, RP option added, part selection added

* 4.1  bas             08/23/2006  - fixed masking and tHZ timing issue

* 4.0  bh              07/12/2006  - merged MT48H16M16LF & MT48H32M16LF to create single model file for all types & densities

* 3.2  dritz           11/04/2005  - Fixed Driver Strength bits

* 3.1  dritz           09/22/2005  - Fixed dqm bits to be [1:0] and tb.v as well

* 3.0  dritz           06/28/2005  - MT48H32M16LF

* 2.1  dritz           03/23/2005  - MT48LC8M32LF Fixed dqm mask bits and functionality

* 2.0  dritz           01/11/2005  - MT48LC8M32B2

* 1.0  NB              07/14/2004  - MT48M16LF

*

**************************************************************************/

`timescale 1ps / 1ps

module mobile_sdr (

    clk   ,

    cke   ,

    addr  ,

    ba    ,

    cs_n  ,

    ras_n ,

    cas_n ,

    we_n  ,

    dq    ,

    dqm

    );

//------------- Include Statements -------------

//`include "mobile_sdr_parameters.vh"

/****************************************************************************************

*

*   Disclaimer   This software code and all associated documentation, comments or other

*  of Warranty:  information (collectively "Software") is provided "AS IS" without

*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY

*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED

*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES

*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT

*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE

*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.

*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR

*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,

*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE

*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,

*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,

*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,

*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,

*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE

*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

*                DAMAGES. Because some jurisdictions prohibit the exclusion or

*                limitation of liability for consequential or incidental damages, the

*                above limitation may not apply to you.

*

*                Copyright 2005 Micron Technology, Inc. All rights reserved.

*

****************************************************************************************/

    // Timing parameters based on Speed Grade and part type (Y47M) 03/07

`define sg6

                                          // SYMBOL UNITS DESCRIPTION

                                          // ------ ----- -----------

`ifdef sg6                                 //              Timing Parameters for -75 (CL = 3)

    parameter tCK              =     6000; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK3_min         =     6000; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK2_min         =     9600; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK1_min         =        0; // tCK    ps    Nominal Clock Cycle Time

    parameter tAC3             =     5000; // tAC3   ps    Access time from CLK (pos edge) CL = 3

    parameter tAC2             =     8000; // tAC2   ps    Access time from CLK (pos edge) CL = 2

    parameter tAC1             =        0; // tAC1   ps    Parameter definition for compilation - CL = 1 illegal for sg75

    parameter tHZ3             =     5000; // tHZ3   ps    Data Out High Z time - CL = 3

    parameter tHZ2             =     8000; // tHZ2   ps    Data Out High Z time - CL = 2

    parameter tHZ1             =        0; // tHZ1   ps    Parameter definition for compilation - CL = 1 illegal for sg75

    parameter tOH              =     2500; // tOH    ps    Data Out Hold time

    parameter tMRD             =        2; // tMRD   tCK   Load Mode Register command cycle time (2 * tCK)

    parameter tRAS             =    42000; // tRAS   ps    Active to Precharge command time

    parameter tRC              =    60000; // tRC    ps    Active to Active/Auto Refresh command time

    parameter tRFC             =    97500; // tRFC   ps    Refresh to Refresh Command interval time

    parameter tRCD             =    18000; // tRCD   ps    Active to Read/Write command time

    parameter tRP              =    18000; // tRP    ps    Precharge command period

    parameter tRRD             =        2; // tRRD   tCK   Active bank a to Active bank b command time

    parameter tWRa             =     7500; // tWR    ps    Write recovery time (auto-precharge mode - must add 1 CLK)

    parameter tWRm             =    15000; // tWR    ps    Write recovery time

    parameter tCH              =     2600; // tCH    ps    Clock high level width

    parameter tCL              =     2600; // tCL    ps    Clock low level width

    parameter tXSR             =   120000; // tXSR   ps    Clock low level width

`else `ifdef sg75                          //              Timing Parameters for -8 (CL = 3)

    parameter tCK              =     7500; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK3_min         =     7500; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK2_min         =     9600; // tCK    ps    Nominal Clock Cycle Time

    parameter tCK1_min         =        0; // tCK    ps    Nominal Clock Cycle Time

    parameter tAC3             =     5400; // tAC3   ps    Access time from CLK (pos edge) CL = 3

    parameter tAC2             =     8000; // tAC2   ps    Access time from CLK (pos edge) CL = 2

    parameter tAC1             =        0; // tAC1   ps    Access time from CLK (pos edge) CL = 1

    parameter tHZ3             =     5400; // tHZ3   ps    Data Out High Z time - CL = 3

    parameter tHZ2             =     8000; // tHZ2   ps    Data Out High Z time - CL = 2

    parameter tHZ1             =        0; // tHZ1   ps    Data Out High Z time - CL = 1

    parameter tOH              =     2500; // tOH    ps    Data Out Hold time

    parameter tMRD             =        2; // tMRD   tCK   Load Mode Register command cycle time (2 * tCK)

    parameter tRAS             =    45000; // tRAS   ps    Active to Precharge command time

    parameter tRC              =    67500; // tRC    ps    Active to Active/Auto Refresh command time

    parameter tRFC             =    97500; // tRFC   ps    Refresh to Refresh Command interval time

    parameter tRCD             =    19200; // tRCD   ps    Active to Read/Write command time

    parameter tRP              =    19200; // tRP    ps    Precharge command period

    parameter tRRD             =        2; // tRRD   tCK   Active bank a to Active bank b command time (2 * tCK)

    parameter tWRa             =     7500; // tWR    ps    Write recovery time (auto-precharge mode - must add 1 CLK)

    parameter tWRm             =    15000; // tWR    ps    Write recovery time

    parameter tCH              =     3000; // tCH    ps    Clock high level width

    parameter tCL              =     3000; // tCL    ps    Clock low level width

    parameter tXSR             =   120000; // tXSR   ps    Clock low level width

`endif `endif

    // Size Parameters based on Part Width

`define x16

`ifdef x32

    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used

    parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used

    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used

    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used

    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used

    parameter BA_BITS          =       2; // Bank bits

`else `ifdef x16

    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used

    parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used

    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used

    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used

    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used

    parameter BA_BITS          =       2; // Bank bits

`endif `endif

    // Other Parameters

    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used

    parameter part_mem_bits    = 10;                         // For fast sim load

    parameter part_size        = 256;                        // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)

//------------- Define Statements --------------

`define BANKS      (1<<BA_BITS)

`define PAGE_SIZE  (1<<COL_BITS)

//------------- Parameters (cke, addr[10], cs_n, ras_n, cas_n, we_n) --------------

    parameter NOP              = 6'b100111 ;

    parameter ACTIVATE         = 6'b100011 ;

    parameter READ             = 6'b100101 ;

    parameter READ_AP          = 6'b110101 ;

    parameter READ_SUSPEND     = 6'b000101 ;

    parameter READ_AP_SUSPEND  = 6'b010101 ;

    parameter WRITE            = 6'b100100 ;

    parameter WRITE_AP         = 6'b110100 ;

    parameter WRITE_SUSPEND    = 6'b000100 ;

    parameter WRITE_AP_SUSPEND = 6'b010100 ;

    parameter BURST_TERMINATE  = 6'b100110 ;

    parameter POWER_DOWN_CI    = 6'b001111 ;

    parameter POWER_DOWN_NOP   = 6'b000111 ;

    parameter DEEP_POWER_DOWN  = 6'b000110 ;

    parameter PRECHARGE        = 6'b100010 ;

    parameter PRECHARGE_ALL    = 6'b110010 ;

    parameter AUTO_REFRESH     = 6'b100001 ;

    parameter SELF_REFRESH     = 6'b000001 ;

    parameter LOAD_MODE        = 6'b100000 ;

    parameter CKE_DISABLE      = 6'b011111 ;

    parameter DEBUG = 1             ;

//----------------------------------------

// Error codes and reporting

//----------------------------------------

    parameter   ERR_MAX_REPORTED =       -1; // >0 = report errors up to ERR_MAX_REPORTED, <0 = report all errors

    parameter   ERR_MAX          =       -1; // >0 = stop the simulation after ERR_MAX has been reached, <0 = never stop the simulation

    parameter   MSGLENGTH        =      256;

    parameter   ERR_CODES        =       16; // track up to 44 different error codes

    // Enumerated error codes (0 = unused)

    parameter   ERR_MISC         =        1;

    parameter   ERR_CMD          =        2;

    parameter   ERR_STATUS       =        3;

    parameter   ERR_tMRD         =        4;

    parameter   ERR_tRAS         =        5;

    parameter   ERR_tRC          =        6;

    parameter   ERR_tRFC         =        7;

    parameter   ERR_tRCD         =        8;

    parameter   ERR_tRP          =        9;

    parameter   ERR_tRRD         =       11;

    parameter   ERR_tWR          =       12;

    parameter   ERR_tCH          =       13;

    parameter   ERR_tCL          =       14;

    parameter   ERR_tXSR         =       15;

    parameter   ERR_tCK_MIN      =       16;

    wire [ERR_CODES : 1] EXP_ERR                  ;

    reg  [ERR_CODES : 1] errcount                 ;

    reg       [8*12-1:0] err_strings [1:ERR_CODES];

    integer     ERR_MAX_INT      =  ERR_MAX;

    assign EXP_ERR     = {ERR_CODES {1'b0}}; // the model expects no errors.  Can only be changed for debug by 'force' statement in testbench.

//------------- Port Declarations --------------

    input                        clk   ;

    input                        cke   ;

    input    [ADDR_BITS - 1 : 0] addr  ;

    input    [BA_BITS - 1 : 0]   ba    ;

    input                        cs_n  ;

    input                        ras_n ;

    input                        cas_n ;

    input                        we_n  ;

    input    [DM_BITS - 1 : 0]   dqm   ;

    inout    [DQ_BITS - 1 : 0]   dq    ;

//------------- Register Declarations --------------

    reg      [8*MSGLENGTH:1]     msg                                      ;

    reg      [`BANKS - 1 :0]     active_bank                              ;

    reg   [ADDR_BITS - 1 :0]     activate_row            [`BANKS - 1 : 0] ;

    reg                          auto_refresh1_done                       ;

    reg  [ COL_BITS - 1 : 0]     burst_count                              ;

    reg   [COL_BITS - 1 : 0]     col_addr_burst_order  [`PAGE_SIZE-1 : 0] ;

    reg    [BA_BITS - 1 : 0]     bank_access_q         [`PAGE_SIZE+2 : 0] ;

    reg   [ROW_BITS - 1 : 0]     row_access_q          [`PAGE_SIZE+2 : 0] ;

    reg   [COL_BITS - 1 : 0]     column_access_q       [`PAGE_SIZE+2 : 0] ;

    reg             [ 1 : 0]     column_access_valid_q [`PAGE_SIZE+2 : 0] ;

    reg             [ 2 : 0]     cas_latency                              ;

    reg                          write_burst_mode                         ;

    reg    [BA_BITS - 1 : 0]     interrupt_bank                           ;

    reg                          burst_type                               ;

    reg      [DQ_BITS-1 : 0]     Dq_out                                   ;

    reg      [DQ_BITS-1 : 0]     Dq_out_tAC                               ;

    reg    [DQ_BITS - 1 : 0]     mdata                                    ;

    reg         [`BANKS-1:0]     ap_set                                   ;

    reg                          cke_q                                    ;

    reg    [DM_BITS - 1 : 0]     dqm_q                                    ;

    reg             [ 1 : 0]     dqm_rtw_chk                              ;

    reg                          Sys_clk                                  ;

    reg              [3 : 0]     initialization_state                     ;

    reg                          self_refresh_enter                       ;

    reg                          power_down_enter                         ;

    reg                          command_sequence_error                   ;

    reg                          read_write_in_progress                   ;

    // Memory Banks

    `ifdef FULL_MEM

        reg  [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1];

    `else

        reg   [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1];

        reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];

        reg   [part_mem_bits     : 0] mem_used;

        reg   [part_mem_bits     : 0] memory_index;

        initial mem_used = 0;

    `endif

//------------- Integer Declarations --------------

    integer                      ck_cntr_initial                          ;

    integer                      ck_cntr_activate                         ;

    integer                      ck_cntr_read                             ;

    integer                      ck_cntr_read_ap                          ;

    integer                      ck_cntr_write                            ;

    integer                      ck_cntr_write_ap                         ;

    integer                      ck_cntr_burst_terminate                  ;

    integer                      ck_cntr_precharge                        ;

    integer                      ck_cntr_auto_refresh                     ;

    integer                      ck_cntr_self_refresh                     ;

    integer                      ck_cntr_power_down                       ;

    integer                      ck_cntr_clock_suspend                    ;

    integer                      ck_cntr_deep_power_down                  ;

    integer                      ck_cntr_load_mode                        ;

    integer                      ck_cntr_cke                              ;

    integer                      ck_cntr_cke_n                            ;

    integer                      ck_cntr_cke_high                         ;

    integer                      ck_cntr_bank_precharge      [`BANKS-1:0] ;

    integer                      ck_cntr_bank_activate       [`BANKS-1:0] ;

    integer                      ck_cntr_bank_write          [`BANKS-1:0] ;

    integer                      ck_cntr_bank_read           [`BANKS-1:0] ;

    integer                      ck_cntr_write_dq            [`BANKS-1:0] ;

    integer                      interrupt_write_ap_n        [`BANKS-1:0] ;

    integer                      interrupt_read_ap_n         [`BANKS-1:0] ;

    integer                      pasr                                     ;

    integer                      warnings                                 ;

    integer                      errors                                   ;

    integer                      burst_length                             ;

    integer                      i                                        ;

//------------- Time Declarations --------------

    time                         tm_initial                     ;

    time                         tm_activate                    ;

    time                         tm_read                        ;

    time                         tm_write                       ;

    time                         tm_burst_terminate             ;

    time                         tm_precharge                   ;

    time                         tm_auto_refresh                ;

    time                         tm_self_refresh                ;

    time                         tm_power_down                  ;

    time                         tm_clock_suspend               ;

    time                         tm_deep_power_down             ;

    time                         tm_load_mode                   ;

    time                         tm_bank_precharge [`BANKS-1:0] ;

    time                         tm_bank_activate  [`BANKS-1:0] ;

    time                         tm_bank_write     [`BANKS-1:0] ;

    time                         tm_bank_read      [`BANKS-1:0] ;

    time                         tm_write_dq       [`BANKS-1:0] ;

    time                         tm_cke                         ;

    time                         tm_cke_n                       ;

    time                         tm_cke_high                    ;

    time                         tm_clk_high_pulse_width        ;

    time                         tm_clk_low_pulse_width         ;

    time                         tm_clk_period                  ;

    time                         tm_clk_negedge                 ;

    time                         tm_clk_posedge                 ;

//------------- Wire Declarations --------------

    wire                         addr_10                        ;

    wire      [ 5 : 0]           command                        ;

//--------------------- Outputs -----------------------

    assign dq = Dq_out_tAC ;

//--------------------- Initialization -----------------------

    initial begin

        auto_refresh1_done = 1'b0           ;

        initialization_state = 4'h0         ;

        active_bank        = {`BANKS{1'b1}} ;

        Dq_out_tAC         = 'bz            ;

        tm_initial         = 0 ;

        tm_activate        = 0 ;

        tm_read            = 0 ;

        tm_write           = 0 ;

        tm_burst_terminate = 0 ;

        tm_precharge       = 0 ;

        tm_auto_refresh    = 0 ;

        tm_self_refresh    = 0 ;

        tm_power_down      = 0 ;

        tm_clock_suspend   = 0 ;

        tm_deep_power_down = 0 ;

        tm_load_mode       = 0 ;

        for (i=0; i<`BANKS; i=i+1) begin

            tm_bank_precharge[i] = 0 ;

            tm_bank_activate[i]  = 0 ;

            tm_bank_write[i]     = 0 ;

            tm_bank_read[i]      = 0 ;

            tm_write_dq[i]       = 0 ;

        end

        tm_cke                 = 0 ;

        tm_cke_n               = 0 ;

        tm_cke_high            = 0 ;

        tm_clk_period          = 0 ;

        tm_clk_low_pulse_width = 0 ;

        tm_clk_high_pulse_width= 0 ;

        tm_clk_negedge         = 0 ;

        tm_clk_posedge         = 0 ;

        tm_clk_low_pulse_width = 0 ;

        for (i=0; i<`BANKS; i=i+1) begin

            ap_set[i] = 1'b0 ;

        end

        ck_cntr_initial         = 100;

        ck_cntr_activate        = 100;

        ck_cntr_read            = 100;

        ck_cntr_read_ap         = 100;

        ck_cntr_write           = 100;

        ck_cntr_write_ap        = 100;

        ck_cntr_burst_terminate = 100;

        ck_cntr_precharge       = 100;

        ck_cntr_auto_refresh    = 100;

        ck_cntr_self_refresh    = 100;

        ck_cntr_power_down      = 100;

        ck_cntr_clock_suspend   = 100;

        ck_cntr_deep_power_down = 100;

        ck_cntr_load_mode       = 100;

        ck_cntr_cke             = 100;

        ck_cntr_cke_n           = 100;

        ck_cntr_cke_high        = 100;

        for (i=0; i<`BANKS; i=i+1) begin

            ck_cntr_bank_precharge[i] = 100;

            ck_cntr_bank_activate[i]  = 100;

            ck_cntr_bank_write[i]     = 100;

            ck_cntr_bank_read[i]      = 100;

            ck_cntr_write_dq[i]       = 100;

            interrupt_write_ap_n[i]   = 2;

            interrupt_read_ap_n[i]    = 1;

        end

        for (i=0; i<`PAGE_SIZE+3;i=i+1) begin

            bank_access_q[i] = 'bz ;

            row_access_q[i] = 'bz ;

            column_access_q[i] = 'bz ;

            column_access_valid_q[i] = 2'b00 ;

        end

        for (i=0; i<`PAGE_SIZE+3; i=i+1) begin

            column_access_valid_q[i] = 2'b00 ;

        end

        warnings = 0;

        errors = 0;

        for (i=1; i<=ERR_CODES; i=i+1) begin

            errcount[i] = 0;

        end

        self_refresh_enter      = 0;

        power_down_enter        = 0;

        command_sequence_error  = 0;

        read_write_in_progress  = 0;

        pasr                    = 0;

    end

//---------------------- Command Selection ----------------------

    assign addr_10 = addr[10] & ((cke_q & ~cs_n &  ras_n & ~cas_n &  we_n & ~(burst_length == `PAGE_SIZE) ) |  // Read w/ap

                                 (cke_q & ~cs_n &  ras_n & ~cas_n & ~we_n & ~(burst_length == `PAGE_SIZE) ) |  // Write w/ap

                                 (cke_q & ~cs_n & ~ras_n &  cas_n & ~we_n                                 ) ); // Precharge all

//    assign command = ({cke, addr_10, cs_n, (ras_n | cs_n), (cas_n | cs_n), (we_n | cs_n)} & {cke_q, {5{1'b1}}}) | {1'b0, {5{~cke_q}}};

    assign command = {cke, addr_10, cs_n, (ras_n | cs_n), (cas_n | cs_n), (we_n | cs_n)} ;

//---------------------- Mode Register Selection ----------------------

    task set_mode_reg;

    begin

        // Burst Length selection

        if (addr[2:0] == 3'b000) begin

            burst_length = 1 ;

        end else if (addr[2:0] == 3'b001) begin

            burst_length = 2 ;

        end else if (addr[2:0] == 3'b010) begin

            burst_length = 4 ;

        end else if (addr[2:0] == 3'b011) begin

            burst_length = 8 ;

        end else if (addr[2:0] == 3'b111) begin

            burst_length = `PAGE_SIZE ;

        end else begin

            burst_length = 0 ;

        end

        burst_type = addr[3] ;

        cas_latency = addr[6:4] ;

        write_burst_mode = addr[9] ;

    end

    endtask

    task set_ext_mode_reg;

    begin

        // PASR selection

        if (addr[2:0] == 3'b000) begin

            pasr = 0 ;

        end else if (addr[2:0] == 3'b001) begin

            pasr = 1 ;

        end else if (addr[2:0] == 3'b010) begin

            pasr = 2 ;

        end else if (addr[2:0] == 3'b101) begin

            pasr = 3 ;

        end else if (addr[2:0] == 3'b110) begin

            pasr = 4 ;

        end else begin

            pasr = 5 ;

        end

    end

    endtask

    task column_burst_order;

    begin

        burst_count = 0 ;

        for (i=0; i<burst_length; i=i+1) begin

            if (burst_length == `PAGE_SIZE) begin

                if (burst_type == 1'b0) begin

                    col_addr_burst_order[i] = addr[COL_BITS-1:0] + burst_count ;

                end else if (burst_type == 1'b1) begin

                    col_addr_burst_order[i] = {COL_BITS{1'bx}} ;

                end

            end else if (burst_length == 1) begin

                if (burst_type == 1'b0) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2:0]} ;

                end else if (burst_type == 1'b1) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2:0]} ;

                end

            end else if (burst_length == 2) begin

                if (burst_type == 1'b0) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2:1], (burst_count[0] + addr[0])} ;

                end else if (burst_type == 1'b1) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2:1], (burst_count[0] ^ addr[0])} ;

                end

            end else if (burst_length == 4) begin

                if (burst_type == 1'b0) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2], (burst_count[1:0] + addr[1:0])} ;

                end else if (burst_type == 1'b1) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], addr[2], (burst_count[1:0] ^ addr[1:0])} ;

                end

            end else if (burst_length == 8) begin

                if (burst_type == 1'b0) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], (burst_count[2:0] + addr[2:0])} ;

                end else if (burst_type == 1'b1) begin

                    col_addr_burst_order[i] = {addr[COL_BITS-1:3], (burst_count[2:0] ^ addr[2:0])} ;

                end

            end

            burst_count = burst_count + 1'b1 ;

        end

    end

    endtask

//---------------------- Memory Address Queue ----------------------

    task column_address_read_queue;

    begin

        for (i=0; i<burst_length;i=i+1) begin

            bank_access_q[cas_latency-1+i] = ba ;

            row_access_q[cas_latency-1+i] = activate_row[ba] ;

            column_access_q[cas_latency-1+i] = col_addr_burst_order[i] ;

            column_access_valid_q[cas_latency-1+i] = 2'b10 ;

        end

        if (burst_length < `PAGE_SIZE) begin

            for (i=burst_length; i< (burst_length+cas_latency-1);i=i+1) begin

                bank_access_q[cas_latency-1+i] = 'bz ;

                row_access_q[cas_latency-1+i] = 'bz ;

                column_access_q[cas_latency-1+i] = 'bz ;

                column_access_valid_q[cas_latency-1+i] = 2'b00 ;

            end

        end

    end

    endtask

    task column_address_write_queue;

    begin

        for (i=0; i<burst_length;i=i+1) begin

            bank_access_q[i] = ba ;

            row_access_q[i] = activate_row[ba] ;

            column_access_q[i] = col_addr_burst_order[i] ;

            column_access_valid_q[i] = 2'b01 ;

        end

        if (burst_length < `PAGE_SIZE) begin

            for (i=burst_length; i<(burst_length+cas_latency-1);i=i+1) begin

                bank_access_q[i] = 'bz ;

                row_access_q[i] = 'bz ;

                column_access_q[i] = 'bz ;

                column_access_valid_q[i] = 2'b00 ;

            end

        end

    end

    endtask

    task burst_term_read_queue;

    begin

        for (i=0; i<burst_length;i=i+1) begin

            bank_access_q[cas_latency-1+i]         =   'bz ;

            row_access_q[cas_latency-1+i]          =   'bz ;