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dimamali |
---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2000 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- Package containing i2c master byte controller component. Component
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-- declaration separated into this file by jan@gaisler.com.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package i2coc is
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component i2c_master_byte_ctrl is
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port (
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clk : in std_logic;
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rst : in std_logic; -- active high reset
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nReset : in std_logic; -- asynchornous active low reset
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-- (not used in GRLIB)
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ena : in std_logic; -- core enable signal
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clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
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-- input signals
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start,
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stop,
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read,
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write,
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ack_in : std_logic;
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din : in std_logic_vector(7 downto 0);
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-- output signals
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cmd_ack : out std_logic;
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ack_out : out std_logic;
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i2c_busy : out std_logic;
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i2c_al : out std_logic;
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dout : out std_logic_vector(7 downto 0);
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-- i2c lines
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scl_i : in std_logic; -- i2c clock line input
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scl_o : out std_logic; -- i2c clock line output
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scl_oen : out std_logic; -- i2c clock line output enable, active low
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sda_i : in std_logic; -- i2c data line input
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sda_o : out std_logic; -- i2c data line output
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sda_oen : out std_logic -- i2c data line output enable, active low
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);
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end component i2c_master_byte_ctrl;
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end;
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