1 |
2 |
dimamali |
------------------------------------------------------------------------------
|
2 |
|
|
-- This file is a part of the GRLIB VHDL IP LIBRARY
|
3 |
|
|
-- Copyright (C) 2003, Gaisler Research
|
4 |
|
|
--
|
5 |
|
|
-- This program is free software; you can redistribute it and/or modify
|
6 |
|
|
-- it under the terms of the GNU General Public License as published by
|
7 |
|
|
-- the Free Software Foundation; either version 2 of the License, or
|
8 |
|
|
-- (at your option) any later version.
|
9 |
|
|
--
|
10 |
|
|
-- This program is distributed in the hope that it will be useful,
|
11 |
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
12 |
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
13 |
|
|
-- GNU General Public License for more details.
|
14 |
|
|
--
|
15 |
|
|
-- You should have received a copy of the GNU General Public License
|
16 |
|
|
-- along with this program; if not, write to the Free Software
|
17 |
|
|
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
18 |
|
|
|
19 |
|
|
library ieee;
|
20 |
|
|
use ieee.std_logic_1164.all;
|
21 |
|
|
|
22 |
|
|
package occomp is
|
23 |
|
|
|
24 |
|
|
component ac97_top
|
25 |
|
|
port(
|
26 |
|
|
clk_i : in std_logic;
|
27 |
|
|
rst_i : in std_logic;
|
28 |
|
|
wb_data_i : in std_logic_vector(31 downto 0);
|
29 |
|
|
wb_data_o : out std_logic_vector(31 downto 0);
|
30 |
|
|
wb_addr_i : in std_logic_vector(31 downto 0);
|
31 |
|
|
wb_sel_i : in std_logic_vector(3 downto 0);
|
32 |
|
|
wb_we_i : in std_logic;
|
33 |
|
|
wb_cyc_i : in std_logic;
|
34 |
|
|
wb_stb_i : in std_logic;
|
35 |
|
|
wb_ack_o : out std_logic;
|
36 |
|
|
wb_err_o : out std_logic;
|
37 |
|
|
int_o : out std_logic;
|
38 |
|
|
dma_req_o : out std_logic_vector(8 downto 0);
|
39 |
|
|
dma_ack_i : in std_logic_vector(8 downto 0);
|
40 |
|
|
suspended_o : out std_logic;
|
41 |
|
|
bit_clk_pad_i : in std_logic;
|
42 |
|
|
sync_pad_o : out std_logic;
|
43 |
|
|
sdata_pad_o : out std_logic;
|
44 |
|
|
sdata_pad_i : in std_logic;
|
45 |
|
|
ac97_resetn_pad_o : out std_logic
|
46 |
|
|
);
|
47 |
|
|
end component;
|
48 |
|
|
|
49 |
|
|
component simple_spi_top
|
50 |
|
|
port (
|
51 |
|
|
prdata_o : out std_logic_vector(7 downto 0);
|
52 |
|
|
pirq_o : out std_logic;
|
53 |
|
|
sck_o : out std_logic;
|
54 |
|
|
mosi_o : out std_logic;
|
55 |
|
|
ssn_o : out std_logic_vector(7 downto 0);
|
56 |
|
|
pclk_i : in std_logic;
|
57 |
|
|
prst_i : in std_logic;
|
58 |
|
|
psel_i : in std_logic;
|
59 |
|
|
penable_i : in std_logic;
|
60 |
|
|
paddr_i : in std_logic_vector(2 downto 0);
|
61 |
|
|
pwrite_i : in std_logic;
|
62 |
|
|
pwdata_i : in std_logic_vector(7 downto 0);
|
63 |
|
|
miso_i : in std_logic);
|
64 |
|
|
end component;
|
65 |
|
|
|
66 |
|
|
component ocidec2_controller
|
67 |
|
|
generic(
|
68 |
|
|
TWIDTH : natural := 8; -- counter width
|
69 |
|
|
|
70 |
|
|
-- PIO mode 0 settings (@100MHz clock)
|
71 |
|
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
72 |
|
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
73 |
|
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
74 |
|
|
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
75 |
|
|
);
|
76 |
|
|
port(
|
77 |
|
|
clk : in std_logic; -- master clock in
|
78 |
|
|
nReset : in std_logic := '1'; -- asynchronous active low reset
|
79 |
|
|
rst : in std_logic := '0'; -- synchronous active high reset
|
80 |
|
|
|
81 |
|
|
irq : out std_logic; -- interrupt request signal
|
82 |
|
|
|
83 |
|
|
-- control / registers
|
84 |
|
|
IDEctrl_rst,
|
85 |
|
|
IDEctrl_IDEen,
|
86 |
|
|
IDEctrl_FATR0,
|
87 |
|
|
IDEctrl_FATR1 : in std_logic;
|
88 |
|
|
|
89 |
|
|
-- PIO registers
|
90 |
|
|
cmdport_T1,
|
91 |
|
|
cmdport_T2,
|
92 |
|
|
cmdport_T4,
|
93 |
|
|
cmdport_Teoc : in std_logic_vector(7 downto 0);
|
94 |
|
|
cmdport_IORDYen : in std_logic; -- PIO command port / non-fast timing
|
95 |
|
|
|
96 |
|
|
dport0_T1,
|
97 |
|
|
dport0_T2,
|
98 |
|
|
dport0_T4,
|
99 |
|
|
dport0_Teoc : in std_logic_vector(7 downto 0);
|
100 |
|
|
dport0_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 0
|
101 |
|
|
|
102 |
|
|
dport1_T1,
|
103 |
|
|
dport1_T2,
|
104 |
|
|
dport1_T4,
|
105 |
|
|
dport1_Teoc : in std_logic_vector(7 downto 0);
|
106 |
|
|
dport1_IORDYen : in std_logic; -- PIO mode data-port / fast timing device 1
|
107 |
|
|
|
108 |
|
|
PIOreq : in std_logic; -- PIO transfer request
|
109 |
|
|
PIOack : out std_logic; -- PIO transfer ended
|
110 |
|
|
PIOa : in std_logic_vector(3 downto 0); -- PIO address
|
111 |
|
|
PIOd : in std_logic_vector(15 downto 0); -- PIO data in
|
112 |
|
|
PIOq : out std_logic_vector(15 downto 0); -- PIO data out
|
113 |
|
|
PIOwe : in std_logic; -- PIO direction bit '1'=write, '0'=read
|
114 |
|
|
|
115 |
|
|
-- ATA signals
|
116 |
|
|
RESETn : out std_logic;
|
117 |
|
|
DDi : in std_logic_vector(15 downto 0);
|
118 |
|
|
DDo : out std_logic_vector(15 downto 0);
|
119 |
|
|
DDoe : out std_logic;
|
120 |
|
|
DA : out std_logic_vector(2 downto 0);
|
121 |
|
|
CS0n : out std_logic;
|
122 |
|
|
CS1n : out std_logic;
|
123 |
|
|
|
124 |
|
|
DIORn : out std_logic;
|
125 |
|
|
DIOWn : out std_logic;
|
126 |
|
|
IORDY : in std_logic;
|
127 |
|
|
INTRQ : in std_logic
|
128 |
|
|
);
|
129 |
|
|
end component ocidec2_controller;
|
130 |
|
|
|
131 |
|
|
component atahost_controller
|
132 |
|
|
generic(
|
133 |
|
|
tech : integer := 0; -- fifo mem technology
|
134 |
|
|
fdepth : integer := 8; -- DMA fifo depth
|
135 |
|
|
TWIDTH : natural := 8; -- counter width
|
136 |
|
|
|
137 |
|
|
-- PIO mode 0 settings (@100MHz clock)
|
138 |
|
|
PIO_mode0_T1 : natural := 6; -- 70ns
|
139 |
|
|
PIO_mode0_T2 : natural := 28; -- 290ns
|
140 |
|
|
PIO_mode0_T4 : natural := 2; -- 30ns
|
141 |
|
|
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
142 |
|
|
|
143 |
|
|
-- Multiword DMA mode 0 settings (@100MHz clock)
|
144 |
|
|
DMA_mode0_Tm : natural := 4; -- 50ns
|
145 |
|
|
DMA_mode0_Td : natural := 21; -- 215ns
|
146 |
|
|
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
|
147 |
|
|
);
|
148 |
|
|
port(
|
149 |
|
|
clk : in std_logic; -- master clock in
|
150 |
|
|
nReset : in std_logic := '1'; -- asynchronous active low reset
|
151 |
|
|
rst : in std_logic := '0'; -- synchronous active high reset
|
152 |
|
|
|
153 |
|
|
irq : out std_logic; -- interrupt request signal
|
154 |
|
|
|
155 |
|
|
-- control / registers
|
156 |
|
|
IDEctrl_IDEen,
|
157 |
|
|
IDEctrl_rst,
|
158 |
|
|
IDEctrl_ppen,
|
159 |
|
|
IDEctrl_FATR0,
|
160 |
|
|
IDEctrl_FATR1 : in std_logic; -- control register settings
|
161 |
|
|
|
162 |
|
|
a : in std_logic_vector(3 downto 0); -- address input
|
163 |
|
|
d : in std_logic_vector(31 downto 0); -- data input
|
164 |
|
|
we : in std_logic; -- write enable input '1'=write, '0'=read
|
165 |
|
|
|
166 |
|
|
-- PIO registers
|
167 |
|
|
PIO_cmdport_T1,
|
168 |
|
|
PIO_cmdport_T2,
|
169 |
|
|
PIO_cmdport_T4,
|
170 |
|
|
PIO_cmdport_Teoc : in std_logic_vector(7 downto 0);
|
171 |
|
|
PIO_cmdport_IORDYen : in std_logic; -- PIO compatible timing settings
|
172 |
|
|
|
173 |
|
|
PIO_dport0_T1,
|
174 |
|
|
PIO_dport0_T2,
|
175 |
|
|
PIO_dport0_T4,
|
176 |
|
|
PIO_dport0_Teoc : in std_logic_vector(7 downto 0);
|
177 |
|
|
PIO_dport0_IORDYen : in std_logic; -- PIO data-port device0 timing settings
|
178 |
|
|
|
179 |
|
|
PIO_dport1_T1,
|
180 |
|
|
PIO_dport1_T2,
|
181 |
|
|
PIO_dport1_T4,
|
182 |
|
|
PIO_dport1_Teoc : in std_logic_vector(7 downto 0);
|
183 |
|
|
PIO_dport1_IORDYen : in std_logic; -- PIO data-port device1 timing settings
|
184 |
|
|
|
185 |
|
|
PIOsel : in std_logic; -- PIO controller select
|
186 |
|
|
PIOack : out std_logic; -- PIO controller acknowledge
|
187 |
|
|
PIOq : out std_logic_vector(15 downto 0); -- PIO data out
|
188 |
|
|
PIOtip : out std_logic :='0'; -- PIO transfer in progress
|
189 |
|
|
PIOpp_full : out std_logic; -- PIO Write PingPong full
|
190 |
|
|
|
191 |
|
|
-- DMA registers
|
192 |
|
|
DMA_dev0_Td,
|
193 |
|
|
DMA_dev0_Tm,
|
194 |
|
|
DMA_dev0_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device0
|
195 |
|
|
|
196 |
|
|
DMA_dev1_Td,
|
197 |
|
|
DMA_dev1_Tm,
|
198 |
|
|
DMA_dev1_Teoc : in std_logic_vector(7 downto 0); -- DMA timing settings for device1
|
199 |
|
|
|
200 |
|
|
DMActrl_DMAen,
|
201 |
|
|
DMActrl_dir,
|
202 |
|
|
DMActrl_Bytesw, --Jagre 2006-12-04 byte swap ATA data
|
203 |
|
|
DMActrl_BeLeC0,
|
204 |
|
|
DMActrl_BeLeC1 : in std_logic; -- DMA settings
|
205 |
|
|
|
206 |
|
|
DMAsel : in std_logic; -- DMA controller select
|
207 |
|
|
DMAack : out std_logic; -- DMA controller acknowledge
|
208 |
|
|
DMAq : out std_logic_vector(31 downto 0); -- DMA data out
|
209 |
|
|
DMAtip_out : out std_logic; -- DMA transfer in progress --Erik Jagre 2006-11-15
|
210 |
|
|
DMA_dmarq : out std_logic; -- Synchronized ATA DMARQ line
|
211 |
|
|
|
212 |
|
|
force_rdy : in std_logic; -- DMA transmit fifo filled up partly --Erik Jagre 2006-10-31
|
213 |
|
|
fifo_rdy : out std_logic; -- DMA transmit fifo filled up --Erik Jagre 2006-10-30
|
214 |
|
|
DMARxEmpty : out std_logic; -- DMA receive buffer empty
|
215 |
|
|
DMARxFull : out std_logic; -- DMA receive fifo full Erik Jagre 2006-10-31
|
216 |
|
|
|
217 |
|
|
DMA_req : out std_logic; -- DMA request to external DMA engine
|
218 |
|
|
DMA_ack : in std_logic; -- DMA acknowledge from external DMA engine
|
219 |
|
|
BM_en : in std_logic; -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
|
220 |
|
|
|
221 |
|
|
-- ATA signals
|
222 |
|
|
RESETn : out std_logic;
|
223 |
|
|
DDi : in std_logic_vector(15 downto 0);
|
224 |
|
|
DDo : out std_logic_vector(15 downto 0);
|
225 |
|
|
DDoe : out std_logic;
|
226 |
|
|
DA : out std_logic_vector(2 downto 0) := "000";
|
227 |
|
|
CS0n : out std_logic;
|
228 |
|
|
CS1n : out std_logic;
|
229 |
|
|
|
230 |
|
|
DMARQ : in std_logic;
|
231 |
|
|
DMACKn : out std_logic;
|
232 |
|
|
DIORn : out std_logic;
|
233 |
|
|
DIOWn : out std_logic;
|
234 |
|
|
IORDY : in std_logic;
|
235 |
|
|
INTRQ : in std_logic
|
236 |
|
|
);
|
237 |
|
|
end component;
|
238 |
|
|
|
239 |
|
|
component ata_device_oc is
|
240 |
|
|
port(
|
241 |
|
|
ata_rst_n : in std_logic;
|
242 |
|
|
ata_data : inout std_logic_vector(15 downto 0);
|
243 |
|
|
ata_da : in std_logic_vector(2 downto 0);
|
244 |
|
|
ata_cs0 : in std_logic;
|
245 |
|
|
ata_cs1 : in std_logic;
|
246 |
|
|
ata_dior_n : in std_logic;
|
247 |
|
|
ata_diow_n : in std_logic;
|
248 |
|
|
ata_iordy : out std_logic;
|
249 |
|
|
ata_intrq : out std_logic
|
250 |
|
|
);
|
251 |
|
|
end component;
|
252 |
|
|
|
253 |
|
|
end;
|