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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: grspw_gen
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-- File: grspw_gen.vhd
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-- Author: Marko Isomaki - Gaisler Research
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-- Description: Generic GRSPW core
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library spw;
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use spw.spwcomp.all;
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entity grspw_gen is
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generic(
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tech : integer := 0;
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sysfreq : integer := 10000;
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usegen : integer range 0 to 1 := 1;
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nsync : integer range 1 to 2 := 1;
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rmap : integer range 0 to 1 := 0;
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rmapcrc : integer range 0 to 1 := 0;
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fifosize1 : integer range 4 to 32 := 32;
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fifosize2 : integer range 16 to 64 := 64;
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rxclkbuftype : integer range 0 to 2 := 0;
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rxunaligned : integer range 0 to 1 := 0;
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rmapbufs : integer range 2 to 8 := 4;
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ft : integer range 0 to 2 := 0;
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scantest : integer range 0 to 1 := 0;
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techfifo : integer range 0 to 1 := 1;
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ports : integer range 1 to 2 := 1;
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memtech : integer := 0
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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txclk : in std_ulogic;
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--ahb mst in
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hgrant : in std_ulogic;
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hready : in std_ulogic;
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hresp : in std_logic_vector(1 downto 0);
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hrdata : in std_logic_vector(31 downto 0);
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--ahb mst out
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hbusreq : out std_ulogic;
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hlock : out std_ulogic;
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htrans : out std_logic_vector(1 downto 0);
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haddr : out std_logic_vector(31 downto 0);
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hwrite : out std_ulogic;
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hsize : out std_logic_vector(2 downto 0);
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hburst : out std_logic_vector(2 downto 0);
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hprot : out std_logic_vector(3 downto 0);
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hwdata : out std_logic_vector(31 downto 0);
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--apb slv in
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psel : in std_ulogic;
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penable : in std_ulogic;
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paddr : in std_logic_vector(31 downto 0);
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pwrite : in std_ulogic;
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pwdata : in std_logic_vector(31 downto 0);
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--apb slv out
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prdata : out std_logic_vector(31 downto 0);
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--spw in
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di : in std_logic_vector(1 downto 0);
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si : in std_logic_vector(1 downto 0);
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--spw out
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do : out std_logic_vector(1 downto 0);
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so : out std_logic_vector(1 downto 0);
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--time iface
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tickin : in std_ulogic;
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tickout : out std_ulogic;
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--irq
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irq : out std_logic;
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--misc
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clkdiv10 : in std_logic_vector(7 downto 0);
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dcrstval : in std_logic_vector(9 downto 0);
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timerrstval : in std_logic_vector(11 downto 0);
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--rmapen
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rmapen : in std_ulogic;
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linkdis : out std_ulogic;
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testclk : in std_ulogic := '0';
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testrst : in std_ulogic := '0';
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testen : in std_ulogic := '0'
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);
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end entity;
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architecture rtl of grspw_gen is
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constant fabits1 : integer := log2(fifosize1);
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constant fabits2 : integer := log2(fifosize2);
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constant rfifo : integer := 5 + log2(rmapbufs);
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signal rxclki, nrxclki, rxclko : std_logic_vector(1 downto 0);
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--rx ahb fifo
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signal rxrenable : std_ulogic;
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signal rxraddress : std_logic_vector(4 downto 0);
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signal rxwrite : std_ulogic;
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signal rxwdata : std_logic_vector(31 downto 0);
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signal rxwaddress : std_logic_vector(4 downto 0);
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signal rxrdata : std_logic_vector(31 downto 0);
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--tx ahb fifo
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signal txrenable : std_ulogic;
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signal txraddress : std_logic_vector(4 downto 0);
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signal txwrite : std_ulogic;
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signal txwdata : std_logic_vector(31 downto 0);
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signal txwaddress : std_logic_vector(4 downto 0);
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signal txrdata : std_logic_vector(31 downto 0);
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--nchar fifo
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signal ncrenable : std_ulogic;
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signal ncraddress : std_logic_vector(5 downto 0);
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signal ncwrite : std_ulogic;
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signal ncwdata : std_logic_vector(8 downto 0);
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signal ncwaddress : std_logic_vector(5 downto 0);
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signal ncrdata : std_logic_vector(8 downto 0);
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--rmap buf
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signal rmrenable : std_ulogic;
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signal rmrenablex : std_ulogic;
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signal rmraddress : std_logic_vector(7 downto 0);
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signal rmwrite : std_ulogic;
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signal rmwdata : std_logic_vector(7 downto 0);
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signal rmwaddress : std_logic_vector(7 downto 0);
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signal rmrdata : std_logic_vector(7 downto 0);
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--misc
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signal rxclk, nrxclk : std_logic_vector(ports-1 downto 0);
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attribute syn_netlist_hierarchy : boolean;
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attribute syn_netlist_hierarchy of rtl : architecture is false;
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begin
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grspwc0 : grspwc
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generic map(
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sysfreq => sysfreq,
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usegen => usegen,
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nsync => nsync,
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rmap => rmap,
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rmapcrc => rmapcrc,
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fifosize1 => fifosize1,
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fifosize2 => fifosize2,
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rxunaligned => rxunaligned,
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rmapbufs => rmapbufs,
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scantest => scantest,
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ports => ports,
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tech => tech)
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port map(
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rst => rst,
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clk => clk,
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txclk => txclk,
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--ahb mst in
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hgrant => hgrant,
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hready => hready,
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hresp => hresp,
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hrdata => hrdata,
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--ahb mst out
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hbusreq => hbusreq,
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hlock => hlock,
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htrans => htrans,
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haddr => haddr,
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hwrite => hwrite,
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hsize => hsize,
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hburst => hburst,
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hprot => hprot,
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hwdata => hwdata,
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--apb slv in
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psel => psel,
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penable => penable,
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paddr => paddr,
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pwrite => pwrite,
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pwdata => pwdata,
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--apb slv out
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prdata => prdata,
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--spw in
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di => di,
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si => si,
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--spw out
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do => do,
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so => so,
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--time iface
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tickin => tickin,
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tickout => tickout,
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--clk bufs
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rxclki => rxclki,
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nrxclki => nrxclki,
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rxclko => rxclko,
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--irq
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irq => irq,
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--misc
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clkdiv10 => clkdiv10,
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dcrstval => dcrstval,
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timerrstval => timerrstval,
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--rmapen
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rmapen => rmapen,
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--rx ahb fifo
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rxrenable => rxrenable,
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rxraddress => rxraddress,
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rxwrite => rxwrite,
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rxwdata => rxwdata,
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rxwaddress => rxwaddress,
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rxrdata => rxrdata,
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--tx ahb fifo
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txrenable => txrenable,
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txraddress => txraddress,
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txwrite => txwrite,
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txwdata => txwdata,
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txwaddress => txwaddress,
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txrdata => txrdata,
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--nchar fifo
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ncrenable => ncrenable,
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ncraddress => ncraddress,
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ncwrite => ncwrite,
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ncwdata => ncwdata,
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ncwaddress => ncwaddress,
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ncrdata => ncrdata,
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--rmap buf
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rmrenable => rmrenable,
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rmraddress => rmraddress,
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rmwrite => rmwrite,
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rmwdata => rmwdata,
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rmwaddress => rmwaddress,
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rmrdata => rmrdata,
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linkdis => linkdis,
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testclk => clk,
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testrst => testrst,
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testen => testen
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);
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ntst: if scantest = 0 generate
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cloop : for i in 0 to ports-1 generate
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rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
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port map(i => rxclko(i), o => rxclki(i));
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end generate;
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rmrenablex <= rmrenable;
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end generate;
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tst: if scantest = 1 generate
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cloop : for i in 0 to ports-1 generate
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rxclk(i) <= clk when testen = '1' else rxclko(i);
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nrxclk(i) <= clk when testen = '1' else not rxclko(i);
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rx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
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port map(i => rxclk(i), o => rxclki(i));
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nrx_clkbuf : techbuf generic map(tech => tech, buftype => rxclkbuftype)
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port map(i => nrxclk(i), o => nrxclki(i));
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end generate;
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rmrenablex <= rmrenable and not testen;
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end generate;
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------------------------------------------------------------------------------
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-- FIFOS ---------------------------------------------------------------------
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------------------------------------------------------------------------------
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nft : if ft = 0 generate
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--receiver AHB FIFO
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rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
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port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
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rxrdata, clk, rxwrite,
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rxwaddress(fabits1-1 downto 0), rxwdata);
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--receiver nchar FIFO
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rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
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port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
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ncrdata, clk, ncwrite,
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ncwaddress(fabits2-1 downto 0), ncwdata);
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--transmitter FIFO
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tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
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port map(clk, txrenable, txraddress(fabits1-1 downto 0),
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txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
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--RMAP Buffer
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rmap_ram : if (rmap = 1) generate
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ram0 : syncram_2p generic map(memtech, rfifo, 8)
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port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
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rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
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rmwdata);
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end generate;
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end generate;
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ft1 : if ft /= 0 generate
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--receiver AHB FIFO
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rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
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297 |
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port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
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298 |
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rxrdata, clk, rxwrite,
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rxwaddress(fabits1-1 downto 0), rxwdata);
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300 |
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301 |
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--receiver nchar FIFO
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302 |
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rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
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303 |
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port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
|
304 |
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ncrdata, clk, ncwrite,
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305 |
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ncwaddress(fabits2-1 downto 0), ncwdata);
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306 |
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307 |
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--transmitter FIFO
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308 |
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tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
|
309 |
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port map(clk, txrenable, txraddress(fabits1-1 downto 0),
|
310 |
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txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
|
311 |
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312 |
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--RMAP Buffer
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313 |
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rmap_ram : if (rmap = 1) generate
|
314 |
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ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
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315 |
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port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
|
316 |
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rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
|
317 |
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rmwdata);
|
318 |
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end generate;
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319 |
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end generate;
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320 |
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321 |
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end architecture;
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